Xilinx Synthesis Technology User Guide

Verilog Code
HDL Coding Techniques
Following is the Verilog Code for a 4-to-1 1-bit MUX using tristate
buffers.
module mux (a, b, c, d, s, o);
input a,b,c,d;
input [3:0] s;
output o;
assign o = s[3] ? a :1'bz;
assign o = s[2] ? b :1'bz;
assign o = s[1] ? c :1'bz;
assign o = s[0] ? d :1'bz;
endmodule
No 4-to-1 MUX
The following example does not generate a 4-to-1 1-bit MUX, but 3to-1
MUX with 1-bit latch. The reason is that not all selector values
were described in the If statement. It is supposed that for the s=11
case, "O" keeps its old value, and therefore a memory element is
needed.
The following table shows pin definitions for a 3-to-1 1-bit MUX with
a 1-bit latch.
IO Pins Description
a, b, c, d Data Inputs
s[1:0] Selector
o Data Output
XST User Guide 2-81