Technical Product Specification for Canoe Pass - Preminary - Intel

Intel ® Server Board S2600CP and Intel ® Server System P4000CP Platform Management
Intel ® Server Board S2600CP and Server System P4000CP TPS
5.5.3 ME System Management Bus (SMBus) Interface
The ME uses the SMLink0 on the SSB in multi-master mode as a dedicated bus for
communication with the BMC using the IPMB protocol. The BMC FW considers this a
secondary IPMB bus and runs at 400 kHz.
The ME uses the SMLink1 on the SSB in multi-master mode bus for communication with
PMBus devices in the power supplies for support of various NM-related features. This bus is
shared with the BMC, which polls these PMBus power supplies for sensor monitoring purposes
(e.g. power supply status, input power, etc.). This bus runs at 100 KHz.
The Management Engine has access to the Host SMBusǁ.
5.5.4 BMC - Management Engine Interaction
Management Engine-Integrated BMC interactions include the following:
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Integrated BMC stores sensor data records for ME-owned sensors.
Integrated BMC participates in ME firmware update.
Integrated BMC initializes ME-owned sensors based on SDRs.
Integrated BMC receives platform event messages sent by the ME.
Integrated BMC notifies ME of POST completion.
BMC may be queried by the ME for inlet temperature readings.
5.5.5 ME Power and Firmware Startup
On Intel ® Server Board S2600CP, the ME is on standby power. The ME FW will begin its startup
sequence at the same time that the BMC FW is booting. As the BMC FW is booting to a Linux
kernel and the ME FW uses an RTOS, the ME FW should always complete its basic
initialization before the BMC. The ME FW can be configured to send a notification message to
the BMC. After this point, the ME FW is ready to process any command requests from the BMC.
In S0/S1 power states, all ME FW functionality is supported. Some features, such as power
limiting, are not supported in S3/S4/S5 power states. Refer to ME FW documentation for details
on what is not supported while in the S3/S4/S5 states.
The ME FW uses a single operational image with a limited-functionality recovery image. In order
to upgrade an operational image, a boot to recovery image must be performed. The ME FW
does not support an IPMI update mechanism except for the case that the system is configured
with a dual-ME (redundant) image. In order to conserve flash space, which the ME FW shares
with BIOS, EPSD systems only support a single ME image. For this case, ME update is only
supported by means of BIOS performing a direct update of the flash component. The recovery
image only provides the basic functionality that is required to perform the update; therefore
other ME FW features are not functional therefore when the update is in progress.
5.5.6 SmaRT/CLST
The power supply optimization provided by SmaRT/CLST relies on a platform HW capability as
well as ME FW support. When a PMBus-compliant power supply detects insufficient input
voltage, an over current condition, or an over-temperature condition, it will assert the SMBAlert#
signal on the power supply SMBus (that is, the PMBus). Through the use of external gates, this
results in a momentary assertion of the PROCHOT# and MEMHOT# signals to the processors,
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