Technical Product Specification for Canoe Pass - Preminary - Intel

Intel ® Server Board S2600CP and Intel ® Server System P4000CP Platform Management
Intel ® Server Board S2600CP and Server System P4000CP TPS
Some of the new features added for NM 2.0 that were not supported in EPSD platforms with NM
1.5 include the following:
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Memory subsystem power monitoring and power limiting
The ability to turn off a core at boot time and run-time (DCA -- Dynamic Core Allocation)
in order to reduce power consumption.
Power supply optimizations
o Smart Ride-Through (SmaRT) – Power consumption is reduced by throttling
techniques and fan gating in order to ride out a momentary AC loss.
o Closed Loop System Throttling (CLST) – Power consumption is reduced by
throttling techniques and fan gating in order to compensate for short-term
problems with the delivery of power by the power supplies due to thermal or
over-current conditions.
Power-limiting at boot time
Optimized power limiting based on multiple controls – NM 2.0 algorithms use a
combination of knobs to optimize power limiting such that performance degradation is
minimized.
5.5 Manageability Engine (ME)
5.5.1 Overview
The Intel ® Server Platform Services (SPS) is a set of manageability services provided by the
firmware executing on an embedded ARC controller within the IOH. This management controller
is also commonly referred to as the Management Engine (ME). The functionality provided by the
SPS firmware is different from Intel ® Active Management Technology (Intel ® AMT or AT)
provided by the ME on client platforms.
Server Platform Services (SPS) are value-added platform management options that enhance
the value of Intel platforms and their component ingredients (CPUs, chipsets, and I/O
components). Each service is designed to function independently wherever possible, or grouped
together with one or more features in flexible combinations to allow OEMs to differentiate
platforms.
5.5.2 BMC – Management Engine (ME) Distributed Model
The Intel ® Server Board S2600CP covered in this specification will require Node Manager 2.0
(NM2.0) support. The following management architecture would need to be supported on the
baseboard to meet product and validation requirements. The NM 2.0 functionality is provided by
the Intel ® C600 PCH Management Engine (ME).
The server management architecture is a partitioned model which places the Management
Engine, which is an embedded controller in the Intel ® C600 chipset, in between the BMC and
the processors. In this architecture, the PCH Management Engine is the owner of the PECI 3.0
bus and the ServerEngines* Pilot III BMC communicates with the ME via an SMBus connection
(SMLINK 0.) The ME provides PECI proxy support that allows the ServerEngines* Pilot III BMC
firmware to access processor functions available on the PECI bus.
Intel Confidential Revision 0.8
Intel order number G26942-003