Technical Product Specification for Canoe Pass - Preminary - Intel
Technical Product Specification for Canoe Pass - Preminary - Intel
Technical Product Specification for Canoe Pass - Preminary - Intel
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<strong>Intel</strong>® Server Board S2600CP Functional Architecture <strong>Intel</strong> ® Server Board S2600CP and Server System P4000CP TPS<br />
44<br />
Table 12. <strong>Intel</strong> ® Server Board S2600CP PCI Bus Segment Characteristics<br />
Voltage Width Speed Type PCI I/O Card Slots<br />
3.3 V X4 or x8<br />
(with mux)<br />
8 GB/S or<br />
16 GB/S<br />
PCI Express*<br />
Gen3<br />
3.3 V x8 16 GB/S PCI Express*<br />
Gen3<br />
3.3 V x8 16 GB/S PCI Express*<br />
Gen3<br />
3.3 V x8 16 GB/S PCI Express*<br />
Gen3<br />
3.3 V x8 16 GB/S PCI Express*<br />
Gen3<br />
3.3 V x8 16 GB/S PCI Express*<br />
Gen3<br />
4.5 Integrated Baseboard Management Controller<br />
X4 or x8 (with mux) PCI Express*<br />
Gen3 throughput to Slot1 (x8<br />
mechanically)<br />
x8 PCI Express* Gen3 throughput<br />
to Slot 2 (x8 mechanically)<br />
x8 PCI Express* Gen3 throughput<br />
to Slot 3 (x8 mechanically, open end<br />
connector)<br />
x8 PCI Express* Gen3 throughput<br />
to Slot 4 (x8 mechanically)<br />
x8 PCI Express* Gen3 throughput<br />
to Slot 5 (x8 mechanically, open end<br />
connector), from CPU2<br />
x8 PCI Express* Gen3 throughput<br />
to Slot 6 (x16 mechanically)<br />
The <strong>Intel</strong> ® Server Boards S2600CP has an Integrated BMC controller based on ServerEngines*<br />
Pilot III. The BMC is provided by an embedded ARM9 controller and associated peripheral<br />
functionality that is required <strong>for</strong> IPMI-based server management. The following is a summary of<br />
the BMC management hardware features used by the BMC:<br />
400MHz 32-bit ARM9 processor with memory management unit (MMU)<br />
Two independent10/100/1000 Ethernet Controllers with RMII/RGMII support<br />
DDR2/3 16-bit interface with up to 800 MHz operation<br />
12 10-bit ADCs<br />
Sixteen fan tachometers<br />
Eight Pulse Width Modulators (PWM)<br />
Chassis intrusion logic<br />
JTAG Master<br />
Eight I2C interfaces with master-slave and SMBus timeout support. All interfaces are<br />
SMBus 2.0 compliant.<br />
Parallel general-purpose I/O Ports (16 direct, 32 shared)<br />
Serial general-purpose I/O Ports (80 in and 80 out)<br />
Three UARTs<br />
Plat<strong>for</strong>m Environmental Control Interface (PECI)<br />
Six general-purpose timers<br />
Interrupt controller<br />
Multiple SPI flash interfaces<br />
NAND/Memory interface<br />
Sixteen mailbox registers <strong>for</strong> communication between the Integrated BMC and host<br />
LPC ROM interface<br />
<strong>Intel</strong> Confidential Revision 0.8<br />
<strong>Intel</strong> order number G26942-003
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