Technical Product Specification for Canoe Pass - Preminary - Intel

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Intel® Server Board S2600CP Functional Architecture Intel ® Server Board S2600CP and Server System P4000CP TPS Table 9. DDR3L Low Voltage RDIMM Population within a Channel (Preliminary. Subject to Change) 36 Configuration Number Speed 1N or 2N DIMM 2 DIMM 1 (Blue Slot) 1 DDR3L-1333, 1066 1N Empty Single-rank 2 DDR3L-1333, 1066 1N Empty Dual-rank 3 DDR3L-800 1N Empty Quad-rank 4 DDR3L-1066 1N Single-rank Single-rank 5 DDR3L-1066 1N Single-rank Dual-rank 6 DDR3L-1066 1N Dual-rank Dual-rank 7 DDR3L- 800 1N Single-rank Quad-rank Table 10. DDR3 UDIMM Population within a Channel (Preliminary. Subject to Change) Configuration Number Speed 1N or 2N DIMM 2 DIMM 1 (Blue Slot) 1 DDR3-1333, & 1066 1N Empty Single-rank 2 DDR3-1333, & 1066 1N Empty Dual-rank 3 DDR3-1333, & 1066 2N Single-rank Single-rank 4 DDR3-1333, & 1066 2N Single-rank Dual-rank 5 DDR3-1333, & 1066 2N Dual-rank Dual-rank Table 11. DDR3L Low Voltage UDIMM Poplulation within a Channel (Preliminary. Subject to Change) Configuration Number Speed 1N or 2N DIMM 2 DIMM 1 (Blue Slot) 1 DDR3-1333,1066 1N Empty Single-rank 2 DDR3-1333, 1066 1N Empty Dual-rank 3 DDR3-1066 2N Single-rank Single-rank 4 DDR3-1066 2N Single-rank Dual-rank 5 DDR3-1066 2N Dual-rank Dual-rank 4.2.2.3 Publishing System Memory The BIOS displays the “Total Memory” of the system during POST if Quite Boot is disabled in the BIOS setup. This is the total size of memory discovered by the BIOS during POST, and is the sum of the individual sizes of installed DDR3 DIMMs in the system. The BIOS displays the “Effective Memory” of the system in the BIOS setup. The term Effective Memory refers to the total size of all DDR3 DIMMs that are active (not disabled) and not used as redundant units. The BIOS provides the total memory of the system in the main page of the BIOS setup. This total is the same as the amount described by the first bullet above. If Quite Boot is disabled, the BIOS displays the total system memory on the diagnostic screen at the end of POST. This total is the same as the amount described by the first bullet above. Intel Confidential Revision 0.8 Intel order number G26942-003
Intel ® Server Board S2600CP and Server System P4000CP TPS Intel® Server Board S2600CP Functional Architecture 4.2.2.4 RAS Features The server board supports the following memory RAS modes: Independent Channel Mode Rank Sparing Mode Mirrored Channel Mode Lockstep Channel Mode Regardless of RAS mode, the requirements for populating within a channel given in the section 4.2.2.2 must be met at all times. Note that support of RAS modes that require matching DIMM population between channels (Mirrored and Lockstep) require that ECC DIMMs be populated. Independent Channel Mode is the only mode that supports non-ECC DIMMs in addition to ECC DIMMs. For RAS modes that require matching populations, the same slot positions across channels must hold the same DIMM type with regards to size and organization. DIMM timings do not have to match but timings will be set to support all DIMMs populated (i.e, DIMMs with slower timings will force faster DIMMs to the slower common timing modes). 4.2.2.4.1 Independent Channel Mode Channels can be populated in any order in Independent Channel Mode. All four channels may be populated in any order and have no matching requirements. All channels must run at the same interface frequency but individual channels may run at different DIMM timings (RAS latency, CAS Latency, and so forth). 4.2.2.4.2 Rank Sparing Mode In Rank Sparing Mode, one rank is a spare of the other ranks on the same channel. The spare rank is held in reserve and is not available as system memory. The spare rank must have identical or larger memory capacity than all the other ranks (sparing source ranks) on the same channel. After sparing, the sparing source rank will be lost. 4.2.2.4.3 Mirrored Channel Mode In Mirrored Channel Mode, the memory contents are mirrored between Channel 0 and Channel 2 and also between Channel 1 and Channel 3. As a result of the mirroring, the total physical memory available to the system is half of what is populated. Mirrored Channel Mode requires that Channel 0 and Channel 2, and Channel 1 and Channel 3 must be populated identically with regards to size and organization. DIMM slot populations within a channel do not have to be identical but the same DIMM slot location across Channel 0 and Channel 2 and across Channel 1 and Channel 3 must be populated the same. 4.2.2.4.4 Lockstep Channel Mode In Lockstep Channel Mode, each memory access is a 128-bit data access that spans Channel 0 and Channel 1, and Channel 2 and Channel 3. Lockstep Channel mode is the only RAS mode that allows SDDC for x8 devices. Lockstep Channel Mode requires that Channel 0 and Channel 1, and Channel 2 and Channel 3 must be populated identically with regards to size and organization. DIMM slot populations within a channel do not have to be identical but the same DIMM slot location across Channel 0 and Channel 1 and across Channel 2 and Channel 3 must be populated the same. Revision 0.8 Intel Confidential Intel order number G26942-003 37
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Technical Product Specification for Canoe Pass - Preminary - Intel

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