Technical Product Specification for Canoe Pass - Preminary - Intel

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Intel® Server Board S2600CP Functional Architecture Intel ® Server Board S2600CP and Server System P4000CP TPS interconnect performance to be achieved in real systems. It has a snoop protocol optimized for low latency and high scalability, as well as packet and lane structures enabling quick completions of transactions. Reliability, availability, and serviceability features (RAS) are built into the architecture. The physical connectivity of each interconnect link is made up of twenty differential signal pairs plus a differential forwarded clock. Each port supports a link pair consisting of two uni-directional links to complete the connection between two components. This supports traffic in both directions simultaneously. To facilitate flexibility and longevity, the interconnect is defined as having five layers: Physical, Link, Routing, Transport, and Protocol. The Intel ® QuickPath Interconnect includes a cache coherency protocol to keep the distributed memory and caching structures coherent during system operation. It supports both low-latency source snooping and a scalable home snoop behavior. The coherency protocol provides for direct cache-to-cache transfers for optimal latency. 4.2.2 Integrated Memory Controller (IMC) and Memory Subsystem 30 2 DIMMs/Ch CPU 1 Figure 16. Integrated Memory Controller (IMC) and Memory Subsystem Integrated into the processor is a memory controller. Each processor provides four DDR3 channels that support the following: Unbuffered DDR3 and registered DDR3 DIMMs CPU 2 LR DIMM (Load Reduced DIMM) for buffered memory solutions demanding higher capacity memory subsystems Independent channel mode or lockstep mode Data burst length of eight cycles for all memory organization modes Memory DDR3 data transfer rates of 800, 1066, 1333, and 1600 MT/s 64-bit wide channels plus 8-bits of ECC support for each channel DDR3 standard I/O Voltage of 1.5 V and DDR3 Low Voltage of 1.35 V 1-Gb, 2-Gb, and 4-Gb DDR3 DRAM technologies supported for these devices: o UDIMM DDR3 – SR x8 and x16 data widths, DR – x8 data width o RDIMM DDR3 – SR,DR, and QR – x4 and x8 data widths o LRDIMM DDR3 – QR – x4 and x8 data widths with direct map or with rank multiplication Up to 8 ranks supported per memory channel, 1, 2 or 4 ranks per DIMM Open with adaptive idle page close timer or closed page policy Intel Confidential Revision 0.8 Intel order number G26942-003 2 DIMMs/Ch
Intel ® Server Board S2600CP and Server System P4000CP TPS Intel® Server Board S2600CP Functional Architecture Per channel memory test and initialization engine can initialize DRAM to all logical zeros with valid ECC (with or without data scrambler) or a predefined test pattern Isochronous access support for Quality of Service (QoS) Minimum memory configuration: independent channel support with 1 DIMM populated Integrated dual SMBus master controllers Command launch modes of 1n/2n RAS Support: o Rank Level Sparing and Device Tagging o Demand and Patrol Scrubbing o DRAM Single Device Data Correction (SDDC) for any single x4 or x8 DRAM device. Independent channel mode supports x4 SDDC. x8 SDDC requires lockstep mode o Lockstep mode where channels 0 & 1 and channels 2 & 3 are operated in lockstep mode o Data scrambling with address to ease detection of write errors to an incorrect address. o Error reporting via Machine Check Architecture o Read Retry during CRC error handling checks by iMC o Channel mirroring within a socket CPU1 Channel Mirror Pairs (A,B) and (C,D) CPU2 Channel Mirror Pairs (E,F) and (G,H) o Error Containment Recovery Improved Thermal Throttling with dynamic Closed Loop Thermal Throttling (CLTT) Memory thermal monitoring support for DIMM temperature 4.2.2.1 Supported Memory Ranks Per DIMM & Data Width SRx8 Non- ECC DRx8 Non- ECC SRx16 Non- ECC SRx8 ECC DRx8 Table 4. UDIMM Support Guidelines (Preliminary. Subject to Change) Memory Capacity Per DIMM1 1GB 2GB 4GB n/a 2GB 4GB 8GB n/a 512MB 1GB 2GB n/a Speed (MT/s) and Voltage Validated by Slot per Channel (SPC) and DIMM Per Channel (DPC)2,3 1 Slot per Channel 2 Slots per Channel 1DPC 1DPC 2DPC 1.35V 1.5V 1.35V 1.5V 1.35V 1.5V 1066, 1333, 1600 1066, 1333, 1600 1066, 1333, 1600 Revision 0.8 Intel Confidential Intel order number G26942-003 n/a 1066, 1333 n/a 1066, 1333 n/a 1066, 1333 n/a 1066, 1333 n/a 1066, 1333 n/a 1066, 1333 1GB 2GB 4GB 1066, 1333 1066, 1333, 1600 ECC Notes: 2GB 4GB 8GB 1066, 1333 1066, 1333, 1600 1. Supported DRAM Densities are 1Gb, 2Gb, and 4Gb. Only 2Gb and 4Gb are validated by Intel 2. Command Address Timing is 1N for 1DPC and 2N for 2DPC 3. No Support for 3DPC when using UDIMMs 1066 1066, 1333 1066 1066, 1333 1066 1066, 1333 1066 1066, 1333 31
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Technical Product Specification for Canoe Pass - Preminary - Intel

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