Technical Product Specification for Canoe Pass - Preminary - Intel
Technical Product Specification for Canoe Pass - Preminary - Intel
Technical Product Specification for Canoe Pass - Preminary - Intel
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<strong>Intel</strong>® Server System P4000CP TPS Appendix E: POST Code Diagnostic LED Decoder<br />
Diagnostic LED Decoder<br />
1 = LED On, 0 = LED Off<br />
Checkpoint Upper Nibble Lower Nibble<br />
MSB LSB<br />
8h 4h 2h 1h 8h 4h 2h 1h<br />
LED # #7 #6 #5 #4 #3 #2 #1 #0 Description<br />
POST Memory Initialization MRC Diagnostic Codes<br />
There are two types of POST Diagnostic Codes displayed by the MRC during memory<br />
initialization; Progress Codes and Fatal Error Codes.<br />
The MRC Progress Codes are displays to the Diagnostic LEDs that show the execution point in<br />
the MRC operational path at each step.<br />
Diagnostic LED Decoder<br />
1 = LED On, 0 = LED Off<br />
Checkpoint Upper Nibble Lower Nibble<br />
MSB LSB<br />
8h 4h 2h 1h 8h 4h 2h 1h<br />
LED #7 #6 #5 #4 #3 #2 #1 #0<br />
MRC Progress Codes<br />
MRC Progress Codes<br />
Revision 0.8 <strong>Intel</strong> Confidential<br />
<strong>Intel</strong> order number G26942-003<br />
Description<br />
B0h 1 0 1 1 0 0 0 0 Detect DIMM population<br />
B1h 1 0 1 1 0 0 0 1 Set DDR3 frequency<br />
B2h 1 0 1 1 0 0 1 0 Gather remaining SPD data<br />
B3h 1 0 1 1 0 0 1 1 Program registers on the memory controller level<br />
B4h 1 0 1 1 0 1 0 0 Evaluate RAS modes and save rank in<strong>for</strong>mation<br />
B5h 1 0 1 1 0 1 0 1 Program registers on the channel level<br />
B6h 1 0 1 1 0 1 1 0 Per<strong>for</strong>m the JEDEC defined initialization sequence<br />
B7h 1 0 1 1 0 1 1 1 Train DDR3 ranks<br />
B8h 1 0 1 1 1 0 0 0 Initialize CLTT/OLTT<br />
B9h 1 0 1 1 1 0 0 1 Hardware memory test and init<br />
BAh 1 0 1 1 1 0 1 0 Execute software memory init<br />
BBh 1 0 1 1 1 0 1 1 Program memory map and interleaving<br />
BCh 1 0 1 1 1 1 0 0 Program RAS configuration<br />
BFh 1 0 1 1 1 1 1 1 MRC is done<br />
Memory Initialization at the beginning of POST includes multiple functions, including: discovery,<br />
channel training, validation that the DIMM population is acceptable and functional, initialization<br />
of the IMC and other hardware settings, and initialization of applicable RAS configurations.<br />
When a major memory initialization error occurs and prevents the system from booting with data<br />
integrity, a beep code is generated, the MRC will display a fatal error code on the diagnostic<br />
LEDs, and a system halt command is executed. Fatal MRC error halts do NOT change the state<br />
of the System Status LED, and they do NOT get logged as SEL events. The following table lists<br />
all MRC fatal errors that are displayed to the Diagnostic LEDs.<br />
MRC Fatal Error Codes<br />
Checkpoint Diagnostic LED Decoder Description<br />
193
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