Technical Product Specification for Canoe Pass - Preminary - Intel

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Appendix E: POST Code Diagnostic LED Decoder ® Intel ® Server Board S2600CP and Server System P4000CP TPS Intel ® Serv 190 Appendix E: POST Code Diagnostic LED Decoder During the system boot process, the BIOS executes a number of platform configuration processes, each of which is assigned a specific hex POST code number. As each configuration routine is started, the BIOS displays the POST code to the POST Code Diagnostic LEDs on the back edge of the server board. To assist in troubleshooting a system hang during the POST process, the Diagnostic LEDs can be used to identify the last POST process that was executed. Each POST code is represented by a sequence of eight amber diagnostic LEDs. The POST codes are divided into two nibbles, an upper nibble and a lower nibble. The upper nibble bits are represented by diagnostic LEDs #4, #5, #6, and #7. The lower nibble bits are represented by diagnostics LEDs #0, #1, #2, and #3. If the bit is set in the upper and lower nibbles, then the corresponding LED is lit. If the bit is clear, then the corresponding LED is off. The diagnostic LED #7 is labeled as “MSB”, and the diagnostic LED #0 is labeled as “LSB”. In the following example, the BIOS sends a value of ACh to the diagnostic LED decoder. The LEDs are decoded as follows: Intel Confidential Intel order number G26942-003
Intel® Server System P4000CP TPS Appendix E: POST Code Diagnostic LED Decoder Table 164. POST Progress Code LED Example Upper Nibble AMBER LEDs Lower Nibble GREEN LEDs LEDs MSB LED #7 LED #6 LED #5 LED #4 LED #3 LED #2 LED #1 LSB LED #0 8h 4h 2h 1h 8h 4h 2h 1h Status ON OFF ON OFF ON ON OFF OFF Results 1 0 Ah 1 0 1 1 Ch 0 0 Upper nibble bits = 1010b = Ah; Lower nibble bits = 1100b = Ch; the two are concatenated as ACh The following table provides a list of all POST progress codes. POST Progress Codes Diagnostic LED Decoder 1 = LED On, 0 = LED Off Checkpoint Upper Nibble Lower Nibble MSB LSB 8h 4h 2h 1h 8h 4h 2h 1h LED # #7 SEC Phase #6 #5 #4 #3 #2 #1 #0 Description 01h 0 0 0 0 0 0 0 1 First POST code after CPU reset 02h 0 0 0 0 0 0 1 0 Microcode load begin 03h 0 0 0 0 0 0 1 1 CRAM initialization begin 04h 0 0 0 0 0 1 0 0 Pei Cache When Disabled 05h 0 0 0 0 0 1 0 1 SEC Core At Power On Begin. 06h 0 0 0 0 0 1 1 0 Early CPU initialization during Sec Phase. 07h 0 0 0 0 0 1 1 1 Early SB initialization during Sec Phase. 08h 0 0 0 0 1 0 0 0 Early NB initialization during Sec Phase. 09h 0 0 0 0 1 0 0 1 End Of Sec Phase. 0Eh 0 0 0 0 1 1 1 0 Microcode Not Found. 0Fh PEI Phase 0 0 0 0 1 1 1 1 Microcode Not Loaded. 10h 0 0 0 1 0 0 0 0 PEI Core 11h 0 0 0 1 0 0 0 1 CPU PEIM 15h 0 0 0 1 0 1 0 1 NB PEIM 19h 0 0 0 1 1 0 0 1 SB PEIM MRC Process Codes – MRC Progress Code Sequence is executed - See Table 63 PEI Phase continued… 31h 0 0 1 1 0 0 0 1 Memory Installed 32h 0 0 1 1 0 0 1 0 CPU PEIM (Cpu Init) 33h 0 0 1 1 0 0 1 1 CPU PEIM (Cache Init) 34h 0 0 1 1 0 1 0 0 CPU PEIM (BSP Select) 35h 0 0 1 1 0 1 0 1 CPU PEIM (AP Init) 36h 0 0 1 1 0 1 1 0 CPU PEIM (CPU SMM Init) 4Fh DXE Phase 0 1 0 0 1 1 1 1 Dxe IPL started 60h 0 1 1 0 0 0 0 0 DXE Core started 61h 0 1 1 0 0 0 0 1 DXE NVRAM Init 62h 0 1 1 0 0 0 1 0 SB RUN Init 63h 0 1 1 0 0 0 1 1 Dxe CPU Init 68h 0 1 1 0 1 0 0 0 DXE PCI Host Bridge Init 69h 0 1 1 0 1 0 0 1 DXE NB Init 6Ah 0 1 1 0 1 0 1 0 DXE NB SMM Init 70h 0 1 1 1 0 0 0 0 DXE SB Init Revision 0.8 Intel Confidential Intel order number G26942-003 191
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