Technical Product Specification for Canoe Pass - Preminary - Intel
Technical Product Specification for Canoe Pass - Preminary - Intel
Technical Product Specification for Canoe Pass - Preminary - Intel
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Appendix C: BMC Sensor Tables <strong>Intel</strong> ® Server Board S2600CP and Server System P4000CP TPS<br />
Full Sensor Name<br />
(Sensor name in SDR)<br />
Processor 2 Thermal<br />
Control %<br />
(P2 Therm Ctrl %)<br />
Processor 3 Thermal<br />
Control %<br />
(P3 Therm Ctrl %)<br />
Processor 4 Thermal<br />
Control %<br />
(P4 Therm Ctrl %)<br />
Processor 1 ERR2 Timeout<br />
(P1 ERR2)<br />
Processor 2 ERR2 Timeout<br />
(P2 ERR2)<br />
Processor 3 ERR2 Timeout<br />
(P3 ERR2)<br />
Processor 4 ERR2 Timeout<br />
(P4 ERR2)<br />
Catastrophic Error<br />
(CATERR)<br />
Processor1 MSID Mismatch<br />
(P1 MSID Mismatch)<br />
Processor Population Fault<br />
(CPU Missing)<br />
Processor 1 DTS Thermal<br />
Margin<br />
(P1 DTS Therm Mgn)<br />
178<br />
Sensor<br />
#<br />
Plat<strong>for</strong>m<br />
Applicability<br />
79h All<br />
7Ah<br />
7Bh<br />
Plat<strong>for</strong>mspecific <br />
Plat<strong>for</strong>mspecific<br />
7Ch All<br />
7Dh All<br />
7Eh<br />
7Fh<br />
Plat<strong>for</strong>mspecific <br />
Plat<strong>for</strong>mspecific<br />
80h All<br />
81h All<br />
82h All<br />
83h All<br />
Sensor Type Event/Readi<br />
ng Type<br />
Temperature<br />
01h<br />
Temperature<br />
01h<br />
Temperature<br />
01h<br />
Processor<br />
07h<br />
Processor<br />
07h<br />
Processor<br />
07h<br />
Processor<br />
07h<br />
Processor<br />
07h<br />
Processor<br />
07h<br />
Processor<br />
07h<br />
Temperature<br />
01h<br />
Threshold<br />
01h<br />
Threshold<br />
01h<br />
Threshold<br />
01h<br />
Digital<br />
Discrete<br />
03h<br />
Digital<br />
Discrete<br />
03h<br />
Digital<br />
Discrete<br />
03h<br />
Digital<br />
Discrete<br />
03h<br />
Digital<br />
Discrete<br />
03h<br />
Digital<br />
Discrete<br />
03h<br />
Digital<br />
Discrete<br />
03h<br />
Threshold<br />
01h<br />
Event Offset Triggers Contrib. To<br />
System Status<br />
[u] [c,nc]<br />
[u] [c,nc]<br />
[u] [c,nc]<br />
nc =<br />
Degraded<br />
c = Non-fatal<br />
nc =<br />
Degraded<br />
c = Non-fatal<br />
nc =<br />
Degraded<br />
c = Non-fatal<br />
01 – State Asserted fatal<br />
01 – State Asserted fatal<br />
01 – State Asserted fatal<br />
01 – State Asserted fatal<br />
01 – State Asserted fatal<br />
01 – State Asserted fatal<br />
01 – State Asserted Fatal<br />
Assert/<br />
Deassert<br />
Readable<br />
Value /<br />
Offsets<br />
Event<br />
Data<br />
<strong>Intel</strong> Confidential Revision 0.8<br />
<strong>Intel</strong> order number G26942-003<br />
As<br />
and<br />
De<br />
As<br />
and<br />
De<br />
As<br />
and<br />
De<br />
As<br />
and<br />
De<br />
As<br />
and<br />
De<br />
As<br />
and<br />
De<br />
As<br />
and<br />
De<br />
As<br />
and<br />
De<br />
As<br />
and<br />
De<br />
As<br />
and<br />
De<br />
Rearm Standby<br />
Analog Trig Offset A –<br />
Analog Trig Offset A –<br />
Analog Trig Offset A –<br />
– Trig Offset A –<br />
– Trig Offset A –<br />
– Trig Offset A –<br />
– Trig Offset A –<br />
– Trig Offset M –<br />
– Trig Offset M –<br />
– Trig Offset M –<br />
- - - Analog R, T A –