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การประชุมวิชาการดานการวิจัยดําเนินงานแหงชาติ ประจําป 2554
วันที่
8-9 กันยายน 2554 ณ โรงแรม เอส ดี อเวนิว กรุงเทพฯ
Flexible Printed Circuit Process Improvement via
Interchangeable Linear Constrained Response Surface Optimisation Models
Pichpimon Kanchanasuttisang 1 and Pongchanun Luangpaiboon 2
1, 2
Industrial Statistics and Operational Research Unit (ISO-RU),
Department of Industrial Engineering, Faculty of Engineering, Thammasat University, Pathumthani, Thailand
Tel: 025643002-9 Ext 3081 Fax: 025643017 E-mail: 1 pichpimon@hotmail.com, 2 lpongch@engr.tu.ac.th
Abstract
This paper presents a collection of experimental design and
mathematical programming techniques for quality improvement in
automotive electronic parts. The quality performance of interest is
measured via the relationship of the etched rate of acid solution and
circuit width, one of the key failure and break down to LED of lighting
vehicles. With lower levels from monitoring the product quality the
manufacturer has spent a lot of cost and time for product verification
procedures. This brings the production with higher levels of waste and
lead time. To validate on processing and to sustain finished goods with
the permanent prevention, the precisely etched condition should be
optimised. The proper factorial experiments, multiple regression and
mathematical programming approaches are applied to investigate the
preferable levels of significant process variables in order to improve the
quality of etched rate. The interchangeable constrained response surface
optimisation models provide the new operating conditions. The
experimental results in each part with less than twenty five lines showed
that the first model decreases the bottom circuit width deviation from
0.0026 to 0.0024 and the latter model decreases the etching rate from
2.033 to 1.124.
Keywords: Flexible Printed Circuit Process, Circuit Width, Etched
Rate, Response Surface Methodology, Multiple Regression,
Steepest Descent
1. INTRODUCTION
In the field of an electronic circuitry, the flexible printed
circuits (FPC) have been developed for lighting automotive vehicles by
assembling with the LED. The emission light and optical properties are
mainly relied on the width of an FPC circuit line. An existing process to
confirm the correct width of a lead line in an electronic field is a
damaged part investigation. The process obviously causes the high
quality cost in FPC manufacturers.
Currently, the circuit width of the FPC is with lower process
capability (Cpk) at -3.03 on the top circuit width and 0.85 on the bottom
circuit width that comparing to the minimal target at 1.33 as shown in
Fig. 1. In this case, the deep details of an etching process should be
investigated so that the optimal working condition would be determined
as a standard process.
LS L
Process Data
0.09
Target 0.1
USL 0.11
Sample M ean 0.0740333
Sample N 60
StD ev (Within) 0.00175612
StD ev (O v erall) 0.00173661
O bserv ed P erform ance
P P M < LSL 1000000.00
PPM > USL 0.00
P P M Total 1000000.00
LS L
P rocess D ata
0.09
Target 0.1
USL 0.11
Sample M ean 0.09655
Sample N 60
StD ev (Within) 0.00257149
StD ev (O v erall) 0.00256062
O bserv ed P erform ance
PPM < LSL 0.00
PPM > USL 0.00
PPM Total 0.00
Process Capability of Top circuit width
LSL Target USL
0.072 0.078 0.084 0.090 0.096 0.102
Exp. Within Performance
P P M < LSL 1000000.00
PPM > USL 0.00
P P M Total 1000000.00
Exp. O verall Performance
P P M < LSL 1000000.00
PPM > USL 0.00
P P M Total 1000000.00
0.108
Process Capability of Bottom circuit width
LSL Target USL
0.0900 0.0936 0.0972 0.1008 0.1044
Exp. Within Performance
PPM < LSL 5430.21
PPM > USL 0.08
PPM Total 5430.30
E xp. O v erall P erform ance
PPM < LSL 5264.21
PPM > USL 0.07
PPM Total 5264.28
0.1080
Within
Overall
P otential (Within) C apability
C p 1.90
C P L -3.03
CPU 6.83
C pk -3.03
O v erall C apability
P p 1.92
PPL -3.06
P P U 6.90
P pk -3.06
Cpm 0.13
Within
Overall
P otential (Within) C apability
C p 1.30
CPL 0.85
CPU 1.74
Cpk 0.85
O v erall C apability
Pp 1.30
PPL 0.85
PPU 1.75
Ppk 0.85
Cpm 0.77
Fig.1 Current Performance on Top and Bottom Circuit Widths.