8Mx8 DRAM
8Mx8 DRAM 8Mx8 DRAM
KM48C8000B, KM48C8100B CMOS DRAM RAS - ONLY REFRESH CYCLE NOTE : W, OE, DIN = Don′t care DOUT = OPEN RAS CAS VIH - VIL - VIH - VIL - VIH - A VIL - tCRP tASR tRAH ROW ADDR CAS - BEFORE - RAS REFRESH CYCLE NOTE : OE, A = Don′t care RAS CAS VIH - VIL - VIH - VIL - VIH - W VIL - DQ0 ~ DQ3(7) VOH - VOL - tRPC tCP tRP tOFF tCSR tWRP tWRH tRAS tCHR tRC tRAS tRC OPEN tRP tRPC tCRP tRPC tRP Don′t care Undefined
KM48C8000B, KM48C8100B CMOS DRAM HIDDEN REFRESH CYCLE ( READ ) RAS CAS VIH - VIL - VIH - VIL - VIH - A VIL - VIH - W VIL - VIH - OE VIL - DQ0 ~ DQ3(7) VOH - VOL - tCRP ROW ADDRESS tRAD tRCD tASR tRAH tASC OPEN tRCS tRAS tRC tCAH COLUMN ADDRESS tRAC tRAL tRSH tAA tCLZ tOEA tCAC tCHR tWRH tRC tRP tRAS tRP tOEZ DATA-OUT tOFF Don′t care Undefined
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KM48C8000B, KM48C8100B CMOS <strong>DRAM</strong><br />
HIDDEN REFRESH CYCLE ( READ )<br />
RAS<br />
CAS<br />
VIH -<br />
VIL -<br />
VIH -<br />
VIL -<br />
VIH -<br />
A<br />
VIL -<br />
VIH -<br />
W<br />
VIL -<br />
VIH -<br />
OE<br />
VIL -<br />
DQ0 ~ DQ3(7)<br />
VOH -<br />
VOL -<br />
tCRP<br />
ROW<br />
ADDRESS<br />
tRAD<br />
tRCD<br />
tASR tRAH tASC<br />
OPEN<br />
tRCS<br />
tRAS<br />
tRC<br />
tCAH<br />
COLUMN<br />
ADDRESS<br />
tRAC<br />
tRAL<br />
tRSH<br />
tAA<br />
tCLZ<br />
tOEA<br />
tCAC<br />
tCHR<br />
tWRH<br />
tRC<br />
tRP tRAS tRP<br />
tOEZ<br />
DATA-OUT<br />
tOFF<br />
Don′t care<br />
Undefined
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