What is New in the PlanAhead 9.2 Release - Xilinx

PlanAhead Release Notes
Release 9.2

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Table of Contents
PlanAhead Release Notes .................................................................................................. 1
What is New in the PlanAhead 9.2 Release ...................................................................... 5
New Device Support.................................................................................................................. 5
Installation and Licensing ........................................................................................................ 5
PinAhead.................................................................................................................................... 6
HDL Import and Export........................................................................................................................ 6
Automatic Placement Rules.................................................................................................................. 6
I/O Bank Statistics ................................................................................................................................6
Clock Region Statistics ......................................................................................................................... 6
Enhanced Search Capability.................................................................................................... 6
Schematic ................................................................................................................................... 7
Removing Objects from the Schematic................................................................................................. 7
Flattening a Net..................................................................................................................................... 7
Area Select............................................................................................................................................ 7
Resource Statistics Report File Output................................................................................... 7
Workspace View Printing Capability...................................................................................... 7
Memory Improvements ............................................................................................................ 7
Miscellaneous............................................................................................................................. 7
Partial Reconfiguration Environment (available for early access users only) .................... 8

What is New in the PlanAhead 9.2 Release
This document provides an overview of the new features and functionality included in the
PlanAhead 9.2 release.
This document assumes that users will upgrade to ISE 9.2i at some point. However, users
electing to use previous ISE versions will still see significant benefits in migrating to
PlanAhead 9.2, as support is available for versions of ISE 6.1i and later.
For more information, please refer to the PlanAhead 9.2 User Guide or contact the Xilinx
Customer Support Hotline. For contact information, visit www.xilinx.com/support
New Device Support
PlanAhead 9.2 now fully supports the Spartan3A-DSP FPGA Families. As new devices
are introduced, they will be made available in PlanAhead through minor releases. It is
advisable to remain current with the PlanAhead minor releases by downloading the latest
incremental release from www.xilinx.com/planahead. Minor releases are distinguished by
the last digit in the release number (9.2.2, 9.2.3, etc.).
PlanAhead 9.2 offers support for the following device families:
Virtex-5 SXT Virtex-II Pro
Virtex-5 LXT Virtex-II
Virtex-5 LX Spartan 3AN
Virtex-4 SX Spartan-3A
Virtex-4 LX Spartan-3E
Virtex-4 FX Spartan-3
Spartan-3A DSP
Installation and Licensing
PlanAhead 9.2 is now using the Xilinx installer rather than Installshield for Windows
installations only. This was done to standardize on the installation process for all Xilinx
Products to make it easier for our users. The Solaris and Linux installation was not
changed and remains a tarkit style installation.
PlanAhead 9.2 includes a new interface to generate, configure and install the license file.
Users can now use the Help | PlanAhead license feature to assist with license generation
and installation. Previous versions of PlanAhead would not invoke if a license was not
configured properly. PlanAhead 9.2 will always invoke and prompt you to generate a
license interactively. You are directed to the Xilinx registration web site to enter your
user and machine data. Some of the fields are seeded automatically with your machine
specific information. This new interface should make licensing PlanAhead much easier,
especially for new users.

PinAhead
PlanAhead 9.2 includes several enhancements to the PinAhead environment as described
below.
HDL Import and Export
PinAhead now enables importing and exporting I/O Port information via the HDL
header.
To import the I/O Ports from a Verilog or VHDL source, use the File | Import I/O
Ports command. You can specify a single or multiple Verilog or VHDL source
files along with their search paths and associated libraries. PlanAhead will extract
the I/O Port information and populate the I/O Ports view
To export a Verilog or VHDL format header containing the I/O Ports defined in
PinAhead, use the Tools | Export I/O Ports command. You are prompted for the
file types to generate (VHDL, Verilog or CSV).
Automatic Placement Rules
Several new placement rules were added to the Automatic I/O Port Placement
command to help ensure proper assignment.
I/O Bank Statistics
The I/O Bank Properties view has been extended to display more information
about the I/O Ports assigned to the I/O Bank. Selecting an I/O Bank will now
display the VCCO and VREF values as well as I/O STANDARD values that have
been assigned to the I/O Bank.
The I/O Bank Properties view also displays the number of I/O Ports assigned to
the I/O Bank and the number of remaining available pins for assignment.
Clock Region Statistics
The Clock Region Properties view has been extended to display more information
about the I/O Ports and “special” logic objects assigned to the Clock Region.
Selecting a Clock Region will now display information about the various I/O
banks contained in the Clock Region as well as list any special resources defined
for the clock regions such as BUFR, BUFIO, IODELAY and IODELAYCTRL.
A new Clock Region to I/O Bank selection rule was added to automatically select
the I/O Banks when a Clock Region is selected.
Enhanced Search Capability
PlanAhead 9.2 provides a much more powerful searching mechanism. The Edit | Find
command interface has been revamped to allow a more comprehensive set of search
criteria. It also now allows for more than one object type to be searched for in the same

Find session. You can now toggle the Object types to search for and enter several
different types of filters to further control the search.
Schematic
PlanAhead 9.2 has several Schematic improvements as described below:
Removing Objects from the Schematic
Objects can now be removed from the Schematic view by selecting them and
using the Remove selected objects from the schematic toolbar button (scissors
icon). The objects and their associated wires are removed from the current
Schematic view.
Flattening a Net
Double-clicking a net will now entirely expand that net through all levels of
hierarchy.
Area Select
Using the Area Select command in the Schematic will now also select the Ports
and Nets as well as the instances in the Area.
Resource Statistics Report File Output
PlanAhead 9.2 enables the resource Properties view Statistics for an Instance, Pblock or
Clock Region to be exported to a text file. To create the file, select the Save statistics to a
file icon in the Instance, Pblock or Clock Region Properties Statistics view and define a
file location.
Workspace View Printing Capability
PlanAhead 9.2 now enables printing of the Workspace views. By making one of the
Workspace views active and selecting the File | Print command, the entire Workspace
view will be sent to the default printer.
Memory Improvements
PlanAhead 9.2 now uses less system memory. On average, a 10-15% memory
improvement is realized using PlanAhead, with a 40-50% improvement when using
TimeAhead.
Miscellaneous
1. The Highlight command was added back to the popup menu and will highlight
selected objects with the default highlight color rather than having the user select
the desired color. The Highlight with command still exists to allow you to select a
desired highlight color.

2. Added back the Unhighlight command feature, which unhighlights the selected
object(s). This shows up under the “Select” main menu and in all other popup
menus.
3. The Run WASSO Analysis dialog has new buttons to reset the parameters to their
default values.
4. The Layout | Reset Layout command has been removed. The PlanAhead default
layout can now be accessed through the Layout | Load Layout | PlanAhead
Default command.
5. Pblock shading now reflects the logic range types applied to it. If a Pblock
RANGE type is turned off, the associated sites within the Pblock rectangle will
not appear shaded when the Pblock is selected.
6. The Workspace view can now be floated outside of the PlanAhead view. To do
so, select the Workspace view tab and use the Float Window popup menu
command.
Partial Reconfiguration Environment (available for early
access users only)
PlanAhead 9.2 drastically improves the early access Partial Reconfiguration design
environment and the overall ease of use of the flow.
With previous PlanAhead versions, a TCL command was required to enable the Partial
Reconfiguration commands. It was required to be set for each PlanAhead session. With
PlanAhead 9.2, the project is set to be a Partial Reconfiguration Project with a TCL
command. It remains set that way each time the Project is opened.
With previous PlanAhead versions, a separate PlanAhead project and implementation
directory was required for each design configuration. PlanAhead 9.2 enables a single
project supporting all design configurations.
In the Netlist view, a top-level netlist instance can be set to be reconfigurable with the Set
Configurable popup menu command. This will automatically create a Pblock for the
Partial Reconfiguration Region and assign the MODE=RECONFIG property. If the
instance was populated and not a black box, you are prompted to name this version of the
Reconfigurable Module. A Reconfigurable Modules folder is created under the instance
in the Netlist view and the newly named version is shown as the active module.
Additional Reconfigurable Modules can be imported for the instance using the Add
Reconfigurable Module popup menu command. It is then displayed as the active
module in the Reconfigurable Modules folder. Selected Modules can be set to active
using the Load Reconfigurable Module command
With PlanAhead 9.2, the ExploreAhead interface is utilized for Partial Reconfiguration
implementation. As Reconfigurable Modules are added, runs are automatically created
for them in the ExploreAhead Runs view. A static logic run is displayed at the top of the
list. The static region must first be implemented before the Reconfigurable Modules can
be implemented. An error dialog is issued if it is attempted.

The run status is displayed and can be monitored using the ExploreAhead Run Properties
interface.
A single implementation directory structure is created and maintained by ExploreAhead.
Alternately, the “Generate Run scripts only” option could be used to export all files
required to implement the partial reconfigurable design and run scripts without launching
the tools.
The Run Assemble popup menu command will invoke a dialog to control the creation of
the partial bitstream files and an initial configuration merged bitstream file. Partial
bitstream files can be created for all Reconfigurable Modules in the Project all at once.
The dialog also enables easy definition of design configurations to create merged
bitstream files independently.