Xilinx DS291, LogiCORE IP Complex Multiplier v3.1, Data Sheet

Functional Description
LogiCORE IP Complex Multiplier v3.1
There are two basic architectures to implement complex multiplication, given two operands: a = ar+ jai and
b = br+ jbi , yielding an output p = ab = pr+ jpi .
Direct implementation requires four real multiplications:
By exploiting that
a three real multiplier solution can be devised, which trades off one multiplier for three pre-combining adders and
increased multiplier wordlength.
Pinout
X-Ref Target - Figure 1
p r
= a
r
b
r
– a
i
b Equation 1
i
p
i
= a
r
b
i
+ a
i
b Equation 2
r
p
r
= a
r
b
r
– a
i
b
i
= a
r
( b
r
+ b
i
) – ( a
r
+ a
i
)b
i
Equation 3
p
i
= a
r
b
i
+ a
i
b
r
= a
r
( b
r
+ b
i
) + ( a
i
– a
r
)b
r
Equation 4
AR
AI
BR
BI
ROUND_CY
SCLR
CLK
CE
Figure 1: Core Schematic Symbol
This section describes the Complex Multiplier core signals as shown in Figure 1 and described in Table 1. All control
inputs are active high. Should an active low input be required for a specific control pin, an inverter must be placed
in the path to the pin and is absorbed appropriately during synthesis and/or mapping.
DS291 March 1, 2011 www.xilinx.com 2
Product Specification
PR
PI