Microsoft PowerPoint - 3.5presentation.ppt - Cadence Design Systems

INVENTIVE 

Synthesis Strategies for 

better QoR using RC 

Nandini Chintala 

Cadence Design Systems

2 

Outline 

Introduction 

Requirements for Synthesis 

Background on RTL Compiler 

Metrics – Area, Timing, Power 

Flow exploration 

Effective strategies 

Conclusions 

© 2007 Cadence Design Systems, Inc. All rights reserved worldwide.

3 

Introduction 

Modern designs have aggressive requirements 

Need implementation of Smaller, Cooler and Faster chips 

Implementation of RTL into netlist is the first step 

Global focus synthesis results in faster chips, single pass multi Vt 

synthesis, and MSV design results in cooler chips 

Logic Netlist determines the quality of design implementation 

Advanced techniques for low power and timing closure 

Capacity allows for top down synthesis 


4 

Synthesis Using RTL Compiler 

Low V t 

Library 

Med. V t 

Library 

High V t 

Library 

Multidimensional Synthesis - Timing, area and power are 

optimized concurrently 

Identify and map critical logic for timing 

Identify and map off-critical logic for power and area 

RTL 

Timing, 

Power 

Constraints 

Multi-objective 

optimization 

Optimized 

Netlist 

Switching 

Activity 

© 2007 Cadence Design Systems, Inc. All rights reserved worldwide. 

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Typical Flow 

Set target library 

set_attr library name / 

Read HDL files 

read_hdl ${FILE_LIST} 

Elaborate the design 

elaborate 

Set timing and design constraints 

Apply optimization directives 

Synthesize –to_gen 

Synthesize –to_map –no_incr 

Synthesize –to_map -incr 

Reports and Interface to P&R 


Timing constraints, Power constraints 

Generic optimizations such as MUX 

optimizations, datapath selections 

Global Mapping 

Incremental Mapping

6 

Mapping stages 

synthesize –to_generic 

synthesize –to_map 

–no_incr 

synthesize –to_map 

-incr 


Generic structuring 

Target setting 

Global mapping 

Remaps (area_map..) 

Incremental 

Generic optimizations such as 

MUX optimizations, datapath 

selections 

Targets for each cost group 

are derived. Each clock 

definition creates a cost group 

Global optimization for area, 

timing, power driven by target 

Area recovery stage for non 

critical paths 

Path based optimization, 

DRC, critical region 

resynthesis for timing and 

sequential resynthesis

7 

Synthesis Strategies Summary 

Technique 

RTL Coding 

Constraints 

Selective 

ungrouping 

Path groups 

Multi Vt Libraries 

Cell selection 

Target manipulation 

Mux optimizations 

WLM selections 

Clock gate analysis 

Area 

++ 

++ 

++ 

++ 

++ 

++ 


= 

++ 

++ 

= 

= 

++ 

++ 

Time 

++ 

++ 

++ 

++ 

++ 

++ 

++ 

Power 

++ 

++ 

++ 

++ 

++ 

++ 

++ 

= 

++ 

++ 

Methodology 

Impact 

High 

High 

Medium 

Low 

Low 

Medium 

Medium 

Medium 

Medium 

High 

Methodology 

Change 

Clock gating 

FSM encoding 

Clean constraints 

result in better netlist 

Analyze opportunity for 

better optimization 

Synthesis script 

Multi Vt libraries 

loaded in synthesis 

Limit cell selection 

Analyze targets 

Analyze mux choices 

Analyze WLM choices 

Analyze clock gating

8 

Typical Flow 

Set target library 

set_attr library name / 

Read HDL files 

read_hdl ${FILE_LIST} 

Elaborate the design 

elaborate 

Set timing and design constraints 

Apply optimization directives 

Synthesize –to_gen 

Synthesize –to_map –no_incr 

Synthesize –to_map -incr 

Reports and Interface to P&R 


RTL coding – example report power -rtl 

•Path adjust 

•Path groups 

•Mux guidance 

•Override target 

•Cell selection 

•Datapath selection 

•Ungrouping 

•Area constraints 

Effort levels

9 

Creating Cost Groups 

Cost groups – buckets of logic sharing the same target 

Divide the problem and conquer 

Target per cost group 

Mapping is target based 

Highly negative target results in unrealistic goal 

Use to isolate impossible paths from other paths 

Target manipulation 

define_cost_group -name C2C 

path_group -from [all::all_seqs] -to [all::all_seqs] -group C2C -name C2C 

define_cost_group –name I2C 

path_group -from [all::all_inps] -to [all::all_seqs] -group I2C -name I2C 

define_cost_group –name I2O 

path_group -from [all::all_inps] -to [all::all_outs] -group I2O -name I2O 

define_cost_group –name C2O 

path_group -from [all::all_seqs] -to [all::all_outs] -group C2O -name C2O 


10 

Path Adjust Flow – Unique To RC 

Target and Path Adjust 

Timing lint report 

Apply target based PA for effective mapping 

Important for area and power effective design for non 

critical paths 

Affects synthesize –to_map only 

path_adjust -to CPU/EBOX/iu0/idaP0ADW/idaP0PreByp2D_reg* -delay -150 

path_adjust -to CPU/EBOX/iu1/idaP1ADW/idaP0PreByp2D_reg* -delay -150 

path_adjust –from [all_ins] –to [all_outs] –delay 500 –name PA_I2O 


11 

Mux Selection And Mapping 

Mux optimization 

Binary mux selection – pragma driven 

Area and timing driven but not congestion driven 

Attributes available to bias mux mapping 

Important for congestion 

Identify the high-density pin cells 

a 

s 

b 

s 

Complex gate Mux gate 


a 

b

12 

Wire Delays – Physically Aware 

Wire delays are significant as process geometries shrink 

Use Physical Layout Estimator (PLE) method 

Dynamic WLM compared to the static library wireload models 

Gate sizing for real wires 

Physical Layout Estimator (PLE) 

• PLE uses actual design and physical 

library information. 

• Dynamically calculates wire delays for 

different logic structures in the design. 

• Correlates better with place and route. 

set_attr lef_library 

set_attr cap_table_file 

set_attr interconnect_mode ple / 


Wire-load Models 

• Wire load models are statistical. 

• Wire loads are calculated based on the nearest 

calibrated area. 

• Correlation is difficult even with custom wire-load 

models. 

set_attr interconnect_mode wireload / 

set_attr wireload_mode top / 

set_attr force_wireload 

[find /mylib -wireload S160K] /designs/*

13 

Wireload Selection Based On the Design 

Timing critical design 

PLE 

Scale factors help to 

introduce pessimism in the 

ple calculated wirecaps 

Can derive from factors used 

in Encounter 

set_attr lef_library 

set_attr cap_table_file 

set_attr interconnect_mode ple / 

set_attribute scale_of_cap_per_unit_len 1.2 / 

set_attribute scale_of_res_per_unit_len 1.2 / 


Non timing critical design 

Zero wireload model 

synthesis 

Smallest design – great for 

area 

Sized/restructured for 

placement introduced wires 

Slight over constrain using 

path adjust in synthesis 

set_attribute force_wireload none /designs/*

14 

Clock Gating – Is it important? 

Clock gating 

Number of clock gating 

elements versus root level 

clock gating 

RC allows Multi level clock 

gating 

Clone and declone clock 

gates after clock gating 

insertion 

Post map analysis on clock 

gating quality of result 

Area vs dynamic power 

savings 


report clock_gating –detail 

report power –clock_tree -buffers - 

leaf_max_fanout 

set_attr lp_clock_gating_max_flops 

/designs/* 

set_attr lp_clock_gating_min_flops 

/designs/* 

clock_gating declone/share

15 

Optimizing Total Negative Slack and Cell 

Selection 

TNS 

If Worst Negative Slack (WNS) is negative, should I 

care about TNS? 

Total Negative Slack Optimization provides critical 

range 

Effective for path based incremental 

Focus on mapping result first 

Reducing the number of paths violating timing 

Cell Selection 

Review of don’t use lists used during synthesis 

Avoid bad cells 


16 

Optimizing For Leakage Power Using Multi Vt Libraries 

Leakage Power optimization 

Load multi Vt libraries 

RC uses leakage power numbers characterized in the 

library 

Depends on the accuracy of library characterization 

Useful for sprinkling in leaky cells 

Strategies 

Limit global mapping to high Vt cells only 

Incremental synthesis using Standard vt cells 

Effective in optimal leakage optimization and better 

structure for timing 


17 

Selective Ungrouping 

Selective ungrouping 

ChipWare components 

Deeply nested hierarchy 

Threshold based or instance name based 

Module naming controlled during generic mapping 

Ungroup Chipware components and very small instances 

set_attribute gen_module_prefix “CW_” / 

ungroup –threshold 5000 

ungroup [get_attr instance $subdesign] 


18 

Effort Levels – Generic, Mapping, Incremental Mapping 

Effort levels 

Effort high does not necessarily mean a good strategy 

Effort level is determined by targets for cost groups 

Global synthesis 

Bottom up synthesis 

Don’t discount it completely 

It works well for certain designs 


19 

Bottom up Flow Implementation 

Read RTL 

Load constraints 

Synthesis 

Derive environment 

Unit level RTL 

Unit constraints/reset target 

Synthesis 

Read unit netlist 

Stitch top level 

Clock gating analysis 


Bottom up flow implementation 

Unit level constraint generation 

Unit level synthesis 

Top level hookup of unit netlists

20 

Flow Explorations 

A small example design was used to test the RC synthesis strategies 

Inst. 

count 

37312 

39109 

45728 

38611 

37228 

Hvt(%) 

37312(100) 

39109(100) 

30548(66.8) 

30386(78.7) 

29423(79) 

Svt(%) 

0(0) 

0(0) 

15177(33.2) 

8222(21.3) 

7802(21) 


Timing 

WNS ps 

-49 

-5 

-12 

500 

Run 1 

Run 2 Run 3 Run 4 

Load Hvt libs 

Load Hvt libs Load Multi-Vt libs Hvt 

No power const 

Map no timing Optimize constraints Multi-Vt Map high –no_incr 

Override target 

Incr with const 

Load Svt 

Incr 

0 

Power 

mW 

15.99 

14.93 

33.34 

17.7 

14.97 

Leakage 

mW 

9.46 

9.07 

27 

6.02 

12.14 

Run 5 

Hvt 

Map no const 

Svt 

Incr

21 

Conclusions 

Exploration of Synthesis flows and strategies 

Better QoR achieved by exploring different 

synthesis flows 


22 

THANK YOU!

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