Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ...

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4.3 Reliability Test Common board level solder joint reliability tests include temperature cycling, thermal shock, temp-humidity-bias, as well as board drop and board bend. Thermal cycling accelerates fatigue failures in solder joints. It determines the ability of assemblies to withstand cyclical exposures in real applications. Since the bulk of real-life solder joint failures are caused by the mismatch between the coefficients of thermal expansion between the component and the substrate, which results in viscoplastic deformation and low cycle fatigue of solder joints, board level thermal cycling has become an industry standard for assessing solder joint reliability. In this research, the industry standard JEDEC JESD22-A 104 specifications were selected as the thermal cycling condition. The cycle temperature was from -55°C to 125°C, with 15 minutes dwell time at each temperature extreme and a total cycle time of 90 minutes. Figure 4.6 shows the time-temperature profile measured by 4 thermocouples attached onto the board and dies at different locations during cycling. Two test vehicles were subject to the thermal cycling test. One group was assembled with reference WLCSPs (or control WLCSPs) without coating material, while the other group was the SolderBrace coated WLCSPs. Each group contained 34 measurement sites (4 boards). 84
Figure 4.6 Air to air thermal cycling chamber temperature profile In order to monitor the resistance of each daisy chain of the test WLCSP in-situ during the thermal cycling, each board was wired outside of the Blue-M air thermal cycle chamber to a PC based data acquisition system, which incorporated Keithley Instruments 7002 switch boxes, Kethley Instruments 2001 multimeters, GPIB scanning system and Labview software (see Figure 4.7). The initial resistance of each daisy-chained WLCSP assembly was measured at room temperature before the cycling as the starting point, and the change in resistance was measured and monitored real-time during the thermal cycling until the part failed. A failure was defined as a resistance reading of 100 ohms. The computer monitoring system counted the number of thermal cycles and recorded the cycle count with the failure data. Five failures were measured prior to the recording of the failure in the data file to avoid false failures. The tests were terminated at 681 cycles when the last assembled SolderBrace WLCSPs failed. Most of the assembled reference dies failed early, within 50 cycles while the last one 85
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Enhanced Polymer Passivation Layer
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SolderBrace coatings were low tempe
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Table of Contents Abstract ........
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4.4 Failure Analysis ..............
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List of Figures Figure 1.1 Trends i
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Figure 3.17 SAC305 Reflow profile .
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CHAPTER 1 INTRODUCTION In the era o
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This effect changes the package to
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1.4 Solder Joint Fatigue Figure 1.2
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leading to the solder joint failure
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umped wafers. The coating is stenci
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11 Bumped Wafer Print over ball Pre
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2.1 Chip Scale Package Technology C
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Mountable with conventional assembl
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Figure 2.3 Cross section of a typic
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Table 2.1 Comparison between tradit
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In-Situ Bumped Wafers Placed Prefor
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of solder joint failure, and they o
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(a) (b) Figure 2.8(a). Metalized ph
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"underfilled" structure distributes
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have generally been the modificatio
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are “low temperature” wafer lev
Page 45 and 46: 2.3.4 Optimized SolderBrace Materia
Page 47 and 48: CHAPTER 3 WLCSP DIE FABRCIATION In
Page 49 and 50: Table 3.1 Test Die used for Reliabi
Page 51 and 52: Figure 3.4 Fabrication Process Flow
Page 53 and 54: spin coating. A layer of light sens
Page 55 and 56: layer, is investigated as a potenti
Page 57 and 58: 10. Final cleaning: After the passi
Page 59 and 60: Cyclopentanone, a colorless liquid
Page 61 and 62: used to check the basic spin and ph
Page 63 and 64: Figure 3.7 SolderBrace film thickne
Page 65 and 66: 6. Post-UV exposure bake: This step
Page 67 and 68: 8. Pattern characterization: The su
Page 69 and 70: offers the optimum flux release cha
Page 71 and 72: fatigue resistance, lower cost SAC
Page 73 and 74: Figure 3.12 Solder Ball Placement M
Page 75 and 76: of solder balls to the holes on the
Page 77 and 78: of thermal shock. If the temperatur
Page 79 and 80: Figure 3.17 SAC305 Reflow profile -
Page 81 and 82: foaming and high performance cleane
Page 83 and 84: - Polish clean: used the optimized
Page 85 and 86: Figure 3.22 SolderBrace printed waf
Page 87 and 88: Voids Figure 3.25 SolderBrace Mater
Page 89 and 90: cutting speed was set at a low valu
Page 91 and 92: Figure 4.2 Process Flow of Board As
Page 93 and 94: pitch, and bump diameter), and subs
Page 95: 4.2.4 X-Ray Inspection Figure 4.5 R
Page 99 and 100: Figure 4.7 Thermal Cycling Setup 87
Page 101 and 102: 4.4 Failure Analysis The main purpo
Page 103 and 104: Figure 4.10 Pad cratering failure o
Page 105 and 106: CHAPTER 5 FINITE ELEMENT ANALYSIS I
Page 107 and 108: 5.1.1 Modeling Approaches Due to th
Page 109 and 110: are shown in Figure 5.2. However, t
Page 111 and 112: 5.1.2 Material Properties Many pack
Page 113 and 114: strain rate sensitivity. The evolut
Page 115 and 116: Morris et a1 [96] used a double pow
Page 117 and 118: focus on the time-dependent effects
Page 119 and 120: 5.2 Modeling Procedure In this proj
Page 121 and 122: Figure 5.6 The diagonal symmetry mo
Page 123 and 124: 5.2.3 Meshing Table 5.2 Anand const
Page 125 and 126: direction, but that the surface is
Page 127 and 128: PREP7 tref,398 ! set zero strain te
Page 129 and 130: 5.2.7 Thermal Fatigue Life Predicti
Page 131 and 132: CHAPTER 6 CONCLUSIONS Wafer level c
Page 133 and 134: References 1. Future Trends in Elec
Page 135 and 136: 23. Electronic Packaging and Interc
Page 137 and 138: 48. Ultra Low Stress and Low Temper
Page 139 and 140: 70. Factors for Successful Wafer-Le
Page 141 and 142: 92. Microstructural Dependendence o
Page 143: 111. Nonlinear Analysis of Full Mat
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Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ...

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