Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ...

4.2 WLCSP-PCB Assembly
The goal of this research was to evaluate the reliability performance of WLCSPs with
SolderBrace material. The bumped dies (both standard and coated dies) were oriented facedown,
accurately aligned to the PCB, flux dipped, placed, and reflowed sequentially as shown in Figure
4.2.
4.2.1 Test Vehicle
The test vehicle as shown in Figure 4.3 was a four layer test board with ten CSP
attachment sites on one side and four BGA sites on the other. In this application, only the
CSP side of the board was assembled. FR4 laminate was used for board fabrication with no high
density interconnect (HDI) or build-up layers. The board dimensions were 2.95" x 7.24" x
0.040", and the pads were 0.012” in diameter, non-solder mask defined. Immersion Sn and
immersion Ag finishes were used as the board surface finishes. Two types of test dies were used
in the assembly for comparison: standard WLCSP dies passivated with a low temperature
PECVD dielectric layer (B-die); and the SolderBrace coated WLCSP B-dies. The PCB’s were
pre-baked (125 o C for 15 mins) to drive any absorbed moisture out of the PCB to prevent
outgassing, warpage and other defects.
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