Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ...

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List of Tables Table 2.1 Comparison between traditional packaging and wafer level packaging ..................... 19 Table 2.2 Comparison of Wafer Level Chip Scale Packaging Technologies ............................ 20 Table 3.1 Test Die used for Reliability Testing ......................................................................... 37 Table 3.2 Silicon Wafer Cleaning Procedure ............................................................................ 40 Table 3.3 Test samples with various material formulations ...................................................... 46 Table 3.4 Printer Set up and Parameters .................................................................................... 58 Table 3.5 Popular Pb-Free solder Alloys ................................................................................... 59 Table 3.6 Polishing Parameters ................................................................................................... 71 Table 4.1 Specifications for wafer dicing ................................................................................... 77 Table 4.2 Reflow Profile Parameters .......................................................................................... 82 Table 4.3 Summary of Thermal Cycling Test Results ................................................................ 88 Table 5.1 Apparent modulus and yield stress constants for SAC solders ................................ 104 Table 5.2 Anand constants SAC 305 ........................................................................................ 111 Table 5.3 Material Properties of models ................................................................................... 111 Table 5.4 Prediction model and parameters used in this study ................................................. 117 Table 5.5 Summary of the characteristic life ............................................................................ 118 viii
List of Figures Figure 1.1 Trends in the Packaging Technology ......................................................................... 3 Figure 1.2 Cross section view of WLCSP ball formation ............................................................ 5 Figure 1.3 Coffin-Manson low cycle fatigue equation ................................................................. 6 Figure 1.4 Distance from netural point for a BGA type package ................................................ 6 Figure 1.5 Polymer coated ceramic filler particle ......................................................................... 7 Figure 1.6 Application method of SolderBrace material by UV definition ................................ 10 Figure 1.7 Application of SolderBrace Material by printing over balled wafer ......................... 11 Figure 2.1 Main CSP Categories ................................................................................................ 15 Figure 2.2 Example of a flex tape style CSP .............................................................................. 16 Figure 2.3 Cross section of a typical Polyimide-RDL WLCSP.................................................. 17 Figure 2.4 Examples of WLCSP ................................................................................................ 18 Figure 2.5 Bumping Backend Process Flow .............................................................................. 21 Figure 2.6 (a).Thermal fatigue failure of UltraCSP solder ball and (b). Partial thermal Fatigue failure of UltraCSP solder ball from Flip Chip technologies ................. 23 Figure 2.7 Illustration of SUB build-up ...................................................................................... 24 Figure 2.8 (a).Metalized photo-paternable silicone bumps and (b). Stencil printed Silicon bumps............................................................................................................. 25 Figure 2.9 Cross section of package structure of Fujitsu’s Super CSP ..................................... 26 Figure 2.10 Examples of Microspring technology (a). Probe Cards (b). Sockets Interposers (c). Die Size Spring Grid Array (DSSGA) Modules ............................................... 27 ix
Page 1 and 2: Enhanced Polymer Passivation Layer
Page 3 and 4: SolderBrace coatings were low tempe
Page 5 and 6: Table of Contents Abstract ........
Page 7: 4.4 Failure Analysis ..............
Page 11 and 12: Figure 3.17 SAC305 Reflow profile .
Page 13 and 14: CHAPTER 1 INTRODUCTION In the era o
Page 15 and 16: This effect changes the package to
Page 17 and 18: 1.4 Solder Joint Fatigue Figure 1.2
Page 19 and 20: leading to the solder joint failure
Page 21 and 22: umped wafers. The coating is stenci
Page 23 and 24: 11 Bumped Wafer Print over ball Pre
Page 25 and 26: 2.1 Chip Scale Package Technology C
Page 27 and 28: Mountable with conventional assembl
Page 29 and 30: Figure 2.3 Cross section of a typic
Page 31 and 32: Table 2.1 Comparison between tradit
Page 33 and 34: In-Situ Bumped Wafers Placed Prefor
Page 35 and 36: of solder joint failure, and they o
Page 37 and 38: (a) (b) Figure 2.8(a). Metalized ph
Page 39 and 40: "underfilled" structure distributes
Page 41 and 42: have generally been the modificatio
Page 43 and 44: are “low temperature” wafer lev
Page 45 and 46: 2.3.4 Optimized SolderBrace Materia
Page 47 and 48: CHAPTER 3 WLCSP DIE FABRCIATION In
Page 49 and 50: Table 3.1 Test Die used for Reliabi
Page 51 and 52: Figure 3.4 Fabrication Process Flow
Page 53 and 54: spin coating. A layer of light sens
Page 55 and 56: layer, is investigated as a potenti
Page 57 and 58: 10. Final cleaning: After the passi
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Cyclopentanone, a colorless liquid
Page 61 and 62:
used to check the basic spin and ph
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Figure 3.7 SolderBrace film thickne
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6. Post-UV exposure bake: This step
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8. Pattern characterization: The su
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offers the optimum flux release cha
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fatigue resistance, lower cost SAC
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Figure 3.12 Solder Ball Placement M
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of solder balls to the holes on the
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of thermal shock. If the temperatur
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Figure 3.17 SAC305 Reflow profile -
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foaming and high performance cleane
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- Polish clean: used the optimized
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Figure 3.22 SolderBrace printed waf
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Voids Figure 3.25 SolderBrace Mater
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cutting speed was set at a low valu
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Figure 4.2 Process Flow of Board As
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pitch, and bump diameter), and subs
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4.2.4 X-Ray Inspection Figure 4.5 R
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Figure 4.6 Air to air thermal cycli
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Figure 4.7 Thermal Cycling Setup 87
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4.4 Failure Analysis The main purpo
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Figure 4.10 Pad cratering failure o
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CHAPTER 5 FINITE ELEMENT ANALYSIS I
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5.1.1 Modeling Approaches Due to th
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are shown in Figure 5.2. However, t
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5.1.2 Material Properties Many pack
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strain rate sensitivity. The evolut
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Morris et a1 [96] used a double pow
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focus on the time-dependent effects
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5.2 Modeling Procedure In this proj
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Figure 5.6 The diagonal symmetry mo
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5.2.3 Meshing Table 5.2 Anand const
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direction, but that the surface is
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PREP7 tref,398 ! set zero strain te
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5.2.7 Thermal Fatigue Life Predicti
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CHAPTER 6 CONCLUSIONS Wafer level c
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References 1. Future Trends in Elec
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23. Electronic Packaging and Interc
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48. Ultra Low Stress and Low Temper
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70. Factors for Successful Wafer-Le
Page 141 and 142:
92. Microstructural Dependendence o
Page 143:
111. Nonlinear Analysis of Full Mat
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