Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ...
Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ... Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ...
Figure 3.21 SolderBrace Material Cleaning by Polishing Method - UV-Defined cleaning: This method was similar to the one described in Section 3.4.1, but the SolderBrace material was printed on the bumped wafer instead of spin coating the wafer followed by the solder bumping. Figure 3.22 shows the partially printed 8” wafer that was used to test this method as the start point. Due to the large size of the wafer, it was first diced into small pieces or panels. With the pattern mask, UV exposure and development, the material coated on the top of the solder balls could be removed (see Figure 3.23). However, for an array of dies or the whole wafer of dies, the size of the exposed areas was still not consistant which might be caused by the non-uniform printing over the solder spheres. What is more, silica filler residue was sometimes left on the solder ball after development (see Figure 3.24). 72
Figure 3.22 SolderBrace printed wafer for the UV-defined cleanning application Figure 3.23 SolderBrace Material cleaned by UV-Defined Method 73 Printed dies
- Page 33 and 34: In-Situ Bumped Wafers Placed Prefor
- Page 35 and 36: of solder joint failure, and they o
- Page 37 and 38: (a) (b) Figure 2.8(a). Metalized ph
- Page 39 and 40: "underfilled" structure distributes
- Page 41 and 42: have generally been the modificatio
- Page 43 and 44: are “low temperature” wafer lev
- Page 45 and 46: 2.3.4 Optimized SolderBrace Materia
- Page 47 and 48: CHAPTER 3 WLCSP DIE FABRCIATION In
- Page 49 and 50: Table 3.1 Test Die used for Reliabi
- Page 51 and 52: Figure 3.4 Fabrication Process Flow
- Page 53 and 54: spin coating. A layer of light sens
- Page 55 and 56: layer, is investigated as a potenti
- Page 57 and 58: 10. Final cleaning: After the passi
- Page 59 and 60: Cyclopentanone, a colorless liquid
- Page 61 and 62: used to check the basic spin and ph
- Page 63 and 64: Figure 3.7 SolderBrace film thickne
- Page 65 and 66: 6. Post-UV exposure bake: This step
- Page 67 and 68: 8. Pattern characterization: The su
- Page 69 and 70: offers the optimum flux release cha
- Page 71 and 72: fatigue resistance, lower cost SAC
- Page 73 and 74: Figure 3.12 Solder Ball Placement M
- Page 75 and 76: of solder balls to the holes on the
- Page 77 and 78: of thermal shock. If the temperatur
- Page 79 and 80: Figure 3.17 SAC305 Reflow profile -
- Page 81 and 82: foaming and high performance cleane
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- Page 87 and 88: Voids Figure 3.25 SolderBrace Mater
- Page 89 and 90: cutting speed was set at a low valu
- Page 91 and 92: Figure 4.2 Process Flow of Board As
- Page 93 and 94: pitch, and bump diameter), and subs
- Page 95 and 96: 4.2.4 X-Ray Inspection Figure 4.5 R
- Page 97 and 98: Figure 4.6 Air to air thermal cycli
- Page 99 and 100: Figure 4.7 Thermal Cycling Setup 87
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- Page 103 and 104: Figure 4.10 Pad cratering failure o
- Page 105 and 106: CHAPTER 5 FINITE ELEMENT ANALYSIS I
- Page 107 and 108: 5.1.1 Modeling Approaches Due to th
- Page 109 and 110: are shown in Figure 5.2. However, t
- Page 111 and 112: 5.1.2 Material Properties Many pack
- Page 113 and 114: strain rate sensitivity. The evolut
- Page 115 and 116: Morris et a1 [96] used a double pow
- Page 117 and 118: focus on the time-dependent effects
- Page 119 and 120: 5.2 Modeling Procedure In this proj
- Page 121 and 122: Figure 5.6 The diagonal symmetry mo
- Page 123 and 124: 5.2.3 Meshing Table 5.2 Anand const
- Page 125 and 126: direction, but that the surface is
- Page 127 and 128: PREP7 tref,398 ! set zero strain te
- Page 129 and 130: 5.2.7 Thermal Fatigue Life Predicti
- Page 131 and 132: CHAPTER 6 CONCLUSIONS Wafer level c
- Page 133 and 134: References 1. Future Trends in Elec
Figure 3.22 SolderBrace printed wafer <strong>for</strong> the UV-defined cleanning application<br />
Figure 3.23 SolderBrace Material cleaned by UV-Defined Method<br />
73<br />
Printed dies