Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ...

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- Post reflow cleaning Kester TSF-6592 no-clean flux (a) Lord no-flow flux (b) Figure 3.18 Solder wettability with different flux after reflow 68 ‘ The term “no-clean” is really a misnomer because many critical applications do require the flux to be cleaned. Nowadays, one of the most common reasons to remove no-clean fluxes is to increase the adhesion of conformal coatings and underfill materials. Residue of the flux can absorb moisture causing the underfill material to separate from the board by forming a little pocket of stream or gas during the underfill curing. Also, the cleaning is needed to prevent corrosion in PCBs exposed to extreme environments, or simply to improve the cosmetic appearance of the boards [76]. Therefore, a post reflow cleaning process was added to this process by using a 10% concentration of HYDREX DX aqueous cleaner. HYDREX DX is a low-
foaming and high performance cleaner selected to remove a broad range of lead free water soluble and no-clean flux residues from circuit assemblies. Prior to the cleaning process, HYDREX DX solution wash bath was diluted and heated to 60°C~ 74°C on the hotplate. Then the bumped wafer was submerged into the cleanser for 5 minutes and then rinsed with DI wafer. Further inspection with a microscope was required to check the surface cleanness. Figure 3.19 shows the top view of a single SolderBrace coated WLCSP die. 3.4.2 Printing Method Figure 3.19 A single WLCSP die with coated SolderBrace material Optionally there is another way to introduce the SolderBrace type material to the WLCSP wafer, called “printing on bumped wafer” as outlined in Figure 3.20. 69
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Enhanced Polymer Passivation Layer
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SolderBrace coatings were low tempe
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Table of Contents Abstract ........
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4.4 Failure Analysis ..............
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List of Figures Figure 1.1 Trends i
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Figure 3.17 SAC305 Reflow profile .
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CHAPTER 1 INTRODUCTION In the era o
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This effect changes the package to
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1.4 Solder Joint Fatigue Figure 1.2
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leading to the solder joint failure
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umped wafers. The coating is stenci
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11 Bumped Wafer Print over ball Pre
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2.1 Chip Scale Package Technology C
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Mountable with conventional assembl
Page 29 and 30: Figure 2.3 Cross section of a typic
Page 31 and 32: Table 2.1 Comparison between tradit
Page 33 and 34: In-Situ Bumped Wafers Placed Prefor
Page 35 and 36: of solder joint failure, and they o
Page 37 and 38: (a) (b) Figure 2.8(a). Metalized ph
Page 39 and 40: "underfilled" structure distributes
Page 41 and 42: have generally been the modificatio
Page 43 and 44: are “low temperature” wafer lev
Page 45 and 46: 2.3.4 Optimized SolderBrace Materia
Page 47 and 48: CHAPTER 3 WLCSP DIE FABRCIATION In
Page 49 and 50: Table 3.1 Test Die used for Reliabi
Page 51 and 52: Figure 3.4 Fabrication Process Flow
Page 53 and 54: spin coating. A layer of light sens
Page 55 and 56: layer, is investigated as a potenti
Page 57 and 58: 10. Final cleaning: After the passi
Page 59 and 60: Cyclopentanone, a colorless liquid
Page 61 and 62: used to check the basic spin and ph
Page 63 and 64: Figure 3.7 SolderBrace film thickne
Page 65 and 66: 6. Post-UV exposure bake: This step
Page 67 and 68: 8. Pattern characterization: The su
Page 69 and 70: offers the optimum flux release cha
Page 71 and 72: fatigue resistance, lower cost SAC
Page 73 and 74: Figure 3.12 Solder Ball Placement M
Page 75 and 76: of solder balls to the holes on the
Page 77 and 78: of thermal shock. If the temperatur
Page 79: Figure 3.17 SAC305 Reflow profile -
Page 83 and 84: - Polish clean: used the optimized
Page 85 and 86: Figure 3.22 SolderBrace printed waf
Page 87 and 88: Voids Figure 3.25 SolderBrace Mater
Page 89 and 90: cutting speed was set at a low valu
Page 91 and 92: Figure 4.2 Process Flow of Board As
Page 93 and 94: pitch, and bump diameter), and subs
Page 95 and 96: 4.2.4 X-Ray Inspection Figure 4.5 R
Page 97 and 98: Figure 4.6 Air to air thermal cycli
Page 99 and 100: Figure 4.7 Thermal Cycling Setup 87
Page 101 and 102: 4.4 Failure Analysis The main purpo
Page 103 and 104: Figure 4.10 Pad cratering failure o
Page 105 and 106: CHAPTER 5 FINITE ELEMENT ANALYSIS I
Page 107 and 108: 5.1.1 Modeling Approaches Due to th
Page 109 and 110: are shown in Figure 5.2. However, t
Page 111 and 112: 5.1.2 Material Properties Many pack
Page 113 and 114: strain rate sensitivity. The evolut
Page 115 and 116: Morris et a1 [96] used a double pow
Page 117 and 118: focus on the time-dependent effects
Page 119 and 120: 5.2 Modeling Procedure In this proj
Page 121 and 122: Figure 5.6 The diagonal symmetry mo
Page 123 and 124: 5.2.3 Meshing Table 5.2 Anand const
Page 125 and 126: direction, but that the surface is
Page 127 and 128: PREP7 tref,398 ! set zero strain te
Page 129 and 130: 5.2.7 Thermal Fatigue Life Predicti
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CHAPTER 6 CONCLUSIONS Wafer level c
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References 1. Future Trends in Elec
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23. Electronic Packaging and Interc
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48. Ultra Low Stress and Low Temper
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70. Factors for Successful Wafer-Le
Page 141 and 142:
92. Microstructural Dependendence o
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111. Nonlinear Analysis of Full Mat
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