Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ...
Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ... Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ...
List of Tables Table 2.1 Comparison between traditional packaging and wafer level packaging ..................... 19 Table 2.2 Comparison of Wafer Level Chip Scale Packaging Technologies ............................ 20 Table 3.1 Test Die used for Reliability Testing ......................................................................... 37 Table 3.2 Silicon Wafer Cleaning Procedure ............................................................................ 40 Table 3.3 Test samples with various material formulations ...................................................... 46 Table 3.4 Printer Set up and Parameters .................................................................................... 58 Table 3.5 Popular Pb-Free solder Alloys ................................................................................... 59 Table 3.6 Polishing Parameters ................................................................................................... 71 Table 4.1 Specifications for wafer dicing ................................................................................... 77 Table 4.2 Reflow Profile Parameters .......................................................................................... 82 Table 4.3 Summary of Thermal Cycling Test Results ................................................................ 88 Table 5.1 Apparent modulus and yield stress constants for SAC solders ................................ 104 Table 5.2 Anand constants SAC 305 ........................................................................................ 111 Table 5.3 Material Properties of models ................................................................................... 111 Table 5.4 Prediction model and parameters used in this study ................................................. 117 Table 5.5 Summary of the characteristic life ............................................................................ 118 viii
List of Figures Figure 1.1 Trends in the Packaging Technology ......................................................................... 3 Figure 1.2 Cross section view of WLCSP ball formation ............................................................ 5 Figure 1.3 Coffin-Manson low cycle fatigue equation ................................................................. 6 Figure 1.4 Distance from netural point for a BGA type package ................................................ 6 Figure 1.5 Polymer coated ceramic filler particle ......................................................................... 7 Figure 1.6 Application method of SolderBrace material by UV definition ................................ 10 Figure 1.7 Application of SolderBrace Material by printing over balled wafer ......................... 11 Figure 2.1 Main CSP Categories ................................................................................................ 15 Figure 2.2 Example of a flex tape style CSP .............................................................................. 16 Figure 2.3 Cross section of a typical Polyimide-RDL WLCSP.................................................. 17 Figure 2.4 Examples of WLCSP ................................................................................................ 18 Figure 2.5 Bumping Backend Process Flow .............................................................................. 21 Figure 2.6 (a).Thermal fatigue failure of UltraCSP solder ball and (b). Partial thermal Fatigue failure of UltraCSP solder ball from Flip Chip technologies ................. 23 Figure 2.7 Illustration of SUB build-up ...................................................................................... 24 Figure 2.8 (a).Metalized photo-paternable silicone bumps and (b). Stencil printed Silicon bumps............................................................................................................. 25 Figure 2.9 Cross section of package structure of Fujitsu’s Super CSP ..................................... 26 Figure 2.10 Examples of Microspring technology (a). Probe Cards (b). Sockets Interposers (c). Die Size Spring Grid Array (DSSGA) Modules ............................................... 27 ix
- Page 1 and 2: Enhanced Polymer Passivation Layer
- Page 3 and 4: SolderBrace coatings were low tempe
- Page 5 and 6: Table of Contents Abstract ........
- Page 7: 4.4 Failure Analysis ..............
- Page 11 and 12: Figure 3.17 SAC305 Reflow profile .
- Page 13 and 14: CHAPTER 1 INTRODUCTION In the era o
- Page 15 and 16: This effect changes the package to
- Page 17 and 18: 1.4 Solder Joint Fatigue Figure 1.2
- Page 19 and 20: leading to the solder joint failure
- Page 21 and 22: umped wafers. The coating is stenci
- Page 23 and 24: 11 Bumped Wafer Print over ball Pre
- Page 25 and 26: 2.1 Chip Scale Package Technology C
- Page 27 and 28: Mountable with conventional assembl
- Page 29 and 30: Figure 2.3 Cross section of a typic
- Page 31 and 32: Table 2.1 Comparison between tradit
- Page 33 and 34: In-Situ Bumped Wafers Placed Prefor
- Page 35 and 36: of solder joint failure, and they o
- Page 37 and 38: (a) (b) Figure 2.8(a). Metalized ph
- Page 39 and 40: "underfilled" structure distributes
- Page 41 and 42: have generally been the modificatio
- Page 43 and 44: are “low temperature” wafer lev
- Page 45 and 46: 2.3.4 Optimized SolderBrace Materia
- Page 47 and 48: CHAPTER 3 WLCSP DIE FABRCIATION In
- Page 49 and 50: Table 3.1 Test Die used for Reliabi
- Page 51 and 52: Figure 3.4 Fabrication Process Flow
- Page 53 and 54: spin coating. A layer of light sens
- Page 55 and 56: layer, is investigated as a potenti
- Page 57 and 58: 10. Final cleaning: After the passi
List of Tables<br />
Table 2.1 Comparison between traditional packaging and wafer level packaging ..................... 19<br />
Table 2.2 Comparison of <strong>Wafer</strong> <strong>Level</strong> <strong>Chip</strong> <strong>Scale</strong> Packaging Technologies ............................ 20<br />
Table 3.1 Test Die used <strong>for</strong> Reliability Testing ......................................................................... 37<br />
Table 3.2 Silicon <strong>Wafer</strong> Cleaning Procedure ............................................................................ 40<br />
Table 3.3 Test samples with various material <strong>for</strong>mulations ...................................................... 46<br />
Table 3.4 Printer Set up and Parameters .................................................................................... 58<br />
Table 3.5 Popular Pb-Free solder Alloys ................................................................................... 59<br />
Table 3.6 Polishing Parameters ................................................................................................... 71<br />
Table 4.1 Specifications <strong>for</strong> wafer dicing ................................................................................... 77<br />
Table 4.2 Reflow Profile Parameters .......................................................................................... 82<br />
Table 4.3 Summary of Thermal Cycling Test Results ................................................................ 88<br />
Table 5.1 Apparent modulus and yield stress constants <strong>for</strong> SAC solders ................................ 104<br />
Table 5.2 Anand constants SAC 305 ........................................................................................ 111<br />
Table 5.3 Material Properties of models ................................................................................... 111<br />
Table 5.4 Prediction model and parameters used in this study ................................................. 117<br />
Table 5.5 Summary of the characteristic life ............................................................................ 118<br />
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