Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ...

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(a) (b) Figure 3.5 Delaminated surface coatings (a) and good surface coatings (b) 3.4 SolderBracing Die Fabrication Process Two wafer level processing methods were introduced and developed to form SolderBrace in this research: Coating-type solder bracing and Maskless printing over solder balled wafer. 3.4.1 Coating Method The coating method included the process steps of spin coating, pre-bake, UV exposure, and development followed by solder ball placement and reflow as outlined in Figure 3.6. With the exception of solder reflow, all of the steps are “low temperature” wafer level steps, where the maximum processing temperature is 100 o C. According to the various SolderBrace material developed at Lord Corporation, a large number of photolithography experiments were investigated and optimized to identify the most stable fabrication parameters. Detail steps to build SolderBrace dies (based on Die A or Die B) are described below. Si and Si dioxide wafers were 48
used to check the basic spin and photo performance prior to the application on the real metalized wafers. 1. Cleaning and dehydration bake: Acetone, methanol, and DI water were in turn used to clean the wafer surface making sure no dust, dirt, or residual photoresist remained. A 20 minutes dehydration baking at 120 o C ensured that any H2O on the surface evaporated. 2. SolderBrace material application: A layer of Lord 9809-19 was spun coated onto the wafer with a 1000 rpm/s acceleration rate to a final spin speed of 2000 rpms, held for 30 seconds. The film thickness vs. spin-speed curves plotted in Figure 3.7 provide the information required to select the appropriate spin speed needed to achieve the desired coating thickness (45-50μm ). 49
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Enhanced Polymer Passivation Layer
Page 3 and 4:
SolderBrace coatings were low tempe
Page 5 and 6:
Table of Contents Abstract ........
Page 7 and 8:
4.4 Failure Analysis ..............
Page 9 and 10: List of Figures Figure 1.1 Trends i
Page 11 and 12: Figure 3.17 SAC305 Reflow profile .
Page 13 and 14: CHAPTER 1 INTRODUCTION In the era o
Page 15 and 16: This effect changes the package to
Page 17 and 18: 1.4 Solder Joint Fatigue Figure 1.2
Page 19 and 20: leading to the solder joint failure
Page 21 and 22: umped wafers. The coating is stenci
Page 23 and 24: 11 Bumped Wafer Print over ball Pre
Page 25 and 26: 2.1 Chip Scale Package Technology C
Page 27 and 28: Mountable with conventional assembl
Page 29 and 30: Figure 2.3 Cross section of a typic
Page 31 and 32: Table 2.1 Comparison between tradit
Page 33 and 34: In-Situ Bumped Wafers Placed Prefor
Page 35 and 36: of solder joint failure, and they o
Page 37 and 38: (a) (b) Figure 2.8(a). Metalized ph
Page 39 and 40: "underfilled" structure distributes
Page 41 and 42: have generally been the modificatio
Page 43 and 44: are “low temperature” wafer lev
Page 45 and 46: 2.3.4 Optimized SolderBrace Materia
Page 47 and 48: CHAPTER 3 WLCSP DIE FABRCIATION In
Page 49 and 50: Table 3.1 Test Die used for Reliabi
Page 51 and 52: Figure 3.4 Fabrication Process Flow
Page 53 and 54: spin coating. A layer of light sens
Page 55 and 56: layer, is investigated as a potenti
Page 57 and 58: 10. Final cleaning: After the passi
Page 59: Cyclopentanone, a colorless liquid
Page 63 and 64: Figure 3.7 SolderBrace film thickne
Page 65 and 66: 6. Post-UV exposure bake: This step
Page 67 and 68: 8. Pattern characterization: The su
Page 69 and 70: offers the optimum flux release cha
Page 71 and 72: fatigue resistance, lower cost SAC
Page 73 and 74: Figure 3.12 Solder Ball Placement M
Page 75 and 76: of solder balls to the holes on the
Page 77 and 78: of thermal shock. If the temperatur
Page 79 and 80: Figure 3.17 SAC305 Reflow profile -
Page 81 and 82: foaming and high performance cleane
Page 83 and 84: - Polish clean: used the optimized
Page 85 and 86: Figure 3.22 SolderBrace printed waf
Page 87 and 88: Voids Figure 3.25 SolderBrace Mater
Page 89 and 90: cutting speed was set at a low valu
Page 91 and 92: Figure 4.2 Process Flow of Board As
Page 93 and 94: pitch, and bump diameter), and subs
Page 95 and 96: 4.2.4 X-Ray Inspection Figure 4.5 R
Page 97 and 98: Figure 4.6 Air to air thermal cycli
Page 99 and 100: Figure 4.7 Thermal Cycling Setup 87
Page 101 and 102: 4.4 Failure Analysis The main purpo
Page 103 and 104: Figure 4.10 Pad cratering failure o
Page 105 and 106: CHAPTER 5 FINITE ELEMENT ANALYSIS I
Page 107 and 108: 5.1.1 Modeling Approaches Due to th
Page 109 and 110: are shown in Figure 5.2. However, t
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5.1.2 Material Properties Many pack
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strain rate sensitivity. The evolut
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Morris et a1 [96] used a double pow
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focus on the time-dependent effects
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5.2 Modeling Procedure In this proj
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Figure 5.6 The diagonal symmetry mo
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5.2.3 Meshing Table 5.2 Anand const
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direction, but that the surface is
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PREP7 tref,398 ! set zero strain te
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5.2.7 Thermal Fatigue Life Predicti
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CHAPTER 6 CONCLUSIONS Wafer level c
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References 1. Future Trends in Elec
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23. Electronic Packaging and Interc
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48. Ultra Low Stress and Low Temper
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70. Factors for Successful Wafer-Le
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92. Microstructural Dependendence o
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111. Nonlinear Analysis of Full Mat
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