Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ...

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Heating from 200 o C to 300 o C, ramp rate 2.5 o C /minute in Nitrogen Hold time at 300 o C for 60 minutes in Nitrogen Gradual cooling to room temperature For die B, about 1μm low temperature PECVD SiO2 was deposited to form the passivation layer. This layer is much more stable with better adhesion to the wafer surface than polyimide. Due to the facility limitation at AMSTC, the growth of the low temperature PECVD SiO2 was performed by Straglass. Inc. - Photolithographic process: step 3 to step 7 were used to form a layer of photoresist pattern exposing each bump pad. - The PECVD SiO2 coated on the bump pad was etched away with buffered HF solution. - The resistance of the Al pad was measured using a 4-point probe station. - The remaining photoresist was removed with an acetone spray. - Electroless Ni/Immersion Pd/Immersion Au Plating was selected as the UBM structure due to advantages such as photolithography not required, suitable for Al pad metallization, improvement of the intermetallic layer stability, low UBM process cost compared to electroplating, and improvement of the device life time in temperature cycling tests. Electroless Palladium, deposited as an additive metal layer of a few hundred nanometers on top of the nickel layer, was used to avoid “Black Pad” that can occur with immersion Au in electroless Ni [62]. 44
10. Final cleaning: After the passivation layer deposition, wafers were cleaned with alcohol, DI water, and blown dry for the next assembly steps. 11. Solderball placement, reflow and singulation will be discussed in the following section. 3.3 Preparation of SolderBrace Material With several years’ diligent work on the development of SolderBrace Material as the final WLCSP passivation layer, researchers from LORD have announced that this product is expected to be commercialized in the near future. However, at the initial stage of this research, a large number of test samples (see Table 3.3) having various chemical formulas were investigated, tested, and compared to optimize the SolderBracing process. The introduction of silica into the polymer compound plays an important role in reducing the CTE and cure shrinkage. According to published literature, smaller size filler such as nano- silica should be more suitable for the photopolymerization process because it would not scatter the UV light and hinder the photo reaction [63]. However, this type of filler also has some negative effects on the underfill materials due to interfacial interactions and large surface areas, including inhibiting the epoxy cure, reducing the composite glass transition temperature (Tg), low density, high moisture absorption, and high viscosity at high loading level [20, 63]. In this research, particular difficulties were encountered with nano-silica filled samples were in washing the unexposed areas. The nano-silica tended to form a "gel" which was hard to remove after developing. In addition, the CTE of nano-silica was not as low as regular silica. Larger size silica and high silica loading were found to be the preferred choice. Low CTE and low cure shrinkage were achieved with high loadings of silica. 45
Page 1 and 2:
Enhanced Polymer Passivation Layer
Page 3 and 4:
SolderBrace coatings were low tempe
Page 5 and 6: Table of Contents Abstract ........
Page 7 and 8: 4.4 Failure Analysis ..............
Page 9 and 10: List of Figures Figure 1.1 Trends i
Page 11 and 12: Figure 3.17 SAC305 Reflow profile .
Page 13 and 14: CHAPTER 1 INTRODUCTION In the era o
Page 15 and 16: This effect changes the package to
Page 17 and 18: 1.4 Solder Joint Fatigue Figure 1.2
Page 19 and 20: leading to the solder joint failure
Page 21 and 22: umped wafers. The coating is stenci
Page 23 and 24: 11 Bumped Wafer Print over ball Pre
Page 25 and 26: 2.1 Chip Scale Package Technology C
Page 27 and 28: Mountable with conventional assembl
Page 29 and 30: Figure 2.3 Cross section of a typic
Page 31 and 32: Table 2.1 Comparison between tradit
Page 33 and 34: In-Situ Bumped Wafers Placed Prefor
Page 35 and 36: of solder joint failure, and they o
Page 37 and 38: (a) (b) Figure 2.8(a). Metalized ph
Page 39 and 40: "underfilled" structure distributes
Page 41 and 42: have generally been the modificatio
Page 43 and 44: are “low temperature” wafer lev
Page 45 and 46: 2.3.4 Optimized SolderBrace Materia
Page 47 and 48: CHAPTER 3 WLCSP DIE FABRCIATION In
Page 49 and 50: Table 3.1 Test Die used for Reliabi
Page 51 and 52: Figure 3.4 Fabrication Process Flow
Page 53 and 54: spin coating. A layer of light sens
Page 55: layer, is investigated as a potenti
Page 59 and 60: Cyclopentanone, a colorless liquid
Page 61 and 62: used to check the basic spin and ph
Page 63 and 64: Figure 3.7 SolderBrace film thickne
Page 65 and 66: 6. Post-UV exposure bake: This step
Page 67 and 68: 8. Pattern characterization: The su
Page 69 and 70: offers the optimum flux release cha
Page 71 and 72: fatigue resistance, lower cost SAC
Page 73 and 74: Figure 3.12 Solder Ball Placement M
Page 75 and 76: of solder balls to the holes on the
Page 77 and 78: of thermal shock. If the temperatur
Page 79 and 80: Figure 3.17 SAC305 Reflow profile -
Page 81 and 82: foaming and high performance cleane
Page 83 and 84: - Polish clean: used the optimized
Page 85 and 86: Figure 3.22 SolderBrace printed waf
Page 87 and 88: Voids Figure 3.25 SolderBrace Mater
Page 89 and 90: cutting speed was set at a low valu
Page 91 and 92: Figure 4.2 Process Flow of Board As
Page 93 and 94: pitch, and bump diameter), and subs
Page 95 and 96: 4.2.4 X-Ray Inspection Figure 4.5 R
Page 97 and 98: Figure 4.6 Air to air thermal cycli
Page 99 and 100: Figure 4.7 Thermal Cycling Setup 87
Page 101 and 102: 4.4 Failure Analysis The main purpo
Page 103 and 104: Figure 4.10 Pad cratering failure o
Page 105 and 106: CHAPTER 5 FINITE ELEMENT ANALYSIS I
Page 107 and 108:
5.1.1 Modeling Approaches Due to th
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are shown in Figure 5.2. However, t
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5.1.2 Material Properties Many pack
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strain rate sensitivity. The evolut
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Morris et a1 [96] used a double pow
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focus on the time-dependent effects
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5.2 Modeling Procedure In this proj
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Figure 5.6 The diagonal symmetry mo
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5.2.3 Meshing Table 5.2 Anand const
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direction, but that the surface is
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PREP7 tref,398 ! set zero strain te
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5.2.7 Thermal Fatigue Life Predicti
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CHAPTER 6 CONCLUSIONS Wafer level c
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References 1. Future Trends in Elec
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23. Electronic Packaging and Interc
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48. Ultra Low Stress and Low Temper
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70. Factors for Successful Wafer-Le
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92. Microstructural Dependendence o
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111. Nonlinear Analysis of Full Mat
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Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ...

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