Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ...

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any residual photoresist in the exposed area while limiting removal of the unexposed photoresist. 15 seconds descum was used in this study. 8. Under bump metallization (UBM) deposition: WLCSP is a well established IC package technology. In its simplest form, this technology requires a UBM layer deposited and patterned over the passivation openings on a wafer. The UBM protects the initial bond pad from the solder bump metallurgy and provides a wettable bond pad for the subsequent solder ball bumping. - For die A, after the descum step the wafer was deposited with 4 layers of metals: titanium, nickel, copper and then gold (Ti/Ni/Cu/Au), using a CHA Industries Mark- 50 Electron Beam. These metal seed layers form a general under bump metallization structure for the WLCSPs which include an adhesion layer (Ti), a diffusion barrier layer (Ni), a solderable layer (Cu), and an oxidation barrier layer (Au). After that, the metal coated wafer was cleaned using acetone in an ultrasonic bath, leaving the patterned metal film, which is called “metal lift-off” process. 9. For die B, aluminum etchant (PAE etchant) was utilized to etch the exposed Al not covered by photoresist. The etch time was 26-28 minutes. The whole wafer was then sprayed with acetone to remove the photoresist on the Al pattern. Electroless Ni/Pd/Au Plating was selected as a new UBM structure for die B due to its advantages such as photolithography not required, suitable for Al pad metallization, improvement of the intermetallic layer stability, low UBM process cost compared to electroplating, and improvement of the device life time at temperature cycling tests. Electroless Palladium, deposited as an additive metal layer of a few hundred nanometers on top of the Nickel 42
layer, is investigated as a potential improvement of intermetallics formation with lead- free solders especially under high temperature conditions. Formation of passivation layer: This layer can serve to greatly reduce the transport of corrosive species to the underlying metal's surface. It also serves as a solder mask to prevent flow of solder along the interconnect traces. For die A, a thin layer of polyimide was used as the dielectric layer. The detail process steps are described as follows: - Polyimide adhesion promoter application: After the spin dry and dehydration bake, a layer of VN651 Polyimide Promoter was spin coated at 3000 rpm for 30 seconds on the wafer. The bonding of the polyimide promoter to the substrate was achieved during the 1 min soft bake at 120 o C as the priming chemistry is activated by temperature. - HD PI2556 polyimide coating: A layer of 0.7μm polyimide was spin coated at 3500 rpm for 30 seconds, and soft baked at 120 o C oven for 5-10 min. - Photolithographic process: step 3 to step 7 were repeated to form a layer of photoresist which exposed each bump pad. The photoresist as well as the polyimide coated on the bump pads was removed with AZ 400K during developing. - Acetone was sprayed onto the wafer to strip off the remaining photoresist layer. - Finally, the whole wafer was placed into a programmable oven to cure the polyimide film. The cure heating cycle converts the polyamic acid to the insoluble imide form and drives out remaining solvents. The curing profile consisted of : Heating from room temperature to 200 o C, ramp 4 o C /minute in air Hold time at 200 o C for 30 minutes in air 43
Page 1 and 2:
Enhanced Polymer Passivation Layer
Page 3 and 4: SolderBrace coatings were low tempe
Page 5 and 6: Table of Contents Abstract ........
Page 7 and 8: 4.4 Failure Analysis ..............
Page 9 and 10: List of Figures Figure 1.1 Trends i
Page 11 and 12: Figure 3.17 SAC305 Reflow profile .
Page 13 and 14: CHAPTER 1 INTRODUCTION In the era o
Page 15 and 16: This effect changes the package to
Page 17 and 18: 1.4 Solder Joint Fatigue Figure 1.2
Page 19 and 20: leading to the solder joint failure
Page 21 and 22: umped wafers. The coating is stenci
Page 23 and 24: 11 Bumped Wafer Print over ball Pre
Page 25 and 26: 2.1 Chip Scale Package Technology C
Page 27 and 28: Mountable with conventional assembl
Page 29 and 30: Figure 2.3 Cross section of a typic
Page 31 and 32: Table 2.1 Comparison between tradit
Page 33 and 34: In-Situ Bumped Wafers Placed Prefor
Page 35 and 36: of solder joint failure, and they o
Page 37 and 38: (a) (b) Figure 2.8(a). Metalized ph
Page 39 and 40: "underfilled" structure distributes
Page 41 and 42: have generally been the modificatio
Page 43 and 44: are “low temperature” wafer lev
Page 45 and 46: 2.3.4 Optimized SolderBrace Materia
Page 47 and 48: CHAPTER 3 WLCSP DIE FABRCIATION In
Page 49 and 50: Table 3.1 Test Die used for Reliabi
Page 51 and 52: Figure 3.4 Fabrication Process Flow
Page 53: spin coating. A layer of light sens
Page 57 and 58: 10. Final cleaning: After the passi
Page 59 and 60: Cyclopentanone, a colorless liquid
Page 61 and 62: used to check the basic spin and ph
Page 63 and 64: Figure 3.7 SolderBrace film thickne
Page 65 and 66: 6. Post-UV exposure bake: This step
Page 67 and 68: 8. Pattern characterization: The su
Page 69 and 70: offers the optimum flux release cha
Page 71 and 72: fatigue resistance, lower cost SAC
Page 73 and 74: Figure 3.12 Solder Ball Placement M
Page 75 and 76: of solder balls to the holes on the
Page 77 and 78: of thermal shock. If the temperatur
Page 79 and 80: Figure 3.17 SAC305 Reflow profile -
Page 81 and 82: foaming and high performance cleane
Page 83 and 84: - Polish clean: used the optimized
Page 85 and 86: Figure 3.22 SolderBrace printed waf
Page 87 and 88: Voids Figure 3.25 SolderBrace Mater
Page 89 and 90: cutting speed was set at a low valu
Page 91 and 92: Figure 4.2 Process Flow of Board As
Page 93 and 94: pitch, and bump diameter), and subs
Page 95 and 96: 4.2.4 X-Ray Inspection Figure 4.5 R
Page 97 and 98: Figure 4.6 Air to air thermal cycli
Page 99 and 100: Figure 4.7 Thermal Cycling Setup 87
Page 101 and 102: 4.4 Failure Analysis The main purpo
Page 103 and 104: Figure 4.10 Pad cratering failure o
Page 105 and 106:
CHAPTER 5 FINITE ELEMENT ANALYSIS I
Page 107 and 108:
5.1.1 Modeling Approaches Due to th
Page 109 and 110:
are shown in Figure 5.2. However, t
Page 111 and 112:
5.1.2 Material Properties Many pack
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strain rate sensitivity. The evolut
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Morris et a1 [96] used a double pow
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focus on the time-dependent effects
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5.2 Modeling Procedure In this proj
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Figure 5.6 The diagonal symmetry mo
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5.2.3 Meshing Table 5.2 Anand const
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direction, but that the surface is
Page 127 and 128:
PREP7 tref,398 ! set zero strain te
Page 129 and 130:
5.2.7 Thermal Fatigue Life Predicti
Page 131 and 132:
CHAPTER 6 CONCLUSIONS Wafer level c
Page 133 and 134:
References 1. Future Trends in Elec
Page 135 and 136:
23. Electronic Packaging and Interc
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48. Ultra Low Stress and Low Temper
Page 139 and 140:
70. Factors for Successful Wafer-Le
Page 141 and 142:
92. Microstructural Dependendence o
Page 143:
111. Nonlinear Analysis of Full Mat
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