Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ...
Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ...
Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ...
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Table 3.2 Silicon <strong>Wafer</strong> Cleaning Procedure [ 59-61 ]<br />
2. Insulation <strong>for</strong>mation: After wafer cleaning, a layer of silicon dioxide (SiO2) was <strong>for</strong>med<br />
on the silicon wafer surface acting as an insulation layer. This SiO2 barrier layer was<br />
produced using thermal oxidation. The wafers were thermally oxidized in a furnace at<br />
1000 o C under one atmosphere of pure oxygen <strong>for</strong> 2 hours. The thickness of the oxidation<br />
layer was measured to be 6084 Ǻ and the color of the wafer surface was blue green.<br />
3. Photoresist application and soft baking: In order to ensure good photoresist adhesion, the<br />
wafer surface was exposed to hexamethyldisilazane (HMDS) <strong>for</strong> 20 minutes prior to the<br />
40