Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ...
Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ...
Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ...
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Table of Contents<br />
Abstract ......................................................................................................................................... ii<br />
Acknowledgments........................................................................................................................ iv<br />
List of Tables ............................................................................................................................. viii<br />
List of Figures .............................................................................................................................. ix<br />
Chapter 1 Introduction ................................................................................................................ 1<br />
1.1 Trends in Integrated Circuit (IC) Package .................................................................. 1<br />
1.2 <strong>Chip</strong> <strong>Scale</strong> Package ..................................................................................................... 2<br />
1.3 <strong>Wafer</strong> <strong>Level</strong> <strong>Chip</strong> <strong>Scale</strong> Package .............................................................................. 4<br />
1.4 Solder Joint Fatigue .................................................................................................. 5<br />
1.5 Photo-definable Epoxy Resin ................................................................................... 6<br />
1.6 Research Objective and Outlines .............................................................................. 8<br />
Chapter 2 Literature Review ..................................................................................................... 13<br />
2.1 <strong>Chip</strong> <strong>Scale</strong> Package Technology ............................................................................... 13<br />
2.1.1 Background .................................................................................................... 13<br />
2.1.2 Advantages and Disadvantages ...................................................................... 14<br />
2.2 <strong>Wafer</strong> <strong>Level</strong> <strong>Chip</strong> <strong>Scale</strong> Packaging Technology ..................................................... 16<br />
2.2.1 Background .................................................................................................... 16<br />
2.2.2 WLCSP Process Flow .................................................................................... 20<br />
2.2.3 Technical Challenges ..................................................................................... 22<br />
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