Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ...
Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ... Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ...
Since the material developed by Lord is photo-sensitive, certain mask dimensions can not be photo-imaged. The current generation of SolderBrace commercialized is mainly targeted at CSP pitches ranging from 0.3mm to 1mm. In order to expand the application to fine pitch and maskless applications, a second-generation wafer-level Solderbrace material is now under development by Lord Scientists. It will improve the resolution by changing the curative formulation and material chemistry to minimize the amount of scattering that usually occurs in a thick coating [58]. 2.4 Summary Use of large die WLCSPs is a rapid growth area which needs cost effective packaging. To address the improved board level solder joint reliability, typical costly stress-relieving methods such as molding compounds and capillary underfills have been utilized by many designers. Wafer level solder bracing is a new technology and cost effective solution to WLCSP protection. It delivers the improved reliability by conventional tools and short process times. The photo-defined SolderBrace materials are similar to polyimide in their UV processing steps, but have extra flexibility of being processed in other ways such as printing over balled wafer. 34
CHAPTER 3 WLCSP DIE FABRCIATION In this study, the WLSCP was designed as a daisy chain to allow in-situ measurement of the resistance during the accelerated temperature cycling testing. Area array solder bumps were used to form electrical connections to the PCB. WLCSPs with and without SolderBrace materials were fabricated using known standard methods at the Alabama Microelectronics Science and Technology Center (AMSTC). The die fabrication process will be discussed in this chapter. 3.1 Test Die Dimension As shown in Figure 3.1, the die size was 6mm x 6mm, with a bump diameter of 300μm in a 6 x 6 (36 I/O) full area array pattern on a 800μm pitch. The wafer, e.g. die, thickness was approximately 560 μm. “LASI 7” software was utilized to design the geometry of the die as well as the photomasks. 35
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CHAPTER 3<br />
WLCSP DIE FABRCIATION<br />
In this study, the WLSCP was designed as a daisy chain to allow in-situ measurement of<br />
the resistance during the accelerated temperature cycling testing. Area array solder bumps were<br />
used to <strong>for</strong>m electrical connections to the PCB. WLCSPs with and without SolderBrace materials<br />
were fabricated using known standard methods at the Alabama Microelectronics Science and<br />
Technology Center (AMSTC). The die fabrication process will be discussed in this chapter.<br />
3.1 Test Die Dimension<br />
As shown in Figure 3.1, the die size was 6mm x 6mm, with a bump diameter of 300μm in<br />
a 6 x 6 (36 I/O) full area array pattern on a 800μm pitch. The wafer, e.g. die, thickness was<br />
approximately 560 μm. “LASI 7” software was utilized to design the geometry of the die as well<br />
as the photomasks.<br />
35
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