Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ...
Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ... Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ...
Figure 2.14 Process flow of a back grind and double bump coating-type wafer level solder brace Figure 2.15 Application method of SolderBrace by photo definition 32
2.3.4 Optimized SolderBrace Material developed by Lord Corporation In the development of a wafer-level underfill targeted at fulfilling the needs of future designs such as fine pitch and 3D wafer level packaging, Lord Corporation has developed a new SolderBrace Material which is being presented as an alternative to underfill. It is a photo- imigable frontside molding compound with a low CTE that can increases the reliability of the package without added cost. More specifically, this SolderBrace technology is a partial underfill in which a thick coating is deposited on the underside of the die at the wafer level by utilizing the same back-end tools normally used in polyimide processing. The wafer-coated material is either spin coated or printed first, and then goes through a low-temperature pre-bake and UV exposure process. The cross section of a SolderBrace supported solder bump is shown in the Figure 2.16. Figure 2.16 Cross section of a WLCSP 250µm solder bump supported by the thick front-side passivation SolderBrace [58]. 33
- Page 1 and 2: Enhanced Polymer Passivation Layer
- Page 3 and 4: SolderBrace coatings were low tempe
- Page 5 and 6: Table of Contents Abstract ........
- Page 7 and 8: 4.4 Failure Analysis ..............
- Page 9 and 10: List of Figures Figure 1.1 Trends i
- Page 11 and 12: Figure 3.17 SAC305 Reflow profile .
- Page 13 and 14: CHAPTER 1 INTRODUCTION In the era o
- Page 15 and 16: This effect changes the package to
- Page 17 and 18: 1.4 Solder Joint Fatigue Figure 1.2
- Page 19 and 20: leading to the solder joint failure
- Page 21 and 22: umped wafers. The coating is stenci
- Page 23 and 24: 11 Bumped Wafer Print over ball Pre
- Page 25 and 26: 2.1 Chip Scale Package Technology C
- Page 27 and 28: Mountable with conventional assembl
- Page 29 and 30: Figure 2.3 Cross section of a typic
- Page 31 and 32: Table 2.1 Comparison between tradit
- Page 33 and 34: In-Situ Bumped Wafers Placed Prefor
- Page 35 and 36: of solder joint failure, and they o
- Page 37 and 38: (a) (b) Figure 2.8(a). Metalized ph
- Page 39 and 40: "underfilled" structure distributes
- Page 41 and 42: have generally been the modificatio
- Page 43: are “low temperature” wafer lev
- Page 47 and 48: CHAPTER 3 WLCSP DIE FABRCIATION In
- Page 49 and 50: Table 3.1 Test Die used for Reliabi
- Page 51 and 52: Figure 3.4 Fabrication Process Flow
- Page 53 and 54: spin coating. A layer of light sens
- Page 55 and 56: layer, is investigated as a potenti
- Page 57 and 58: 10. Final cleaning: After the passi
- Page 59 and 60: Cyclopentanone, a colorless liquid
- Page 61 and 62: used to check the basic spin and ph
- Page 63 and 64: Figure 3.7 SolderBrace film thickne
- Page 65 and 66: 6. Post-UV exposure bake: This step
- Page 67 and 68: 8. Pattern characterization: The su
- Page 69 and 70: offers the optimum flux release cha
- Page 71 and 72: fatigue resistance, lower cost SAC
- Page 73 and 74: Figure 3.12 Solder Ball Placement M
- Page 75 and 76: of solder balls to the holes on the
- Page 77 and 78: of thermal shock. If the temperatur
- Page 79 and 80: Figure 3.17 SAC305 Reflow profile -
- Page 81 and 82: foaming and high performance cleane
- Page 83 and 84: - Polish clean: used the optimized
- Page 85 and 86: Figure 3.22 SolderBrace printed waf
- Page 87 and 88: Voids Figure 3.25 SolderBrace Mater
- Page 89 and 90: cutting speed was set at a low valu
- Page 91 and 92: Figure 4.2 Process Flow of Board As
- Page 93 and 94: pitch, and bump diameter), and subs
Figure 2.14 Process flow of a back grind and double bump coating-type wafer level solder brace<br />
Figure 2.15 Application method of SolderBrace by photo definition<br />
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