Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ...
Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ...
Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ...
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"underfilled" structure distributes the stress on the solder columns and protects the redistribution<br />
layer from stress concentrations. Such structures have shown ~2x the cycles to first fail in<br />
thermal cycling [50].<br />
(a) (b)<br />
(c)<br />
Figure 2.10 Examples of Microspring technology (a). Probe Cards (b). Sockets Interposers (c).<br />
Die Size Spring Grid Array (DSSGA) Modules<br />
National Semiconductor enlarged the passivation layer opening at the solder die interface<br />
to improve the solder joint reliability [51], and a WLCSP technology evaluated by Keser in<br />
Motorola SPS demonstrated that board level solder joint reliability of the WLCSP can be<br />
improved through wafer thinning [52].<br />
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