Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ...

(a) (b)
Figure 2.8(a). Metalized photo-paternable silicone bumps and (b). Stencil printed silicon bumps
[48]
Another stress release method was developed by the Fujitsu Co. by forming high copper
posts to increase the gap between the chip and PCB. This chip-sized package is marketed by the
trademark name SuperCSP [46]. Figure 2.9 shows a cross-sectional view and layer structure of
this package. The processes of making the SuperCSP involve several main steps such as the
redistribution traces and metal post forming, encapsulating the wafer, and peeling the film. First
the peripheral pads on the wafer are rearranged in a real array pattern after photolithographic
plating. About 100 µm high metal posts are then fabricated on the wafer. After encapsulating the
entire surface of the wafer, a package having the same size as the chip is fabricated using a
wafer-level packaging method. The connecting portion of copper post and solder ball has a
strong structure that can tolerate the stress because solder balls catch hold of the entire surface of
copper posts, which stick out from the encapsulant and have a mound-like structure [49].
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