Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ...
Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ...
Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ...
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Table 2.1 Comparison between traditional packaging and wafer level packaging [8]<br />
Traditional IC Packaging <strong>Wafer</strong> level Packaging<br />
Current Situation<br />
<strong>Wafer</strong> is probed, diced and sorted<br />
ICs packaged away from fab<br />
ICs are packaged one at a time<br />
Burn in per<strong>for</strong>med in sockets<br />
Device tested two to three times<br />
Current Situation<br />
Power and ground taken from PCB<br />
High pin counts required<br />
Less than optimal power to<br />
per<strong>for</strong>mance efficiency<br />
All function in the chip<br />
More complex substrate required<br />
Lead inductance concerns<br />
19<br />
Current Opportunity<br />
<strong>Wafer</strong> moved directly to packaging<br />
ICs packaged in fab<br />
ICs are packaged en masse<br />
Burn in per<strong>for</strong>med on wafer<br />
Device tested once<br />
Next generation opportunity<br />
Power and ground distributed in<br />
assembled structure<br />
Lower external I/O possible<br />
Power to per<strong>for</strong>mance efficiency<br />
increase possible<br />
Function shared between package and<br />
chip<br />
Simpler substrates possible<br />
Lead inductance nearly eliminated