Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ...
Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ... Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ...
Figure 2.2 Example of a flex tape style CSP [25] 2.2 Wafer Level Chip Scale Packaging Technology 2.2.1 Background Instead of the traditional process of assembling individual units in packages after dicing them from a wafer, wafer level chip scale packaging technology packages an integrated circuit at the wafer level. This process is basically an extension of the wafer fab processes, where the device protections and interconnects are accomplished using the traditional fab processes and tools. In the final form, the device is essentially a die with an array pattern of solder balls or bumps attached at an I/O pitch that is compatible with traditional circuit board assembly processes [28]. One of the features of most WLCSP structures is the application of a metal layer to redistribute the fine pitch pads on the chip to larger pitch area arrayed pads with much taller solder joints on the substrate. This technology not only provides the means of external connection, but also improves the reliability by allowing the use of larger and more robust balls for interconnection (Figure 2.3) [29]. 16
Figure 2.3 Cross section of a typical Polyimide-RDL WLCSP [28] WLCSP combines the conventional chip scale package advantages of thinning, miniaturizing, low mass packaged chips, and ease of handling with an efficient volume production approach based upon batch packaging at the wafer level [30]. Table 2.1 compares the differences between traditional packaging and wafer level packaging [8]. Many companies around the world are developing or have begun providing devices packaged in chip size fashion. Amkor, Fujitsu, Shell Case, Chip Scale, Oki, Unitive, Flip Chip Technologies (FCT), Fraunhoffer Technical University, Tessera, and some other companies have all shown diligence in the area [8]. Although all of these technologies result in packaged area array chips, the technologies still differ, sometimes significantly, in processing steps such as redistribution technologies, encapsulated technologies, and flex tape technologies. Table 2.2 lists and compares the key process features for most of manufactures [6] while Figure 2.4 shows some of their products such as (1). The Casio Wrist Camera with super CSP 48 developed by Fuji, (2). The Ultra CSP by Flip chip International, (3). The National Semiconductor Micro- SMD, (4). The Ericsson Bluetooth, and (5). The Tessera Wafer-Level Camera (WLC) technologies. 17
- Page 1 and 2: Enhanced Polymer Passivation Layer
- Page 3 and 4: SolderBrace coatings were low tempe
- Page 5 and 6: Table of Contents Abstract ........
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- Page 9 and 10: List of Figures Figure 1.1 Trends i
- Page 11 and 12: Figure 3.17 SAC305 Reflow profile .
- Page 13 and 14: CHAPTER 1 INTRODUCTION In the era o
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- Page 17 and 18: 1.4 Solder Joint Fatigue Figure 1.2
- Page 19 and 20: leading to the solder joint failure
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- Page 25 and 26: 2.1 Chip Scale Package Technology C
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- Page 31 and 32: Table 2.1 Comparison between tradit
- Page 33 and 34: In-Situ Bumped Wafers Placed Prefor
- Page 35 and 36: of solder joint failure, and they o
- Page 37 and 38: (a) (b) Figure 2.8(a). Metalized ph
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- Page 43 and 44: are “low temperature” wafer lev
- Page 45 and 46: 2.3.4 Optimized SolderBrace Materia
- Page 47 and 48: CHAPTER 3 WLCSP DIE FABRCIATION In
- Page 49 and 50: Table 3.1 Test Die used for Reliabi
- Page 51 and 52: Figure 3.4 Fabrication Process Flow
- Page 53 and 54: spin coating. A layer of light sens
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- Page 57 and 58: 10. Final cleaning: After the passi
- Page 59 and 60: Cyclopentanone, a colorless liquid
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Figure 2.2 Example of a flex tape style CSP [25]<br />
2.2 <strong>Wafer</strong> <strong>Level</strong> <strong>Chip</strong> <strong>Scale</strong> Packaging Technology<br />
2.2.1 Background<br />
Instead of the traditional process of assembling individual units in packages after dicing<br />
them from a wafer, wafer level chip scale packaging technology packages an integrated circuit at<br />
the wafer level. This process is basically an extension of the wafer fab processes, where the<br />
device protections and interconnects are accomplished using the traditional fab processes and<br />
tools. In the final <strong>for</strong>m, the device is essentially a die with an array pattern of solder balls or<br />
bumps attached at an I/O pitch that is compatible with traditional circuit board assembly<br />
processes [28]. One of the features of most WLCSP structures is the application of a metal layer<br />
to redistribute the fine pitch pads on the chip to larger pitch area arrayed pads with much taller<br />
solder joints on the substrate. This technology not only provides the means of external<br />
connection, but also improves the reliability by allowing the use of larger and more robust balls<br />
<strong>for</strong> interconnection (Figure 2.3) [29].<br />
16
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