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Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ...

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fatigue lifetime of a solder joint is proportional to the square of the bump standoff and inversely<br />

proportional to the square of DNP, Δα, and ΔT. There<strong>for</strong>e, the solder joint reliability can be<br />

enhanced by using smaller die, lower CTE mismatch, smaller temperature range of operation and<br />

the higher standoff height [13].<br />

Figure 1.3 Coffin-Manson low cycle fatigue equation<br />

Figure 1.4 Distance from netural point <strong>for</strong> a BGA type package [14]<br />

1.5 Photo-definable Epoxy Resin<br />

Epoxy resins have long been widely used in industries due to their ease of processing, less<br />

curing shrinkage, excellent heat and chemical resistance, low cost, and extreme versatility in<br />

chemical structures. However, the large CTE mismatch between the neat epoxy resin (50-80<br />

ppm/K) and the silicon chip (2.8 ppm/K) results in a huge amount of stress at the interface<br />

6<br />

Reduce Δα can<br />

increase fatigue life

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