- Page 1 and 2: Enhanced Polymer Passivation Layer
- Page 3 and 4: SolderBrace coatings were low tempe
- Page 5 and 6: Table of Contents Abstract ........
- Page 7 and 8: 4.4 Failure Analysis ..............
- Page 9 and 10: List of Figures Figure 1.1 Trends i
- Page 11 and 12: Figure 3.17 SAC305 Reflow profile .
- Page 13: CHAPTER 1 INTRODUCTION In the era o
- Page 17 and 18: 1.4 Solder Joint Fatigue Figure 1.2
- Page 19 and 20: leading to the solder joint failure
- Page 21 and 22: umped wafers. The coating is stenci
- Page 23 and 24: 11 Bumped Wafer Print over ball Pre
- Page 25 and 26: 2.1 Chip Scale Package Technology C
- Page 27 and 28: Mountable with conventional assembl
- Page 29 and 30: Figure 2.3 Cross section of a typic
- Page 31 and 32: Table 2.1 Comparison between tradit
- Page 33 and 34: In-Situ Bumped Wafers Placed Prefor
- Page 35 and 36: of solder joint failure, and they o
- Page 37 and 38: (a) (b) Figure 2.8(a). Metalized ph
- Page 39 and 40: "underfilled" structure distributes
- Page 41 and 42: have generally been the modificatio
- Page 43 and 44: are “low temperature” wafer lev
- Page 45 and 46: 2.3.4 Optimized SolderBrace Materia
- Page 47 and 48: CHAPTER 3 WLCSP DIE FABRCIATION In
- Page 49 and 50: Table 3.1 Test Die used for Reliabi
- Page 51 and 52: Figure 3.4 Fabrication Process Flow
- Page 53 and 54: spin coating. A layer of light sens
- Page 55 and 56: layer, is investigated as a potenti
- Page 57 and 58: 10. Final cleaning: After the passi
- Page 59 and 60: Cyclopentanone, a colorless liquid
- Page 61 and 62: used to check the basic spin and ph
- Page 63 and 64: Figure 3.7 SolderBrace film thickne
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6. Post-UV exposure bake: This step
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8. Pattern characterization: The su
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offers the optimum flux release cha
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fatigue resistance, lower cost SAC
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Figure 3.12 Solder Ball Placement M
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of solder balls to the holes on the
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of thermal shock. If the temperatur
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Figure 3.17 SAC305 Reflow profile -
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foaming and high performance cleane
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- Polish clean: used the optimized
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Figure 3.22 SolderBrace printed waf
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Voids Figure 3.25 SolderBrace Mater
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cutting speed was set at a low valu
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Figure 4.2 Process Flow of Board As
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pitch, and bump diameter), and subs
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4.2.4 X-Ray Inspection Figure 4.5 R
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Figure 4.6 Air to air thermal cycli
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Figure 4.7 Thermal Cycling Setup 87
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4.4 Failure Analysis The main purpo
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Figure 4.10 Pad cratering failure o
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CHAPTER 5 FINITE ELEMENT ANALYSIS I
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5.1.1 Modeling Approaches Due to th
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are shown in Figure 5.2. However, t
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5.1.2 Material Properties Many pack
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strain rate sensitivity. The evolut
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Morris et a1 [96] used a double pow
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focus on the time-dependent effects
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5.2 Modeling Procedure In this proj
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Figure 5.6 The diagonal symmetry mo
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5.2.3 Meshing Table 5.2 Anand const
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direction, but that the surface is
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PREP7 tref,398 ! set zero strain te
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5.2.7 Thermal Fatigue Life Predicti
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CHAPTER 6 CONCLUSIONS Wafer level c
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References 1. Future Trends in Elec
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23. Electronic Packaging and Interc
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48. Ultra Low Stress and Low Temper
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70. Factors for Successful Wafer-Le
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92. Microstructural Dependendence o
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111. Nonlinear Analysis of Full Mat