Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ...

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38. Critical Issues of Wafer Level Chip Scale Package (WLCSP) With Emphasis on Cost Analysis and Solder Joint Reliability, John H. Lau, IEEE Transactions on electronic packaging manufacturing, Vol. 25, No. 1, 2002 39. http://www.siliconfareast.com/rel.html 40. A Study of Board Level Reliability Test with Bump Structure of WLCSP Lead-free Solder Joints, Kao, Frank, Proceedings of Technical Papers, IMPACT, p 323-326, 2007 41. Board-Level Reliability of Pb-Free Solder Joints of TSOP and Various CSPs, Seung Wook Yoon, IEEE Transactions on electronic packaging manufacturing, Vol. 28, No. 2, 2005 42. Low Cost Flip Chip Technologies: for DCA, WLCSP, and PBGA Assembles, John H. Lau, McGraw-Hill (New York, ZOOO), pp. 324-329,2000 43. Reliability Characterization in Ultra CSPTM Package Development, Hong Yang, Electronic Components and Technology Conference, p1376-1383,2000 44. W. C. Lo et al, Hectronics Packaging Technology Conf, pp, 218-222,2002 45. Integration of a Low Stress Photopatternable Silicone into a Wafer Level Package, G. Gardner et al, Proc 54th Electronic Components and Technology Conf, Las Vegas, 2004, pp. 170-174 46. Chip Scale Package CSP: Design, Materials, and applications, John H. Lau, McGraw-Hill, pp. 487-494,1999 47. Lost cost flip chip technologies for DCA. W LCSP, and PBGA Assemblies, John H. Lau, McGraw-Hill, pp. 344-348,2000 124
48. Ultra Low Stress and Low Temperature Patternable silicone materials for applications within microelectronics, Microelectronic Engineering,Volume 76, Issues 1-4, P 212-218, 2004 49. SuperCSP, Kawahara, Toshimi, IEEE Transactions on Advanced Packaging, v 23, n 2, p 215-219, 2000 50. Wafer Level Package using Double Balls, Toepper, M., Proceedings of the International Symposium and Exhibition on Advanced Packaging Materials Processes, Properties and Interfaces, p 198-200, 2000 51. Numerical and experimental analysis of large passivation opening for solder joint reliability improvement of micro SMD packages, Zhang L, Microelectron Reliab, 2004. 52. WL-CSP Reliability with Various Solder Alloys and Die Thickness, Keser, WetzL, Microelectron Reliab, 2004 53. Non-Capillary Protection Options for WLCSPs, Russell Stapleton,2008 54. Multifunctional Coatings for Wafer Level Chip Scale Packaging, Stapleton Russell, European Microelectronics and Packaging Conference, EMPC 2009 55. Solder Joint Reliability of a Polymer Reinforced Wafer Level Package, Kim, Deok-Hoon, Proceedings - Electronic Components and Technology Conference, p 1347-1354, 2002 56. Flip Chip with Integrated Solder Mask and Underfill, Gilleo,K, US 6228678 B1 57. Semiconductor Flip-Chip Assembly with Pre-applied Encapsulating Layers, US 6297560 B1, 2001 58. Commercializing a WLCSP Passivation Layer Solution, Debra Vogler, Solid State Technology,2009 125
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Enhanced Polymer Passivation Layer
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SolderBrace coatings were low tempe
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Table of Contents Abstract ........
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4.4 Failure Analysis ..............
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List of Figures Figure 1.1 Trends i
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Figure 3.17 SAC305 Reflow profile .
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CHAPTER 1 INTRODUCTION In the era o
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This effect changes the package to
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1.4 Solder Joint Fatigue Figure 1.2
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leading to the solder joint failure
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umped wafers. The coating is stenci
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11 Bumped Wafer Print over ball Pre
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2.1 Chip Scale Package Technology C
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Mountable with conventional assembl
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Figure 2.3 Cross section of a typic
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Table 2.1 Comparison between tradit
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In-Situ Bumped Wafers Placed Prefor
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of solder joint failure, and they o
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(a) (b) Figure 2.8(a). Metalized ph
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"underfilled" structure distributes
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have generally been the modificatio
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are “low temperature” wafer lev
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2.3.4 Optimized SolderBrace Materia
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CHAPTER 3 WLCSP DIE FABRCIATION In
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Table 3.1 Test Die used for Reliabi
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Figure 3.4 Fabrication Process Flow
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spin coating. A layer of light sens
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layer, is investigated as a potenti
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10. Final cleaning: After the passi
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Cyclopentanone, a colorless liquid
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used to check the basic spin and ph
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Figure 3.7 SolderBrace film thickne
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6. Post-UV exposure bake: This step
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8. Pattern characterization: The su
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offers the optimum flux release cha
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fatigue resistance, lower cost SAC
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Figure 3.12 Solder Ball Placement M
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of solder balls to the holes on the
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of thermal shock. If the temperatur
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Figure 3.17 SAC305 Reflow profile -
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foaming and high performance cleane
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- Polish clean: used the optimized
Page 85 and 86: Figure 3.22 SolderBrace printed waf
Page 87 and 88: Voids Figure 3.25 SolderBrace Mater
Page 89 and 90: cutting speed was set at a low valu
Page 91 and 92: Figure 4.2 Process Flow of Board As
Page 93 and 94: pitch, and bump diameter), and subs
Page 95 and 96: 4.2.4 X-Ray Inspection Figure 4.5 R
Page 97 and 98: Figure 4.6 Air to air thermal cycli
Page 99 and 100: Figure 4.7 Thermal Cycling Setup 87
Page 101 and 102: 4.4 Failure Analysis The main purpo
Page 103 and 104: Figure 4.10 Pad cratering failure o
Page 105 and 106: CHAPTER 5 FINITE ELEMENT ANALYSIS I
Page 107 and 108: 5.1.1 Modeling Approaches Due to th
Page 109 and 110: are shown in Figure 5.2. However, t
Page 111 and 112: 5.1.2 Material Properties Many pack
Page 113 and 114: strain rate sensitivity. The evolut
Page 115 and 116: Morris et a1 [96] used a double pow
Page 117 and 118: focus on the time-dependent effects
Page 119 and 120: 5.2 Modeling Procedure In this proj
Page 121 and 122: Figure 5.6 The diagonal symmetry mo
Page 123 and 124: 5.2.3 Meshing Table 5.2 Anand const
Page 125 and 126: direction, but that the surface is
Page 127 and 128: PREP7 tref,398 ! set zero strain te
Page 129 and 130: 5.2.7 Thermal Fatigue Life Predicti
Page 131 and 132: CHAPTER 6 CONCLUSIONS Wafer level c
Page 133 and 134: References 1. Future Trends in Elec
Page 135: 23. Electronic Packaging and Interc
Page 139 and 140: 70. Factors for Successful Wafer-Le
Page 141 and 142: 92. Microstructural Dependendence o
Page 143: 111. Nonlinear Analysis of Full Mat
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