Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ...

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11. Solder Joint Fatigue Models: Review and applicability to chip scale packages Lee, W.W. Nguyen, Microelectronics Reliability, v 40, n 2, p 231-244, 2000 12. Solder Joint Reliability Prediction for Multiple Environments, Andrew E. Perkins, Technology & Engineering, P19, 2008 13. The Electronic Packaging, G. R. Blackwell, Morgan Hill, California: CRC Press, IEEE Press, 1999 14. Printed Circuit Handbook , McGraw-Hill Professional, 6 edition, P58.24, 2007 15. SU-8 Thick Photoresist Processing as a Functional Material for MEMS Applications Conradie, Ewan H. Moore, Journal of Micromechanics and Microengineering, v 12, n 4, p 368- 374, 2002 16. The Properties of Epoxy Resin Coated Silica Fillers Composites Teh, P.L, Materials Letters, v 61, n 11-12, p 2156-2158, 2007 17. Electronics Packaging of High Speed Circuitry, S. G. Konsowski, New York: McGraw- Hill, 1997 18. Polymer, K. K. Baikerikar, vol. 42, pp. 431-441, 2001 19. F. Bauer, H. Ernst, D. Hirsch, S. Naumov, M. Pelzing, V.Sauerland, and R. Mehnert, Macromol.Chem.Phys., vol. 205, pp. 1587-1593, 2004. 20. J. Zhang, K. L. Tan, G. D. Hong, L. J. Yang, and H. Q. Gong, Journal of Micromechanics and Microengineering,vol. 11, pp. 20-26, 2001. 21. Y. Sun and C. P. Wong, '54 Electronic Components and Technology Conference, Las Vegas, pp. 477-483, 2004. 22. Photo-definable Nanocomposite for Wafer Level Packaging, Sun, Yangyang, Proceedings - Electronic Components and Technology Conference, v 1, p 179-184, 2005 122
23. Electronic Packaging and Interconnection Handbook, Charles A Harper, 2004 24. Chip Scale Package, http://www.siliconfareast.com/csp.htm 25. New Enhanced Flex Based Chip Scale Package with Improved Board Level Reliability, R. D. Schueller, SMTA Emerging Technologies Symposium, 1997 26. Chip Scale Packaging Guidelines, Reza Ghaffarian, Distributed by ITRI, Interconnection Technology Research Institute, January 2000, pp.40 27. The Nordic Electronic Packaging Guideline Chapter D: CSP 28. Wafer Level Chip Scale Package (WLCSP), Freescale Semiconductor, Inc., 2009. 29. A New Thermal-Fatigue Life Prediction Model for Wafer Level Chip Scale Package (WLCSP) Solder Joints, John H. Lau, Journal of Electronic Packaging Vol. 124, pp 212- 220, 2002 30. http://www.flipchips.com/tutorial31.html 31. http://www.ieec.binghamton.edu/ieec/teardown/casio_wrist_camera.htm 32. http://www.flipchip.com/bump_heights-160um.html 33. http://www.national.com/appinfo/microsmd/ 34. Novel Approach Yields 100mW Bluetooth Amplifier, Maxim,2002 35. http://www.tessera.com/technologies/imagingandoptics 36. http://en.wikipedia.org/wiki/Front_and_back_ends 37. Backend Processing for Wafer Level Chip Scale Packaging, Hunt, John R, Proceedings of the IEEE/CPMT International Electronics Manufacturing Technology (IEMT) Symposium, p 187-193, 2003 123
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Enhanced Polymer Passivation Layer
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SolderBrace coatings were low tempe
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Table of Contents Abstract ........
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4.4 Failure Analysis ..............
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List of Figures Figure 1.1 Trends i
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Figure 3.17 SAC305 Reflow profile .
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CHAPTER 1 INTRODUCTION In the era o
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This effect changes the package to
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1.4 Solder Joint Fatigue Figure 1.2
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leading to the solder joint failure
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umped wafers. The coating is stenci
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11 Bumped Wafer Print over ball Pre
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2.1 Chip Scale Package Technology C
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Mountable with conventional assembl
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Figure 2.3 Cross section of a typic
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Table 2.1 Comparison between tradit
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In-Situ Bumped Wafers Placed Prefor
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of solder joint failure, and they o
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(a) (b) Figure 2.8(a). Metalized ph
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"underfilled" structure distributes
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have generally been the modificatio
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are “low temperature” wafer lev
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2.3.4 Optimized SolderBrace Materia
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CHAPTER 3 WLCSP DIE FABRCIATION In
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Table 3.1 Test Die used for Reliabi
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Figure 3.4 Fabrication Process Flow
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spin coating. A layer of light sens
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layer, is investigated as a potenti
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10. Final cleaning: After the passi
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Cyclopentanone, a colorless liquid
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used to check the basic spin and ph
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Figure 3.7 SolderBrace film thickne
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6. Post-UV exposure bake: This step
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8. Pattern characterization: The su
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offers the optimum flux release cha
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fatigue resistance, lower cost SAC
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Figure 3.12 Solder Ball Placement M
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of solder balls to the holes on the
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of thermal shock. If the temperatur
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Figure 3.17 SAC305 Reflow profile -
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foaming and high performance cleane
Page 83 and 84: - Polish clean: used the optimized
Page 85 and 86: Figure 3.22 SolderBrace printed waf
Page 87 and 88: Voids Figure 3.25 SolderBrace Mater
Page 89 and 90: cutting speed was set at a low valu
Page 91 and 92: Figure 4.2 Process Flow of Board As
Page 93 and 94: pitch, and bump diameter), and subs
Page 95 and 96: 4.2.4 X-Ray Inspection Figure 4.5 R
Page 97 and 98: Figure 4.6 Air to air thermal cycli
Page 99 and 100: Figure 4.7 Thermal Cycling Setup 87
Page 101 and 102: 4.4 Failure Analysis The main purpo
Page 103 and 104: Figure 4.10 Pad cratering failure o
Page 105 and 106: CHAPTER 5 FINITE ELEMENT ANALYSIS I
Page 107 and 108: 5.1.1 Modeling Approaches Due to th
Page 109 and 110: are shown in Figure 5.2. However, t
Page 111 and 112: 5.1.2 Material Properties Many pack
Page 113 and 114: strain rate sensitivity. The evolut
Page 115 and 116: Morris et a1 [96] used a double pow
Page 117 and 118: focus on the time-dependent effects
Page 119 and 120: 5.2 Modeling Procedure In this proj
Page 121 and 122: Figure 5.6 The diagonal symmetry mo
Page 123 and 124: 5.2.3 Meshing Table 5.2 Anand const
Page 125 and 126: direction, but that the surface is
Page 127 and 128: PREP7 tref,398 ! set zero strain te
Page 129 and 130: 5.2.7 Thermal Fatigue Life Predicti
Page 131 and 132: CHAPTER 6 CONCLUSIONS Wafer level c
Page 133: References 1. Future Trends in Elec
Page 137 and 138: 48. Ultra Low Stress and Low Temper
Page 139 and 140: 70. Factors for Successful Wafer-Le
Page 141 and 142: 92. Microstructural Dependendence o
Page 143: 111. Nonlinear Analysis of Full Mat
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