Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ...

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still over-estimated by approximately 20%. As the Solderbrace material is still new, further investigation is required to determine its exact material properties. In addition to material properties deviations may result from various model parameters such as element type, or shape and size. Characteristic life Na Table 5.5 Summary of the characteristic life Experimental Result Prediction Result 510 cycles 613 cycles 118
CHAPTER 6 CONCLUSIONS Wafer level chip scale package (WLCSP) designs have been used in many consumer products, and thus they are competitive in cost, size, yield, and technology. Solder joint reliability is a major concern for advanced WLCSPs. Typical stress-relieving methods such as capillary underfills and molding compounds have not been the preferred solutions due to the extra packaging cost they bring into the assembly process. Instead, successful low cost reliability solutions have generally been the adaptation of wafer level backend packaging processes such as modification of the redistribution layer materials, solder selection, or metal pad thickness. However, the increased performance is limited. In this research, a cost effective solution to WLCSP reliability improvement can be enabled through wafer level coatings (SolderBrace coating). This new approach is presented to reexamine the final passivation layer as more than a dielectric, but also a partial underfill. SolderBrace coating adds a mechanical buffer to the front side of the WLCSP and delivers improved reliability with conventional tools, short process times and lower costs. Test WLCSPs, including the SolderBrace coated WLCSPs and standard non-coated WLCSPs, were designed and fabricated with known standard fabrication procedures. The processing of the SolderBrace coatings was achieved by two different methods: Coating-type solder bracing and Maskless printing over solder balled wafer. These coatings were low 119
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Enhanced Polymer Passivation Layer
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SolderBrace coatings were low tempe
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Table of Contents Abstract ........
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4.4 Failure Analysis ..............
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List of Figures Figure 1.1 Trends i
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Figure 3.17 SAC305 Reflow profile .
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CHAPTER 1 INTRODUCTION In the era o
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This effect changes the package to
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1.4 Solder Joint Fatigue Figure 1.2
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leading to the solder joint failure
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umped wafers. The coating is stenci
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11 Bumped Wafer Print over ball Pre
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2.1 Chip Scale Package Technology C
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Mountable with conventional assembl
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Figure 2.3 Cross section of a typic
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Table 2.1 Comparison between tradit
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In-Situ Bumped Wafers Placed Prefor
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of solder joint failure, and they o
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(a) (b) Figure 2.8(a). Metalized ph
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"underfilled" structure distributes
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have generally been the modificatio
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are “low temperature” wafer lev
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2.3.4 Optimized SolderBrace Materia
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CHAPTER 3 WLCSP DIE FABRCIATION In
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Table 3.1 Test Die used for Reliabi
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Figure 3.4 Fabrication Process Flow
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spin coating. A layer of light sens
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layer, is investigated as a potenti
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10. Final cleaning: After the passi
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Cyclopentanone, a colorless liquid
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used to check the basic spin and ph
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Figure 3.7 SolderBrace film thickne
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6. Post-UV exposure bake: This step
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8. Pattern characterization: The su
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offers the optimum flux release cha
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fatigue resistance, lower cost SAC
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Figure 3.12 Solder Ball Placement M
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of solder balls to the holes on the
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of thermal shock. If the temperatur
Page 79 and 80: Figure 3.17 SAC305 Reflow profile -
Page 81 and 82: foaming and high performance cleane
Page 83 and 84: - Polish clean: used the optimized
Page 85 and 86: Figure 3.22 SolderBrace printed waf
Page 87 and 88: Voids Figure 3.25 SolderBrace Mater
Page 89 and 90: cutting speed was set at a low valu
Page 91 and 92: Figure 4.2 Process Flow of Board As
Page 93 and 94: pitch, and bump diameter), and subs
Page 95 and 96: 4.2.4 X-Ray Inspection Figure 4.5 R
Page 97 and 98: Figure 4.6 Air to air thermal cycli
Page 99 and 100: Figure 4.7 Thermal Cycling Setup 87
Page 101 and 102: 4.4 Failure Analysis The main purpo
Page 103 and 104: Figure 4.10 Pad cratering failure o
Page 105 and 106: CHAPTER 5 FINITE ELEMENT ANALYSIS I
Page 107 and 108: 5.1.1 Modeling Approaches Due to th
Page 109 and 110: are shown in Figure 5.2. However, t
Page 111 and 112: 5.1.2 Material Properties Many pack
Page 113 and 114: strain rate sensitivity. The evolut
Page 115 and 116: Morris et a1 [96] used a double pow
Page 117 and 118: focus on the time-dependent effects
Page 119 and 120: 5.2 Modeling Procedure In this proj
Page 121 and 122: Figure 5.6 The diagonal symmetry mo
Page 123 and 124: 5.2.3 Meshing Table 5.2 Anand const
Page 125 and 126: direction, but that the surface is
Page 127 and 128: PREP7 tref,398 ! set zero strain te
Page 129: 5.2.7 Thermal Fatigue Life Predicti
Page 133 and 134: References 1. Future Trends in Elec
Page 135 and 136: 23. Electronic Packaging and Interc
Page 137 and 138: 48. Ultra Low Stress and Low Temper
Page 139 and 140: 70. Factors for Successful Wafer-Le
Page 141 and 142: 92. Microstructural Dependendence o
Page 143: 111. Nonlinear Analysis of Full Mat
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Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ...

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