09.06.2013 Views

Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ...

Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ...

Enhanced Polymer Passivation Layer for Wafer Level Chip Scale ...

SHOW MORE
SHOW LESS

You also want an ePaper? Increase the reach of your titles

YUMPU automatically turns print PDFs into web optimized ePapers that Google loves.

Figure 5.2 Global model with a submodel ............................................................................... 97<br />

Figure 5.3 Slice model .............................................................................................................. 98<br />

Figure 5.4 Comparison of Creep Models <strong>for</strong> SnAgCu and SnPb solder .................................. 103<br />

Figure 5.5 Schemiatic representation of the standard (a) and solderbrace-coated<br />

(b)WLCSP assembly (not to scale) ........................................................................ 108<br />

Figure 5.6 The diagonal symmetry model ............................................................................. 109<br />

Figure 5.7 Finished mesh <strong>for</strong> the solderbrace-coated WLCSP package ................................. 112<br />

Figure 5.8 Boundary Conditions applied to a typical slice model ......................................... 113<br />

Figure 5.9 Von Mises stress (MPa) distribution in the solder joint <strong>for</strong> (a) Solderbrace-coated<br />

model and (b) Reference (non-coating) model ..................................................... 116<br />

Figure 5.10 Air-to-air thermal cycling reliability test results ................................................ 116<br />

xii

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!