Microsoft PowerPoint ... - Cadence

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Wire Widening Results Timing improvements on a critical bus (descending order) Net Before After wire widening Difference Delay(ps) Delay(ps) (ps) Net[13] 27.95 20.9 7.05 Net[18] 22.51 15.88 6.63 Net[0] 27.51 21.39 6.12 Net[3] 25.45 19.82 5.63 Net[38] 14.69 10.48 4.21 Net[45] 13.22 9.16 4.06 Net[46] 11.45 7.4 4.05 Net[49] 12.86 9.44 3.42 Net[24] 25.5 22.45 3.05 Net[54] 11.11 8.16 2.95 Net[42] 13.98 11.2 2.78 Net[41] 15.62 13.97 1.65 Net[62] 10.49 9.01 1.48 Net[36] 18.21 17 1.21 Net[33] 25.79 24.59 1.2 Net[37] 16.26 15.29 0.97 Net[48] 14.42 13.65 0.77 Net[44] 12.83 12.28 0.55 Net[14] 22.99 22.85 0.14 9/25/07 Snapshot of a net that is widened 8
Shorts and DRC Reduction Encounter not clean on 65nm Design Rules Complex Rules Congested blocks Grided versus Gridless fixing Option CCO: set_route_on_grid ECOs in Encounter, a consideration 9/25/07 9
Page 1 and 2: 9/25/07 Using Cadence Chip Optmizer
Page 3 and 4: Background SoC Design Semi-Custom
Page 5 and 6: CCO Integration in Flow 9/25/07 Enc
Page 7: Wire Widening Timing Improvements
Page 11 and 12: Examples of Design Rule Coding Min
Page 13 and 14: Yield Optimization Optimization of
Page 15 and 16: Jog Removal Before and After CCO s
Page 17 and 18: Summary CCO Integration with Encou
Page 19 and 20: Acknowledgments Cadence Design Sys

Microsoft PowerPoint ... - Cadence

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