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ECO Experiments

Wire Widening

Shorts and DRC Fixing

Technology File Add-Ons

Yield Optimization

Via Reduction

Jog Removal

Via Doubling

9/25/07

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ECO Experiments Wire Widening Shorts and DRC Fixing Technology File Add-Ons Yield Optimization Via Reduction Jog Removal Via Doubling 9/25/07 6

Wire Widening Timing Improvements Reduce Resistance of wires Taper Wires M5-M7 for maximum benefits on long wires 3 Steps of changes to Widths of wires Output versus input Long wires Noise Flow Robust 9/25/07 wire width increased in 3 steps M7 M6 Tapering from input pin M5 7

Page 1 and 2: 9/25/07 Using Cadence Chip Optmizer
Page 3 and 4: Background SoC Design Semi-Custom
Page 5: CCO Integration in Flow 9/25/07 Enc
Page 9 and 10: Shorts and DRC Reduction Encounter
Page 11 and 12: Examples of Design Rule Coding Min
Page 13 and 14: Yield Optimization Optimization of
Page 15 and 16: Jog Removal Before and After CCO s
Page 17 and 18: Summary CCO Integration with Encou
Page 19 and 20: Acknowledgments Cadence Design Sys

Microsoft PowerPoint ... - Cadence

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