Logic Array Blocks and Adaptive Logic Modules in Cyclone ... - Altera
Logic Array Blocks and Adaptive Logic Modules in Cyclone ... - Altera
Logic Array Blocks and Adaptive Logic Modules in Cyclone ... - Altera
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2013.05.06<br />
CV-52001 Subscribe Feedback<br />
LAB<br />
<strong>Logic</strong> <strong>Array</strong> <strong>Blocks</strong> <strong>and</strong> <strong>Adaptive</strong> <strong>Logic</strong><br />
<strong>Modules</strong> <strong>in</strong> <strong>Cyclone</strong> V Devices<br />
This chapter describes the features of the logic array block (LAB) <strong>in</strong> the <strong>Cyclone</strong> ® V core fabric.<br />
The LAB is composed of basic build<strong>in</strong>g blocks known as adaptive logic modules (ALMs) that you can<br />
configure to implement logic functions, arithmetic functions, <strong>and</strong> register functions.<br />
You can use a quarter of the available LABs <strong>in</strong> the <strong>Cyclone</strong> V devices as a memory LAB (MLAB).<br />
1<br />
The Quartus ® II software <strong>and</strong> other supported third-party synthesis tools, <strong>in</strong> conjunction with parameterized<br />
functions such as the library of parameterized modules (LPM), automatically choose the appropriate mode<br />
for common functions such as counters, adders, subtractors, <strong>and</strong> arithmetic functions.<br />
This chapter conta<strong>in</strong>s the follow<strong>in</strong>g sections:<br />
• LAB<br />
• ALM Operat<strong>in</strong>g Modes<br />
Related Information<br />
<strong>Cyclone</strong> V Device H<strong>and</strong>book: Known Issues<br />
Lists the planned updates to the <strong>Cyclone</strong> V Device H<strong>and</strong>book chapters.<br />
The LABs are configurable logic blocks that consist of a group of logic resources. Each LAB conta<strong>in</strong>s dedicated<br />
logic for driv<strong>in</strong>g control signals to its ALMs.<br />
MLAB is a superset of the LAB <strong>and</strong> <strong>in</strong>cludes all the LAB features.<br />
© 2013 <strong>Altera</strong> Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS <strong>and</strong> STRATIX<br />
words <strong>and</strong> logos are trademarks of <strong>Altera</strong> Corporation <strong>and</strong> registered <strong>in</strong> the U.S. Patent <strong>and</strong> Trademark Office <strong>and</strong> <strong>in</strong> other countries. All other words<br />
<strong>and</strong> logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.<br />
<strong>Altera</strong> warrants performance of its semiconductor products to current specifications <strong>in</strong> accordance with <strong>Altera</strong>'s st<strong>and</strong>ard warranty, but reserves the<br />
right to make changes to any products <strong>and</strong> services at any time without notice. <strong>Altera</strong> assumes no responsibility or liability aris<strong>in</strong>g out of the application<br />
or use of any <strong>in</strong>formation, product, or service described here<strong>in</strong> except as expressly agreed to <strong>in</strong> writ<strong>in</strong>g by <strong>Altera</strong>. <strong>Altera</strong> customers are advised to<br />
obta<strong>in</strong> the latest version of device specifications before rely<strong>in</strong>g on any published <strong>in</strong>formation <strong>and</strong> before plac<strong>in</strong>g orders for products or services.<br />
www.altera.com<br />
101 Innovation Drive, San Jose, CA 95134<br />
ISO<br />
9001:2008<br />
Registered
1-2<br />
Figure 1-1: LAB Structure <strong>and</strong> Interconnects Overview <strong>in</strong> <strong>Cyclone</strong> V Devices<br />
MLAB<br />
MLAB<br />
This figure shows an overview of the <strong>Cyclone</strong> V LAB <strong>and</strong> MLAB structure with the LAB <strong>in</strong>terconnects.<br />
Connects to adjacent<br />
LABs, memory blocks,<br />
digital signal process<strong>in</strong>g<br />
(DSP) blocks, or I/O<br />
element (IOE) outputs.<br />
<strong>Altera</strong> Corporation<br />
R14<br />
R3/R6<br />
Direct-L<strong>in</strong>k<br />
Interconnect from<br />
Adjacent Block<br />
Direct-L<strong>in</strong>k<br />
Interconnect to<br />
Adjacent Block<br />
Local Interconnect<br />
LAB<br />
C2/C4 C12<br />
Row Interconnects of<br />
Variable Speed <strong>and</strong> Length<br />
MLAB<br />
ALMs<br />
Fast Local Interconnect Is Driven<br />
from Either Sides by Column Interconnect<br />
<strong>and</strong> LABs, <strong>and</strong> from Above by Row Interconnect<br />
Each MLAB supports a maximum of 640 bits of simple dual-port SRAM.<br />
Direct-L<strong>in</strong>k<br />
Interconnect from<br />
Adjacent Block<br />
Direct-L<strong>in</strong>k<br />
Interconnect to<br />
Adjacent Block<br />
Column Interconnects of<br />
Variable Speed <strong>and</strong> Length<br />
You can configure each ALM <strong>in</strong> an MLAB as a 32 x 2 memory block, result<strong>in</strong>g <strong>in</strong> a configuration of 32 x 20<br />
simple dual-port SRAM block.<br />
<strong>Logic</strong> <strong>Array</strong> <strong>Blocks</strong> <strong>and</strong> <strong>Adaptive</strong> <strong>Logic</strong> <strong>Modules</strong> <strong>in</strong> <strong>Cyclone</strong> V Devices<br />
CV-52001<br />
2013.05.06<br />
Feedback
CV-52001<br />
2013.05.06<br />
Figure 1-2: LAB <strong>and</strong> MLAB Structure for <strong>Cyclone</strong> V Devices<br />
You can use an MLAB<br />
ALM as a regular LAB<br />
ALM or configure it as a<br />
dual-port SRAM.<br />
You can use an MLAB<br />
ALM as a regular LAB<br />
ALM or configure it as a<br />
dual-port SRAM.<br />
Local <strong>and</strong> Direct L<strong>in</strong>k Interconnects<br />
LUT-Based-32 x 2<br />
Simple Dual-Port SRAM<br />
LUT-Based-32 x 2<br />
Simple Dual-Port SRAM<br />
LUT-Based-32 x 2<br />
Simple Dual-Port SRAM<br />
LUT-Based-32 x 2<br />
Simple Dual-Port SRAM<br />
LUT-Based-32 x 2<br />
Simple Dual-Port SRAM<br />
LAB Control Block<br />
LUT-Based-32 x 2<br />
Simple Dual-Port SRAM<br />
LUT-Based-32 x 2<br />
Simple Dual-Port SRAM<br />
LUT-Based-32 x 2<br />
Simple Dual-Port SRAM<br />
LUT-Based-32 x 2<br />
Simple Dual-Port SRAM<br />
LUT-Based-32 x 2<br />
Simple Dual-Port SRAM<br />
ALM<br />
ALM<br />
ALM<br />
ALM<br />
ALM<br />
LAB Control Block<br />
ALM<br />
ALM<br />
ALM<br />
ALM<br />
ALM<br />
MLAB LAB<br />
Each LAB can drive 30 ALMs through fast-local <strong>and</strong> direct-l<strong>in</strong>k <strong>in</strong>terconnects. Ten ALMs are <strong>in</strong> any given<br />
LAB <strong>and</strong> ten ALMs are <strong>in</strong> each of the adjacent LABs.<br />
The local <strong>in</strong>terconnect can drive ALMs <strong>in</strong> the same LAB us<strong>in</strong>g column <strong>and</strong> row <strong>in</strong>terconnects <strong>and</strong> ALM<br />
outputs <strong>in</strong> the same LAB.<br />
Neighbor<strong>in</strong>g LABs, MLABs, M10K blocks, or digital signal process<strong>in</strong>g (DSP) blocks from the left or right<br />
can also drive the LAB’s local <strong>in</strong>terconnect us<strong>in</strong>g the direct l<strong>in</strong>k connection.<br />
The direct l<strong>in</strong>k connection feature m<strong>in</strong>imizes the use of row <strong>and</strong> column <strong>in</strong>terconnects, provid<strong>in</strong>g higher<br />
performance <strong>and</strong> flexibility.<br />
<strong>Logic</strong> <strong>Array</strong> <strong>Blocks</strong> <strong>and</strong> <strong>Adaptive</strong> <strong>Logic</strong> <strong>Modules</strong> <strong>in</strong> <strong>Cyclone</strong> V Devices<br />
Feedback<br />
Local <strong>and</strong> Direct L<strong>in</strong>k Interconnects<br />
1-3<br />
<strong>Altera</strong> Corporation
1-4<br />
Figure 1-3: LAB Fast Local <strong>and</strong> Direct L<strong>in</strong>k Interconnects for <strong>Cyclone</strong> V Devices<br />
LAB Control Signals<br />
<strong>Altera</strong> Corporation<br />
LAB Control Signals<br />
Direct L<strong>in</strong>k<br />
Interconnect<br />
to Left<br />
Direct L<strong>in</strong>k Interconnect from<br />
Left LAB, Memory Block,<br />
DSP Block, or IOE Output<br />
ALMs ALMs<br />
MLAB<br />
Fast Local<br />
Interconnect<br />
LAB<br />
Direct L<strong>in</strong>k Interconnect from<br />
Right LAB, Memory Block,<br />
DSP Block, or IOE Output<br />
Direct L<strong>in</strong>k<br />
Interconnect<br />
to Right<br />
Each LAB conta<strong>in</strong>s dedicated logic for driv<strong>in</strong>g the control signals to its ALMs, <strong>and</strong> has two unique clock<br />
sources <strong>and</strong> three clock enable signals.<br />
The LAB control block generates up to three clocks us<strong>in</strong>g the two clock sources <strong>and</strong> three clock enable<br />
signals. Each clock <strong>and</strong> the clock enable signals are l<strong>in</strong>ked.<br />
De-assert<strong>in</strong>g the clock enable signal turns off the correspond<strong>in</strong>g LAB-wide clock.<br />
<strong>Logic</strong> <strong>Array</strong> <strong>Blocks</strong> <strong>and</strong> <strong>Adaptive</strong> <strong>Logic</strong> <strong>Modules</strong> <strong>in</strong> <strong>Cyclone</strong> V Devices<br />
CV-52001<br />
2013.05.06<br />
Feedback
CV-52001<br />
2013.05.06<br />
Figure 1-4: LAB-Wide Control Signals for <strong>Cyclone</strong> V Devices<br />
This figure shows the clock sources <strong>and</strong> clock enable signals <strong>in</strong> a LAB.<br />
Dedicated Row<br />
LAB Clocks<br />
Local Interconnect<br />
Local Interconnect<br />
Local Interconnect<br />
Local Interconnect<br />
ALM Resources<br />
6<br />
6<br />
6<br />
There are two unique<br />
clock signals per LAB.<br />
labclk0 labclk1 labclk2 syncload<br />
labclr1<br />
labclkena0<br />
or asyncload<br />
or labpreset<br />
labclkena1 labclkena2 labclr0 synclr<br />
One ALM conta<strong>in</strong>s four programmable registers. Each register has the follow<strong>in</strong>g ports:<br />
• Data<br />
• Clock<br />
• Synchronous <strong>and</strong> asynchronous clear<br />
• Synchronous load<br />
Global signals, general-purpose I/O (GPIO) p<strong>in</strong>s, or any <strong>in</strong>ternal logic can drive the clock <strong>and</strong> clear control<br />
signals of an ALM register.<br />
GPIO p<strong>in</strong>s or <strong>in</strong>ternal logic drives the clock enable signal.<br />
For comb<strong>in</strong>ational functions, the registers are bypassed <strong>and</strong> the output of the look-up table (LUT) drives<br />
directly to the outputs of an ALM.<br />
Note:<br />
The Quartus II software automatically configures the ALMs for optimized performance.<br />
<strong>Logic</strong> <strong>Array</strong> <strong>Blocks</strong> <strong>and</strong> <strong>Adaptive</strong> <strong>Logic</strong> <strong>Modules</strong> <strong>in</strong> <strong>Cyclone</strong> V Devices<br />
Feedback<br />
ALM Resources<br />
1-5<br />
<strong>Altera</strong> Corporation
1-6<br />
ALM Output<br />
Figure 1-5: ALM High-Level Block Diagram for <strong>Cyclone</strong> V Devices<br />
ALM Output<br />
<strong>Altera</strong> Corporation<br />
dataf0<br />
datae0<br />
dataa<br />
datab<br />
datac<br />
datad<br />
datae1<br />
dataf1<br />
shared_arith_<strong>in</strong><br />
6-Input<br />
LUT<br />
6-Input<br />
LUT<br />
shared_arith_out<br />
carry_<strong>in</strong><br />
adder0<br />
adder1<br />
carry_out<br />
Comb<strong>in</strong>ational/<br />
Memory ALUT0<br />
Comb<strong>in</strong>ational/<br />
Memory ALUT1<br />
labclk<br />
D Q<br />
reg0<br />
D Q<br />
reg1<br />
D Q<br />
reg2<br />
D Q<br />
reg3<br />
To General or<br />
Local Rout<strong>in</strong>g<br />
To General or<br />
Local Rout<strong>in</strong>g<br />
To General or<br />
Local Rout<strong>in</strong>g<br />
To General or<br />
Local Rout<strong>in</strong>g<br />
To General or<br />
Local Rout<strong>in</strong>g<br />
To General or<br />
Local Rout<strong>in</strong>g<br />
To General or<br />
Local Rout<strong>in</strong>g<br />
To General or<br />
Local Rout<strong>in</strong>g<br />
The general rout<strong>in</strong>g outputs <strong>in</strong> each ALM drive the local, row, <strong>and</strong> column rout<strong>in</strong>g resources. Two ALM<br />
outputs can drive column, row, or direct l<strong>in</strong>k rout<strong>in</strong>g connections, <strong>and</strong> one of these ALM outputs can also<br />
drive local <strong>in</strong>terconnect resources.<br />
The LUT, adder, or register output can drive the ALM outputs. The LUT or adder can drive one output<br />
while the register drives another output.<br />
Register pack<strong>in</strong>g improves device utilization by allow<strong>in</strong>g unrelated register <strong>and</strong> comb<strong>in</strong>ational logic to be<br />
packed <strong>in</strong>to a s<strong>in</strong>gle ALM. Another mechanism to improve fitt<strong>in</strong>g is to allow the register output to feed back<br />
<strong>in</strong>to the look-up table (LUT) of the same ALM so that the register is packed with its own fan-out LUT. The<br />
ALM can also drive out registered <strong>and</strong> unregistered versions of the LUT or adder output.<br />
<strong>Logic</strong> <strong>Array</strong> <strong>Blocks</strong> <strong>and</strong> <strong>Adaptive</strong> <strong>Logic</strong> <strong>Modules</strong> <strong>in</strong> <strong>Cyclone</strong> V Devices<br />
CV-52001<br />
2013.05.06<br />
Feedback
CV-52001<br />
2013.05.06<br />
Figure 1-6: ALM Connection Details for <strong>Cyclone</strong> V Devices<br />
dataf0<br />
datae0<br />
dataa<br />
datab<br />
datac0<br />
datac1<br />
datae1<br />
dataf1<br />
shared_arith_<strong>in</strong><br />
4-Input<br />
LUT<br />
3-Input<br />
LUT<br />
3-Input<br />
LUT<br />
4-Input<br />
LUT<br />
3-Input<br />
LUT<br />
3-Input<br />
LUT<br />
shared_arith_out<br />
ALM Operat<strong>in</strong>g Modes<br />
carry_<strong>in</strong><br />
+<br />
+<br />
carry_out<br />
GND<br />
VCC<br />
syncload<br />
aclr[1:0]<br />
clk[2:0] sclr<br />
The <strong>Cyclone</strong> V ALM operates <strong>in</strong> any of the follow<strong>in</strong>g modes:<br />
• Normal mode<br />
• Extended LUT mode<br />
• Arithmetic mode<br />
• Shared arithmetic mode<br />
<strong>Logic</strong> <strong>Array</strong> <strong>Blocks</strong> <strong>and</strong> <strong>Adaptive</strong> <strong>Logic</strong> <strong>Modules</strong> <strong>in</strong> <strong>Cyclone</strong> V Devices<br />
Feedback<br />
CLR<br />
D Q<br />
CLR<br />
D Q<br />
CLR<br />
D Q<br />
CLR<br />
D Q<br />
ALM Operat<strong>in</strong>g Modes<br />
Row, Column<br />
Direct L<strong>in</strong>k Rout<strong>in</strong>g<br />
Row, Column<br />
Direct L<strong>in</strong>k Rout<strong>in</strong>g<br />
Local<br />
Interconnect<br />
Row, Column<br />
Direct L<strong>in</strong>k Rout<strong>in</strong>g<br />
Row, Column<br />
Direct L<strong>in</strong>k Rout<strong>in</strong>g<br />
Local<br />
Interconnect<br />
1-7<br />
<strong>Altera</strong> Corporation
1-8<br />
Normal Mode<br />
Normal mode allows two functions to be implemented <strong>in</strong> one <strong>Cyclone</strong> V ALM, or a s<strong>in</strong>gle function of up<br />
to six <strong>in</strong>puts.<br />
Up to eight data <strong>in</strong>puts from the LAB local <strong>in</strong>terconnect are <strong>in</strong>puts to the comb<strong>in</strong>ational logic.<br />
The ALM can support certa<strong>in</strong> comb<strong>in</strong>ations of completely <strong>in</strong>dependent functions <strong>and</strong> various comb<strong>in</strong>ations<br />
of functions that have common <strong>in</strong>puts.<br />
Extended LUT Mode<br />
In this mode, if the 7-<strong>in</strong>put function is unregistered, the unused eighth <strong>in</strong>put is available for register pack<strong>in</strong>g.<br />
Functions that fit <strong>in</strong>to the template, as shown <strong>in</strong> the follow<strong>in</strong>g figure, often appear <strong>in</strong> designs as “if-else”<br />
statements <strong>in</strong> Verilog HDL or VHDL code.<br />
Figure 1-7: Template for Supported 7-Input Functions <strong>in</strong> Extended LUT Mode for <strong>Cyclone</strong> V Devices<br />
Arithmetic Mode<br />
<strong>Altera</strong> Corporation<br />
Normal Mode<br />
datae0<br />
datac<br />
dataa<br />
datab<br />
datad<br />
dataf0<br />
datae1<br />
dataf1<br />
5-Input<br />
LUT<br />
5-Input<br />
LUT<br />
This <strong>in</strong>put is available<br />
for register pack<strong>in</strong>g.<br />
combout0<br />
D Q<br />
reg0<br />
To General or<br />
Local Rout<strong>in</strong>g<br />
To General or<br />
Local Rout<strong>in</strong>g<br />
The ALM <strong>in</strong> arithmetic mode uses two sets of two 4-<strong>in</strong>put LUTs along with two dedicated full adders.<br />
The dedicated adders allow the LUTs to perform pre-adder logic; therefore, each adder can add the output<br />
of two 4-<strong>in</strong>put functions.<br />
The ALM supports simultaneous use of the adder’s carry output along with comb<strong>in</strong>ational logic outputs.<br />
The adder output is ignored <strong>in</strong> this operation.<br />
Us<strong>in</strong>g the adder with the comb<strong>in</strong>ational logic output provides resource sav<strong>in</strong>gs of up to 50% for functions<br />
that can use this mode.<br />
<strong>Logic</strong> <strong>Array</strong> <strong>Blocks</strong> <strong>and</strong> <strong>Adaptive</strong> <strong>Logic</strong> <strong>Modules</strong> <strong>in</strong> <strong>Cyclone</strong> V Devices<br />
CV-52001<br />
2013.05.06<br />
Feedback
CV-52001<br />
2013.05.06<br />
Figure 1-8: ALM <strong>in</strong> Arithmetic Mode for <strong>Cyclone</strong> V Devices<br />
Carry Cha<strong>in</strong><br />
datae0<br />
dataf0<br />
datac<br />
datab<br />
dataa<br />
datad<br />
datae1<br />
dataf1<br />
4-Input<br />
LUT<br />
4-Input<br />
LUT<br />
4-Input<br />
LUT<br />
4-Input<br />
LUT<br />
carry_<strong>in</strong><br />
carry_out<br />
adder0<br />
adder1<br />
reg0<br />
reg1<br />
reg2<br />
reg3<br />
To General or<br />
Local Rout<strong>in</strong>g<br />
To General or<br />
Local Rout<strong>in</strong>g<br />
The carry cha<strong>in</strong> provides a fast carry function between the dedicated adders <strong>in</strong> arithmetic or shared arithmetic<br />
mode.<br />
The two-bit carry select feature <strong>in</strong> <strong>Cyclone</strong> V devices halves the propagation delay of carry cha<strong>in</strong>s with<strong>in</strong><br />
the ALM. Carry cha<strong>in</strong>s can beg<strong>in</strong> <strong>in</strong> either the first ALM or the fifth ALM <strong>in</strong> a LAB. The f<strong>in</strong>al carry-out<br />
signal is routed to an ALM, where it is fed to local, row, or column <strong>in</strong>terconnects.<br />
To avoid rout<strong>in</strong>g congestion <strong>in</strong> one small area of the device when a high fan-<strong>in</strong> arithmetic function is<br />
implemented, the LAB can support carry cha<strong>in</strong>s that only use either the top half or bottom half of the LAB<br />
before connect<strong>in</strong>g to the next LAB. This leaves the other half of the ALMs <strong>in</strong> the LAB available for<br />
implement<strong>in</strong>g narrower fan-<strong>in</strong> functions <strong>in</strong> normal mode. Carry cha<strong>in</strong>s that use the top five ALMs <strong>in</strong> the<br />
first LAB carry <strong>in</strong>to the top half of the ALMs <strong>in</strong> the next LAB <strong>in</strong> the column. Carry cha<strong>in</strong>s that use the bottom<br />
five ALMs <strong>in</strong> the first LAB carry <strong>in</strong>to the bottom half of the ALMs <strong>in</strong> the next LAB with<strong>in</strong> the column. You<br />
can bypass the top-half of the LAB columns <strong>and</strong> bottom-half of the MLAB columns.<br />
The Quartus II Compiler creates carry cha<strong>in</strong>s longer than 20 ALMs (10 ALMs <strong>in</strong> arithmetic or shared<br />
arithmetic mode) by l<strong>in</strong>k<strong>in</strong>g LABs together automatically. For enhanced fitt<strong>in</strong>g, a long carry cha<strong>in</strong> runs<br />
vertically, allow<strong>in</strong>g fast horizontal connections to the TriMatrix memory <strong>and</strong> DSP blocks. A carry cha<strong>in</strong> can<br />
cont<strong>in</strong>ue as far as a full column.<br />
Shared Arithmetic Mode<br />
The ALM <strong>in</strong> shared arithmetic mode can implement a 3-<strong>in</strong>put add <strong>in</strong> the ALM.<br />
This mode configures the ALM with four 4-<strong>in</strong>put LUTs. Each LUT either computes the sum of three <strong>in</strong>puts<br />
or the carry of three <strong>in</strong>puts. The output of the carry computation is fed to the next adder us<strong>in</strong>g a dedicated<br />
connection called the shared arithmetic cha<strong>in</strong>.<br />
<strong>Logic</strong> <strong>Array</strong> <strong>Blocks</strong> <strong>and</strong> <strong>Adaptive</strong> <strong>Logic</strong> <strong>Modules</strong> <strong>in</strong> <strong>Cyclone</strong> V Devices<br />
Feedback<br />
Shared Arithmetic Mode<br />
1-9<br />
<strong>Altera</strong> Corporation
1-10<br />
Figure 1-9: ALM <strong>in</strong> Shared Arithmetic Mode for <strong>Cyclone</strong> V Devices<br />
Shared Arithmetic Cha<strong>in</strong><br />
datae0<br />
datac<br />
datab<br />
dataa<br />
datad<br />
datae1<br />
4-Input<br />
LUT<br />
4-Input<br />
LUT<br />
4-Input<br />
LUT<br />
4-Input<br />
LUT<br />
shared_arith_<strong>in</strong><br />
shared_arith_out<br />
carry_<strong>in</strong><br />
carry_out<br />
labclk<br />
reg0<br />
reg1<br />
reg2<br />
reg3<br />
To General or<br />
Local Rout<strong>in</strong>g<br />
The shared arithmetic cha<strong>in</strong> available <strong>in</strong> enhanced arithmetic mode allows the ALM to implement a 3-<strong>in</strong>put<br />
adder. This significantly reduces the resources necessary to implement large adder trees or correlator<br />
functions.<br />
The shared arithmetic cha<strong>in</strong> can beg<strong>in</strong> <strong>in</strong> either the first or sixth ALM <strong>in</strong> a LAB.<br />
Similar to carry cha<strong>in</strong>s, the top <strong>and</strong> bottom half of the shared arithmetic cha<strong>in</strong>s <strong>in</strong> alternate LAB columns<br />
can be bypassed. This capability allows the shared arithmetic cha<strong>in</strong> to cascade through half of the ALMs <strong>in</strong><br />
an LAB while leav<strong>in</strong>g the other half available for narrower fan-<strong>in</strong> functionality. In every LAB, the column<br />
is top-half bypassable; while <strong>in</strong> MLAB, columns are bottom-half bypassable.<br />
The Quartus II Compiler creates shared arithmetic cha<strong>in</strong>s longer than 20 ALMs (10 ALMs <strong>in</strong> arithmetic or<br />
shared arithmetic mode) by l<strong>in</strong>k<strong>in</strong>g LABs together automatically. To enhance fitt<strong>in</strong>g, a long shared arithmetic<br />
cha<strong>in</strong> runs vertically, allow<strong>in</strong>g fast horizontal connections to the TriMatrix memory <strong>and</strong> DSP blocks. A<br />
shared arithmetic cha<strong>in</strong> can cont<strong>in</strong>ue as far as a full column.<br />
Document Revision History<br />
Date<br />
May 2013<br />
<strong>Altera</strong> Corporation<br />
Document Revision History<br />
Version<br />
2013.05.06<br />
Changes<br />
• Added l<strong>in</strong>k to the known document issues <strong>in</strong> the Knowledge Base.<br />
• Removed register cha<strong>in</strong> outputs <strong>in</strong>formation <strong>in</strong> ALM output section.<br />
• Removed reg_cha<strong>in</strong>_<strong>in</strong> <strong>and</strong> reg_cha<strong>in</strong>_out ports <strong>in</strong> ALM<br />
high-level block diagram <strong>and</strong> ALM connection details diagram.<br />
<strong>Logic</strong> <strong>Array</strong> <strong>Blocks</strong> <strong>and</strong> <strong>Adaptive</strong> <strong>Logic</strong> <strong>Modules</strong> <strong>in</strong> <strong>Cyclone</strong> V Devices<br />
CV-52001<br />
2013.05.06<br />
Feedback
CV-52001<br />
2013.05.06<br />
Date<br />
December 2012<br />
June 2012<br />
November 2011<br />
October 2011<br />
Version<br />
2012.12.28<br />
2.0<br />
1.1<br />
1.0<br />
Changes<br />
Reorganized content <strong>and</strong> updated template.<br />
Updated for the Quartus II software v12.0 release:<br />
• Restructured chapter.<br />
• Updated Figure 1–6.<br />
M<strong>in</strong>or text edits.<br />
Initial release.<br />
<strong>Logic</strong> <strong>Array</strong> <strong>Blocks</strong> <strong>and</strong> <strong>Adaptive</strong> <strong>Logic</strong> <strong>Modules</strong> <strong>in</strong> <strong>Cyclone</strong> V Devices<br />
Feedback<br />
Document Revision History<br />
1-11<br />
<strong>Altera</strong> Corporation