EBDW Overcoming Challenges in Extendiing Optical ... - Sematech
EBDW Overcoming Challenges in Extendiing Optical ... - Sematech
EBDW Overcoming Challenges in Extendiing Optical ... - Sematech
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<strong>EBDW</strong> <strong>EBDW</strong> <strong>Overcom<strong>in</strong>g</strong> <strong>Overcom<strong>in</strong>g</strong> <strong>Challenges</strong><br />
<strong>Challenges</strong><br />
<strong>in</strong> <strong>in</strong> Extend<strong>in</strong>g<br />
Extend<strong>in</strong>g<br />
<strong>Optical</strong> <strong>Optical</strong> 193 193 nm nm Lithography<br />
Lithography<br />
Dave Liu, Ted Prescop<br />
Oct 22, 2010 – Kobe, Japan
1. Industry Trend<br />
2010 Int’l Symposium on Litho Extensions<br />
Outl<strong>in</strong>e<br />
Logic layout for DFM: One Direction, Fixed Pitch<br />
<strong>EBDW</strong> as Complementary Lithography<br />
2. Top <strong>EBDW</strong> Challenge: Throughput<br />
3. Top Lithography Challenge: Overlay Accuracy<br />
4. <strong>EBDW</strong> Can Overcome <strong>Challenges</strong> and Extend <strong>Optical</strong><br />
2
Industry Trend # 1: 1D Layout, 1 Pitch<br />
• Intel, TSMC and others adopt<strong>in</strong>g highly regular Logic layouts<br />
“… allowed logic poly layout to be one pitch and one direction …”<br />
– Intel Technology Journal (Vol. 12, Issue 2, 2008)<br />
“… draws a lithography-optimized lithography optimized pattern with uniform density<br />
through unidirectional poly on a fixed pitch…” pitch…”<br />
– TSMC press release (June 2010)<br />
2010 Int’l Symposium on Litho Extensions<br />
Courtesy Tela Innovations<br />
3
Industry Trend # 2: Complementary Litho<br />
• Borodovsky (Intel) shows 193 nm immersion (193i) requires<br />
5 masks for 11 nm Node (40nm pitch) HVM <strong>in</strong> 2015:<br />
1 to create the l<strong>in</strong>es and 4 to break cont<strong>in</strong>uity (“cut” l<strong>in</strong>es)<br />
Mask Count:<br />
1<br />
2<br />
3<br />
4<br />
5<br />
– Borodovsky, Y. (Maskless Litho and Multibeam Mask Workshop 2010) 2010<br />
2010 Int’l Symposium on Litho Extensions<br />
4
Yan Borodovsky’s Borodovsky s Realistic Solution<br />
• Borodovsky (Intel) shows 193 nm immersion (193i) requires<br />
5 masks for 11 nm Node (40nm pitch) HVM <strong>in</strong> 2015:<br />
1 to create the l<strong>in</strong>es and 4 to break cont<strong>in</strong>uity (“cut” l<strong>in</strong>es)<br />
• <strong>EBDW</strong> can cut l<strong>in</strong>es and elim<strong>in</strong>ate all 4 “cut cut” masks<br />
Mask Count:<br />
1<br />
2010 Int’l Symposium on Litho Extensions<br />
This is Complementary Lithography<br />
5
Top challenges for “Maskless Maskless Lithography” Lithography <strong>in</strong> 2009 ITRS*:<br />
1. 1. WWafer<br />
Wafer Throughput<br />
Beam Current<br />
Pattern<strong>in</strong>g Speed<br />
* http://www.itrs.net/L<strong>in</strong>ks/2009ITRS/2009Chapters_2009Tables/2009_Litho.pdf<br />
2010 Int’l Symposium on Litho Extensions<br />
Top <strong>EBDW</strong> <strong>Challenges</strong><br />
2. Cost Control and Return on Investment (ROI)<br />
3. Die-to Die to-database database <strong>in</strong>spection of wafer patterns<br />
4. Pattern placement - <strong>in</strong>clud<strong>in</strong>g stitch<strong>in</strong>g<br />
5. Controll<strong>in</strong>g variability between beams <strong>in</strong> multibeam<br />
systems<br />
6
Throughput Challenge # 1: Beam Current<br />
• E-beam beam current identified as a throughput challenge<br />
What e-beam e beam current is required to achieve 5 wph?<br />
Beam current required for 5 wph<br />
(Resist Dose) * (5% Writ<strong>in</strong>g Area) / (Write Time) = Beam Current<br />
20 µC/cm 2 * 5% * π * (15 cm) 2 / 720 seconds = 1.0 µA<br />
• How does Multibeam deliver 1.0 µA? A?<br />
2010 Int’l Symposium on Litho Extensions<br />
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High-Current High Current E-Beam E Beam Column<br />
• Each column has TFE (1) e-source source<br />
TFE brightness: 200 µA/ A/sr sr<br />
25 nA at wafer (5 keV beam, 22 nm FWHM (2) )<br />
25 nA at wafer (50 keV beam, 10 nm FWHM)<br />
• All-electrostatic All electrostatic (no magnetic field)<br />
Faster deflection<br />
Smaller diameter (22 mm outer diameter)<br />
88 columns <strong>in</strong> a 30x30 mm array<br />
120 columns <strong>in</strong> a 25x25 mm array<br />
(1) TFE = Thermal Field Emitter<br />
(2) FWHM = Full Width Half Max beam spot size<br />
2010 Int’l Symposium on Litho Extensions<br />
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• Identical columns are arrayed <strong>in</strong> a row<br />
E-Beam Beam Column<br />
2010 Int’l Symposium on Litho Extensions<br />
Column Array<br />
9
2010 Int’l Symposium on Litho Extensions<br />
Column Array<br />
• Identical columns are arrayed <strong>in</strong> a row<br />
• Row becomes 2-D 2 D array<br />
• Throughput rema<strong>in</strong>s the same for all wafer sizes<br />
10
Vector-Scan Vector Scan Pattern<strong>in</strong>g Strategy<br />
• Column array is stationary<br />
• Stage speed is very slow<br />
• Stage travel is very small<br />
L<strong>in</strong>ear Stage<br />
Sub-fields<br />
Frame size ~50 µm<br />
2010 Int’l Symposium on Litho Extensions<br />
11<br />
Beam from each<br />
column writes<br />
~30mm x ~30mm<br />
Vector scanned<br />
shaped beams
Beam Current is Achievable<br />
• To achieve 5 wph …<br />
We only pattern critical layers with low pattern density (~5%)<br />
We use multiple columns <strong>in</strong> parallel to pattern each wafer<br />
Total beam current required for 5 wph = 1.0 µA<br />
Beam current required per column = 10 nA<br />
• For Complementary Lithography, Multibeam’s<br />
Multibeam s<br />
column has more than enough current<br />
2010 Int’l Symposium on Litho Extensions<br />
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Throughput Challenge # 2: Pattern<strong>in</strong>g Speed<br />
• Pattern<strong>in</strong>g speed identified as a throughput challenge<br />
High pattern<strong>in</strong>g speed required at high resolution<br />
What pattern<strong>in</strong>g speed is required to achieve 5 wph?<br />
(Assume: 300 mm wafer, 5% pattern density, 100 columns, 20nm features) features<br />
• 5 wph requires: (88*10 9 ) / (720 s) = 120 MHz<br />
… or 8 ns per shot<br />
2010 Int’l Symposium on Litho Extensions<br />
Number of shapes written per column<br />
= π * (15 cm) 2 * 5% / 100 / (20nm) 2<br />
= 88 Giga-shots / column<br />
… How do we achieve this high pattern<strong>in</strong>g speed?<br />
13
Pattern<strong>in</strong>g Speed is Achievable<br />
• We optimize vector-scan vector scan strategy<br />
Need only one beam shape for l<strong>in</strong>e-cutt<strong>in</strong>g l<strong>in</strong>e cutt<strong>in</strong>g<br />
M<strong>in</strong>imize electronics overhead for blank<strong>in</strong>g and settl<strong>in</strong>g<br />
~80% of pattern is “neighbor<strong>in</strong>g<br />
cuts” with almost no overhead<br />
~20% of pattern is “random<br />
cuts” with higher overhead<br />
2010 Int’l Symposium on Litho Extensions<br />
14<br />
Portion of a logic block<br />
Courtesy of Tela Innovations<br />
Optimiz<strong>in</strong>g scan path further <strong>in</strong>creases throughput
Wafer Throughput - Achievable<br />
Pattern critical layers only<br />
Vector-scan shaped beam<br />
Array multiple columns<br />
Cluster multiple modules<br />
S<strong>in</strong>gle Module<br />
(Multibeam Inside) Cluster Configuration<br />
2010 Int’l Symposium on Litho Extensions<br />
Low-density patterns: ~5%<br />
Optimize scan path, reduce data storage and<br />
reduce data transfer rate to each column<br />
Scalable architecture to boost throughput<br />
Cluster<strong>in</strong>g to meet HVM requirements<br />
top view<br />
15<br />
Cluster Configuration
Other Lithography <strong>Challenges</strong><br />
Common Challenge for All Lithography:<br />
1. Overlay Accuracy<br />
2. Critical Dimension Uniformity (CDU)<br />
3. L<strong>in</strong>e Edge Roughness (LER)<br />
2010 Int’l Symposium on Litho Extensions<br />
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Overlay Accuracy Challenge<br />
• Problem: Beam Drift<br />
High energy beams: less drift, but thermal control is challeng<strong>in</strong>g<br />
Low energy beams: sensitive to drift due to charg<strong>in</strong>g<br />
For example, if 1 mV static charge causes 1 nm beam drift at 50 keV,<br />
the same charge will cause 10 nm drift at 5 keV<br />
• Solutions to Overcome Beam Drift<br />
Conductive layer <strong>in</strong> resist: prevent wafer charg<strong>in</strong>g<br />
Off-axis Off axis optical alignment: register column-array column array position<br />
BSE (1) detector (SEM mode): register position of every beam<br />
(1) BSE = back ackscattered cattered electron lectron<br />
2010 Int’l Symposium on Litho Extensions<br />
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2010 Int’l Symposium on Litho Extensions<br />
Thermal Budget<br />
• Thermal budget identified as overlay challenge<br />
Energy deposited <strong>in</strong>to wafer =<br />
(Voltage) * (Resist Dose) * (5% Writ<strong>in</strong>g Area)<br />
5 keV * 20 µC/cm 2 * 5% * π * (15 cm) 2 = 3.5 Joules<br />
Expansion of wafer =<br />
(Energy) / (Wafer Heat Capacity) * (300mm Wafer Expansion)<br />
3.5 Joules / (87 Joules/ºC) * (690 nm/ºC/300mm) = 28 nm<br />
Exposure Energy<br />
5 keV, 20 µC/cm 2<br />
20 keV, 80 µC/cm 2<br />
Joules/wafer<br />
3.5<br />
56<br />
Net expansion (nm)<br />
over 300mm<br />
18<br />
28<br />
450<br />
Net expansion (nm),<br />
99% heat transfer<br />
0.28<br />
4.5
2010 Int’l Symposium on Litho Extensions<br />
Alignment Mark Contrast<br />
Image Contrast<br />
1.2<br />
1.0<br />
0.8<br />
0.6<br />
0.4<br />
0.2<br />
260nm Au/Si<br />
350nm SiO 2 on 260nm Au/Si<br />
0<br />
0 5 10 15 20 25 30 35<br />
Beam Energy (keV)<br />
– Greeneich, Greeneich,<br />
J. (Contrast for gold marks on silicon under SiO 2 )<br />
19<br />
Image contrast depends on<br />
electron penetrat<strong>in</strong>g depth<br />
(called “Bethe Range”)
Beam Energy Trade-offs Trade offs for Overlay<br />
Thermal control<br />
Beam drift<br />
Alignment mark signal<br />
2010 Int’l Symposium on Litho Extensions<br />
High Energy<br />
20<br />
≥ 10 keV<br />
☺<br />
☺<br />
Best Overlay Results at ~10 keV<br />
Low Energy<br />
≤ 5 keV<br />
☺
Overlay Accuracy is Achievable<br />
• One beam per column: column:<br />
for maximum<br />
control of each beam<br />
• BSE detector (SEM-mode)<br />
(SEM mode): to scan<br />
alignment marks for direct registration<br />
• Optimized beam energy: for best Overlay<br />
2010 Int’l Symposium on Litho Extensions<br />
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Multibeam’s Multi-column Architecture<br />
Overcomes Key <strong>Challenges</strong> <strong>in</strong> <strong>EBDW</strong><br />
• Throughput<br />
Pattern low-density low density critical layers<br />
Vector-scanned Vector scanned shaped beams<br />
Scalable array of multiple columns<br />
Cluster multiple column-array column array modules for HVM<br />
• Overlay<br />
BSE detector for each beam<br />
Adjustable beam energy<br />
Complementary <strong>EBDW</strong> will extend 193nm <strong>Optical</strong> Litho<br />
2010 Int’l Symposium on Litho Extensions<br />
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