Control Data Flow Graph (CDFG) • Combines DFG and CFG • Often ...

Control Data Flow Graph (CDFG)
• Combines DFG and CFG
– Nodes for all control flow elements
– DFG for each basic block
– Dummy nodes at beginning and end of each basic block
– Dummy nodes ensure synchronization with predecessors
and successors
• Often used in HW synthesis systems
©Christian Hochberger Slide 34 of47

CDFG – Example
i = 0;
x = 0;
while (i

CDFG – Branch Handling
• Branches can be handled differently
– Like in programming languages: predication
– All branches run concurrently: speculation
• Only strict requirements:
– Only one branch may have lasting effects
• Lasting effects:
– Variable assignments
– Memory alterations
– Method calls (probably not important in HW synthesis)
©Christian Hochberger Slide 36 of47

CDFG – Predication
• Resembles instruction sequence of traditional
processors
– Condition is evaluated
– Conditional blocks
• are only evaluated if condition is met
• only one is evaluated
• Works perfect for all program constructs
• Always wastes time (almost)
©Christian Hochberger Slide 37 of47

CDFG – Predication (2)
• Implementation
– Usually by the controlling state machine
• State machine waits for condition result
• State machine enters corresponding state sequence
• Individual schedules for each branch
(and condition computation)
• Resources required:
– Maximum per resource type of (V cond ,V if , V else )
• Execution time:
– Maximum of if and else branch + condition computation
©Christian Hochberger Slide 38 of47

CDFG – Predication Example
if ((i­4)/3 < 7) {
s += x;
} else {
s += x * (i ­ 3);
}
x = x * 1.3;
i = i + 1;
Resources:
­ / < * +
©Christian Hochberger Slide 39 of47
0
1
2
3
4
5
6
­
*
+
­
/
<
+
Alternative state
sequences

CDFG – Speculation
• Concurrent execution of
– Condition computation
– Alternative branches
• When all three are ready
– Select variable values according to condition
– Expressed in PHI functions in SSA
– Translates to multiplexers in HW
• Does not work for all programming constructs
©Christian Hochberger Slide 40 of47

CDFG – Speculation (2)
• Implementation
– Build circuit for condition computation + if-branch + else
branch
– Analyze variable usage (easy with SSA)
– Introduce multiplexers for identical variables in alternative
branches
• Resources required:
– Sum of all resources (V cond ,V if , V else )
• Execution time:
– Maximum of if-branch, else branch and condition
computation
©Christian Hochberger Slide 41 of47

CDFG – Speculation Example
if ((i­4)/3 < 7) {
s += x;
} else {
s += x * (i ­ 3);
}
x = x * 1.3;
i = i + 1;
­
Resources:
­ / < * +
©Christian Hochberger Slide 42 of47
0
1
2
3
4
­
*
+
­
/
<
+
Additional time step
+ mux may be necessary

Control Memory Data Flow Graph (CMDFG)
• Arrays and records cause problems in SSA
• Reason: Both relate to memory areas
• General memory access problems:
– May not occur in speculation
– Often limited number of concurrent accesses
• Solution:
– Treat memory access as first class node type in graph
– CMDFG has three node types:
• Control flow
• Memory access
• Data flow
©Christian Hochberger Slide 43 of47

CMDFG – Example
i = 0;
while (i

Problem and Resource Graph
• Problem graph:
– Generalization of data flow graphs
– Nodes for all tasks (node set V)
– Edges for all data dependencies (edge set E)
• Resource graph:
– Node set V R = V ∪ V T
– Set V T contains node for all resource types
– Edges (v i ,r k ) with v i ∈ V and r k ∈ V T :
Task v i can be accomplished by r k
– Edge weights describe the time required for the operation
©Christian Hochberger Slide 45 of47

Problem and Resource Graph - Example
while (i

Problem and Resource Graph – Pros/Cons
• Pro:
– Alternative implementations can be described
– Only immediate dependencies
– Simplifies graph
• Cons:
– Control flow not captured
– Complicates RTL generation
©Christian Hochberger Slide 47 of47