Control Data Flow Graph (CDFG) • Combines DFG and CFG • Often ...
Control Data Flow Graph (CDFG) • Combines DFG and CFG • Often ...
Control Data Flow Graph (CDFG) • Combines DFG and CFG • Often ...
Create successful ePaper yourself
Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.
<strong>Control</strong> <strong>Data</strong> <strong>Flow</strong> <strong>Graph</strong> (<strong>C<strong>DFG</strong></strong>)<br />
<strong>•</strong> <strong>Combines</strong> <strong>DFG</strong> <strong>and</strong> <strong>CFG</strong><br />
– Nodes for all control flow elements<br />
– <strong>DFG</strong> for each basic block<br />
– Dummy nodes at beginning <strong>and</strong> end of each basic block<br />
– Dummy nodes ensure synchronization with predecessors<br />
<strong>and</strong> successors<br />
<strong>•</strong> <strong>Often</strong> used in HW synthesis systems<br />
©Christian Hochberger Slide 34 of47
<strong>C<strong>DFG</strong></strong> – Example<br />
i = 0;<br />
x = 0;<br />
while (i
<strong>C<strong>DFG</strong></strong> – Branch H<strong>and</strong>ling<br />
<strong>•</strong> Branches can be h<strong>and</strong>led differently<br />
– Like in programming languages: predication<br />
– All branches run concurrently: speculation<br />
<strong>•</strong> Only strict requirements:<br />
– Only one branch may have lasting effects<br />
<strong>•</strong> Lasting effects:<br />
– Variable assignments<br />
– Memory alterations<br />
– Method calls (probably not important in HW synthesis)<br />
©Christian Hochberger Slide 36 of47
<strong>C<strong>DFG</strong></strong> – Predication<br />
<strong>•</strong> Resembles instruction sequence of traditional<br />
processors<br />
– Condition is evaluated<br />
– Conditional blocks<br />
<strong>•</strong> are only evaluated if condition is met<br />
<strong>•</strong> only one is evaluated<br />
<strong>•</strong> Works perfect for all program constructs<br />
<strong>•</strong> Always wastes time (almost)<br />
©Christian Hochberger Slide 37 of47
<strong>C<strong>DFG</strong></strong> – Predication (2)<br />
<strong>•</strong> Implementation<br />
– Usually by the controlling state machine<br />
<strong>•</strong> State machine waits for condition result<br />
<strong>•</strong> State machine enters corresponding state sequence<br />
<strong>•</strong> Individual schedules for each branch<br />
(<strong>and</strong> condition computation)<br />
<strong>•</strong> Resources required:<br />
– Maximum per resource type of (V cond ,V if , V else )<br />
<strong>•</strong> Execution time:<br />
– Maximum of if <strong>and</strong> else branch + condition computation<br />
©Christian Hochberger Slide 38 of47
<strong>C<strong>DFG</strong></strong> – Predication Example<br />
if ((i4)/3 < 7) {<br />
s += x;<br />
} else {<br />
s += x * (i 3);<br />
}<br />
x = x * 1.3;<br />
i = i + 1;<br />
Resources:<br />
/ < * +<br />
©Christian Hochberger Slide 39 of47<br />
0<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
<br />
*<br />
+<br />
<br />
/<br />
<<br />
+<br />
Alternative state<br />
sequences
<strong>C<strong>DFG</strong></strong> – Speculation<br />
<strong>•</strong> Concurrent execution of<br />
– Condition computation<br />
– Alternative branches<br />
<strong>•</strong> When all three are ready<br />
– Select variable values according to condition<br />
– Expressed in PHI functions in SSA<br />
– Translates to multiplexers in HW<br />
<strong>•</strong> Does not work for all programming constructs<br />
©Christian Hochberger Slide 40 of47
<strong>C<strong>DFG</strong></strong> – Speculation (2)<br />
<strong>•</strong> Implementation<br />
– Build circuit for condition computation + if-branch + else<br />
branch<br />
– Analyze variable usage (easy with SSA)<br />
– Introduce multiplexers for identical variables in alternative<br />
branches<br />
<strong>•</strong> Resources required:<br />
– Sum of all resources (V cond ,V if , V else )<br />
<strong>•</strong> Execution time:<br />
– Maximum of if-branch, else branch <strong>and</strong> condition<br />
computation<br />
©Christian Hochberger Slide 41 of47
<strong>C<strong>DFG</strong></strong> – Speculation Example<br />
if ((i4)/3 < 7) {<br />
s += x;<br />
} else {<br />
s += x * (i 3);<br />
}<br />
x = x * 1.3;<br />
i = i + 1;<br />
<br />
Resources:<br />
/ < * +<br />
©Christian Hochberger Slide 42 of47<br />
0<br />
1<br />
2<br />
3<br />
4<br />
<br />
*<br />
+<br />
<br />
/<br />
<<br />
+<br />
Additional time step<br />
+ mux may be necessary
<strong>Control</strong> Memory <strong>Data</strong> <strong>Flow</strong> <strong>Graph</strong> (CM<strong>DFG</strong>)<br />
<strong>•</strong> Arrays <strong>and</strong> records cause problems in SSA<br />
<strong>•</strong> Reason: Both relate to memory areas<br />
<strong>•</strong> General memory access problems:<br />
– May not occur in speculation<br />
– <strong>Often</strong> limited number of concurrent accesses<br />
<strong>•</strong> Solution:<br />
– Treat memory access as first class node type in graph<br />
– CM<strong>DFG</strong> has three node types:<br />
<strong>•</strong> <strong>Control</strong> flow<br />
<strong>•</strong> Memory access<br />
<strong>•</strong> <strong>Data</strong> flow<br />
©Christian Hochberger Slide 43 of47
CM<strong>DFG</strong> – Example<br />
i = 0;<br />
while (i
Problem <strong>and</strong> Resource <strong>Graph</strong><br />
<strong>•</strong> Problem graph:<br />
– Generalization of data flow graphs<br />
– Nodes for all tasks (node set V)<br />
– Edges for all data dependencies (edge set E)<br />
<strong>•</strong> Resource graph:<br />
– Node set V R = V ∪ V T<br />
– Set V T contains node for all resource types<br />
– Edges (v i ,r k ) with v i ∈ V <strong>and</strong> r k ∈ V T :<br />
Task v i can be accomplished by r k<br />
– Edge weights describe the time required for the operation<br />
©Christian Hochberger Slide 45 of47
Problem <strong>and</strong> Resource <strong>Graph</strong> - Example<br />
while (i
Problem <strong>and</strong> Resource <strong>Graph</strong> – Pros/Cons<br />
<strong>•</strong> Pro:<br />
– Alternative implementations can be described<br />
– Only immediate dependencies<br />
– Simplifies graph<br />
<strong>•</strong> Cons:<br />
– <strong>Control</strong> flow not captured<br />
– Complicates RTL generation<br />
©Christian Hochberger Slide 47 of47