DRAM Technology

DRAM
Technology
Research & Development Division
Yunseok Chun, Ph.D. (yunseok.chun@skhynix.com)
© 2012 SK hynix Semiconductor Inc.
This document is proprietary and confidential of SK hynix Semiconductor Inc.

Tutorial Overview
DRAM Technology
Objectives
• To provide an introduction to current DRAM
technology, DRAM fundamental,
scaling trends & challenges

Contents
• Overview
• DRAM Fundamentals
• DRAM Scaling
• Wrap-up

Overview
• Applications & Classification
• Business
• Cost
• Technology Acceleration

Chips
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Memory Chip Applications
DRAM
Flash
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Classification of Memory
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Industry
반도체 회사
• 제조
• 불량부품 교체 불가
• Yield ~80%
• 파급효과 : 小
자동차 회사
• 조립
• 불량부품 교체 가능
• Yield ~100%
• 파급효과 : 大
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History of DRAM
Dr. Robert H. Dennard,
IBM Fellow
created the one-transistor
DRAM in 1966
World 1’st Available DRAM Chip
Intel 1103
1966
. 1 Kb
. 3 Transistors
1’st DRAM Chip with 1-Tr. & 1-Cap.
MK4096
[Source : S.Y. Cha(Hynix), VLSI Short Course 2011]
1970
. 4 Kb
. 1-Tr. & 1-Cap.
. Address multiplexing
. VDD : 11.4~12.6V
. Access time of 300ns
. Refresh time of 2ms
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1973

DRAM in Semiconductor Industry
Sensor
[Source : WSTS 2011]
Analog
Opto
Discrete
$ 226.2 billion in 2011
Other
Memory
Logic
NAND SRAM
Memory
MPU
Other Micro
$ 22.4 billion for DRAM
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DRAM Producer
▷ Elpida
▷ Hynix
▷ Micron
▷ Nanya
▷ PowerChip
▷ ProMos
▷ Samsung
▷ Winbond
1985 1995 2000 2009 2015
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Rapid Scaling
2002
58,062ea of 130nm
256Mb DDR DRAM cell in a hair
Thickness of a human hair : ~ 100㎛ (Average)
[Source : S.Y. Cha(Hynix), VLSI Short Course 2011]
2010
506,844ea of 4xnm
1Gb DDR3 DRAM cell in a hair
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DRAM Scaling Trend
Minimum Feature Size [nm]
200
90
80
70
60
50
40
30
20
Die cost =
Cost =
wafer cost
net die * yield
Die cost + Test cost + Package cost
final test yield
[Source : ITRS]
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[Year]

Net die ?
200mm (8 inch)
4
10
82
86
18
76
28
38
48
58
68
ex) 86 ea vs. 210 ea
300mm (12 inch)
2배 이상의 cost가 들어가지 않으면 300mm Wafer 사용이 이익
8
18
30
44
194
204
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210
58
74
90
106
122
138
154
168
182

DRAM 제품 제조 과정
Design
Circuit Design
Wafer Processing
Photo
Lithography
Test & Package
Wafer
Test
Etch
Layout Drawing Mask Making
Diffusion
Implantation
Inspection & Measurement
Thin Film
(CVD/PVD)
Die & Wire Encap-
Dicing Bonding sulation
CMP
Cleaning
Test &
Burn-in
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DRAM Fundamentals
• MOSFET
• Chip Architecture
• DRAM Operation

What is MOSFET ?
Source
0V
Gate
Gate Oxide Gate Oxide
N+ N+
N+
- - - - - - - - - N+
X
P-Substrate
B
V DS
Drain
Source
Channel
V GS > V T V DS
Gate
P-Substrate
Off State On State
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B
Drain

MOS-C ?
Metal-Oxide-Semiconductor Capacitor
MOSFET ?
Metal-Oxide-Semiconductor Field Effect Transistor
CMOS ?
Oxide
Complementary MOSFET : NMOS + PMOS Low Power
V GB
N+ Gate
2 terminal 4 terminal
N+ N+
P-Substrate P-Substrate P-Substrate
V GS
B
Short channel effect
MOS-C MOSFET (Long Channel) MOSFET (Short Channel)
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V DS
V GS
B
V DS

NMOS & PMOS Structure
Vs
NMOSFET PMOSFET
Vg(Vgs>0) Vd(Vds>0)
N+ Poly
oxide
e
N+ N+
P-type 기판(P-Well)
Vb(Vbs0, Vbs

MOSFET Performance
x
Source
L D
V GS
Gate
N+ N+
Leff
Ldrawn
P-Substrate
B
V DS
Drain
High Performance
& Low Power
1. Maximize On Current !
2. Minimize Off Current !
Z
y
I D V DS =2V
V DS =0.05V
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Logarithmic Scale
0
V T
Ideal MOS Current
1 2 3
On Current
COX
W
I D GS
2 L
Off Current
2 V V
T
V GS

DRAM Chip Architecture
1 MAT
Cell Array
Bit line sense amp
Peripheral Circuit
Word Line
Sub WL
driver
Bit Line
Cell Transistor
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Cell Capacitor
SN
SNC
BLC
Cell
BL
Peripheral Transistor
Peripheral

Devices inside DRAM Chip
Cell
Cell Transistor
Cell Capacitor
Word line, Bit line, Contacts
1 MAT
Cell Array
Bit line sense amp
Sub WL
driver
Peripheral Transistors
High speed/ Low power
S/A Transistor for Sensing
SWD Transistor for driving WL
with High Voltage
Transistors for voltage generation
Role Area Ratio
Cell Data storage 50~55 %
Core Data restoring 25~30 %
peripheral Control-logic / In-Out interface ~20 %
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Word Line
Bit Line

DRAM Cell
Word Line
SN SN
SN
Gate
Cell capacitor
(Charge storage)
Si
BL
Bit Line
capacitor
1. Word Line
Access Transistor Gate Control ( On/Off )
Storage Node High Data 보다 승압된 젂원 Level 사용
Poly-Si Layer (또는 WSi 2, W)
2. Bit Line
Data Transfer Line
Read/Write 공용
Half Vcore level Precharge for Power Saving
3. Access Transistor
Switch기능의 NMOS Transistor 1개
Refresh 특성강화 위해 High Vt 설정
4. Capacitor
Data 저장 장소
Storage Node의 Charge량에 의해 Data유지
REFRESH 필요
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BL
1 Transistor 1 Capacitor DRAM Cell
WL
CAP
BL
WL
2 Transistors on 1 Active
Bit Line (V BL)
: Data Path
to Bit Line Sense Amp.
Word Line (V (VWL) WL) WL)
: Control signal
to Access Transistor
Body (V (VBB) BB) BB)
: Substrate
Storage Node (V SN)
: Storing charges
to Word line Driver
Access (Cell) Transistor
: Switching Bit line to storage node
Common Plate (V CP)
: Keeping Plate constant
Cell Capacitor (C S)
: Keeping stored charges
If V SN is high voltage, then cell data is “1”.
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Basic DRAM operation
Capacitor
(Cs)
Q s=Cs*Vcore
Cell Tr.
(Vth, Ids, Rc)
Bit-Line
(Cbl)
Vcore/2
Q b=Cbl*Vcore/2
Sense
Amplifier
/Bit-Line
(Cbl)
Vcore/2
Q b=Cbl*Vcore/2
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Basic DRAM Operation
WL
BL /BL
BL S/A
BL /BL
Restore
Sensing
Active (RAS) → Row Address Input & Decoding → BL S/A Activation
→ Read/Write (CAS) → Column Address Input & Decoding
→ Column selection signal enable (Yi) → Data Sensing (or Write Drive) → Data Out
V PP
V Core
V BLP
V SS
BL & /BL
Data
S/A
Write
Driver
Active
WL
Command
Enable
S/A
Enable
Data Input
Register
Pipe
Register
WL
Read/Write
Available
Output
Buffer
BL
△V Charge Sharing
/BL
Input
Buffer
Precharge
Command
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I/O
PAD
WL & S/A
Disable

Basic Operation : Write
V PP
Total Cell Resistance to write data (Rc)
= R ch (Channel Resistance of Cell Tr)
+ R BLC (Bit Line Plug Contact Resistance)
+ R SNC (Storage Node Contact Resistance)
+ R BL (Bit Line Resistance)
Vcore for writing “1”
V SS (0V) for writing “0”
Even though the technology shrinks down,
Rext
R ch is mainly depends on the V PP Level, mobility,
dimension of Cell transistor, gate oxide thickness.
But, the maximum value of V PP is limited by the
reliability of gate oxide.
Total Rc should be maintained under a certain
value in order to satisfy tWR specification(~12ns).
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Basic Operation : Read
V core or V ss
When the desired WL is selected, charge of
capacitor is transferred between the storage cell
/BL
BL
and the connected bit line.
But, only small voltage is applied to the connected
bit line due to high capacitance of bit line.
Sense amplifier has to amplify that small difference.
V BLP (~1/2V core)
V BLP ± ΔV
C B : Bit line capacitance ~ (3~4)xCs
B
Sense
Amplifier
( V V
1
C / C
core BLP
V
~ 150 mV
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S
)

Basic Operation : Retention
Field
Ox.
4
5
-
+
-
+
-
+
-
+
SNC Gate BLC
1
Capacitor
2
Leakage paths losing data
1) Junction leakage
2) GIDL
3) Off-leakage
3
The dynamic nature of DRAM requires that the memory
be refreshed periodically so as not to lose the contents
of the memory cells.
Refreshed every 64ms typically (as defined by JEDEC)
4) Field Tr. leakage
5) Capacitor leakage
Cells with low retention time (Tail Cells)
are screened, and then replaced
(repaired) by redundancy cells.
Stored charge
CS
C
tREF
V
B
BLP 1 VOffset
a CS
Sensing ability
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Basic Operation : Sensing Margin
Sensing Signal
ΔV =
V core-V blp
1+C BL/C S
Sensing Margin
= ΔV – S/A Offset
S/A Offset
In order for sense amplifier to amplify
successfully, a certain amount of
sensing margin is necessary except for
intrinsic offset and noise from total
charge sharing voltage.
Noise by data pattern
As technology shrinks down,
△V decrease due to reduced Cell
Capacitance (Cs) & Vcore
Intrinsic offset increase by RDF
Intrinsic offset by VT Mismatch
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DRAM Scaling
• Scaling Methods
• Scaling Challenges

Target of Bit growth
[Source : WSTS ]
We should keep the cost-down to
36% every year.
Therefore, Bit growth should be
more than 50% (considering Costdown
and investments) for each
technology generation.
the number of net die can increase
about 40% as the technology shrinks
about 20%.
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Scaling
1. Design Rule
. 80nm → 60nm → 40nm
. Resolution
2. Cell Layout
. 16F 2 → 8F 2 → 6F 2 → 4F 2
3. Chip Design
. Cell Efficiency
. Chip Architecture
Wavelength Wavelength (nm) (nm)
436
365
365
248
248
193
193
Optical
(Ultraviolet)
DUV : Deep Ultraviolet
VUV : Vacuum Ultraviolet
EUV : Extreme Ultraviolet
157
126
광원의 g-line i-line i-line line KrF KrF
종류
ArF ArF F 2 Ar 2
DUV VUV
13
Non-Optical
1 4x10-3 5x10-5 1 4x10-3 5x10-5 EUV XRL EPL IPL
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Cell Area Factor
toward more compact
Unit Cell Area 8F 2 6F 2 4F 2
Schematic
Special
Feature
Normal Twist Tr Vertical Tr
Sensing Folded Open Open
Cell Cap. Area 4F 2 3F 2 2F 2
S/A Pitch 4 BL Pitch 2 BL Pitch 2 BL pitch
Merits
WL
BL
SNC BLC
2F
Noise immunity
Large Cs
Demerits Large cell size
Active area
4F
2F
WL
BL
3F
Medium cell
Small Cb
WL
2F
Large noise
BL
Integration difficulty
2F
Small cell
Small Cb
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Folded vs. Open BL Scheme
SA
Scheme
Folded
Bit line
(8F 2 )
Open
Bit line
(4/6F 2 )
SA
SA
SA
Cell Architecture
6F 2
Layout
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Types of Transistors
Type of
Transistor
Applied
Voltage
Gate Oxide
Thickness
Gate Length
Contact
Key
Requirements
Cell Transistor
VPP ( ~ 3.0V) VDD (1.5V @DDR3)
Peripheral Transistors
Normal Transistor BLSA Latch Transistor SWD Transistor
Vcore
( 1.0~1.3V @DDR3)
VPP (~3.0V)
Thick Oxide Slim Oxide Thick Oxide
Minimum Feature Size
(ex. 45nm)
Self-aligned contact
with minimum gate
spacer
Low Junction leakage
Short channel margin
High operating current
Minimum Lg in the
peripheral circuit
(ex. ≥ 80nm)
Maximize Lg within
pitched layout
(ex. ≥ 120nm)
Maximize Lg within
pitched layout
(ex. ≥ 140nm)
Hole or Slit contact
High Speed
Short channel margin
Small local variation Good Reliability
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DRAM Technology Node
Scaling Challenges of DRAM Technology
50nm
40nm
30nm
20nm
10nm
Patterning
Cell Capacitor
Retention Time
Sensing Margin
Parasitic resistance
Gate Oxide of Peri Tr
Big Challenges !
2008 2009 2010 2011 2012 2013 2014 2015
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Year

Shrink Limitations : Transistor
Cell Tr
Peri Tr
Planar
WSix
N+
BC-PMOS
Recessed Fin Vertical Nanowire
WSix
P+
SC-PMOS
P+
100 100 80 80 60 40 40 20 1020
W
W-SC
Technology (nm)
Technology Node (nm)
W
P+
Strained
/ ESD
Fin
/HKMG
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Cell Transistor : Considerations on Scaling
Lower Retention time caused
by increased electric field.
Lower On-Current caused by
decreased dimension.
Higher Off-Leakage current
caused by short channel effect.
[Source : S.Y. Cha(Hynix), VLSI Short Course 2011]
Process margin
D/R
Refresh Time
On-Current
Off-Leakage
Scale down
How to increase retention time ?
How to increase on-current ?
How to improve short channel margin ?
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Cell Transistor : History & Future Trends
Cell Area [um2]
0.2
0.1
0.05
0.01
0.005
0.003
0.002
Planar Cell
C-Halo
Recess Gate
8F2
8F2
Sphere RG
150 120 100 80 60 50 40 30 20
6F2
6F2
Gate
Active
Saddle Fin FET
Buried Gate
4F2
Vertical Gate
4F2
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Why Scaling ?
T
pd
CV
I
C ox WLV
W
eff C ox
L
( V
V th )
Lateral scaling
Iop ↑, Cap. ↓
Higher density
Higher performance
Low Power
Vertical scaling
Vt ↓/ St ↑/△Vt↑/μ↓ Ig↑/Cj↑/Rs↑
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Conventional Scaling Method for Peri Tr.
Power
Jn↓
Vth↓
Tox↓
Lg↓
+
New
Technology
Goal
High performance
Low power
Performance
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MOSFET Scaling Method
S
Wd
eff COX
W
IOP GS
2 L
TSC
2 V V
V by DIBL
l
T
G
Lg
Sub
Vgs
Tox
Vds
L
/ 2l
L
/ l
2( V 2 ) V
e 2e
bi
t
si oxWd
ox
B
As gate length & width are scaling down,
Tox should be also scaled by 1/k
in order to maintain the same Iop & DIBL.
DS
D
I
'
op
l
eff
'
C
2
Scaling factor k
Gate Length (L) 1/k
Gate Width (W) 1/k
Gate Oxide (t ox) 1/k
Depletion width (W d) 1/k
'
Voltage (V)
W '
L'
Iop 1
Power
2 ' '
V
OX V
GS T
t
' '
si Wd
ox
ox
'
Iop Iop
G
S D
Wd
k
1
1
Lg
k
Sub
k
k
Vgs
k
Tox
k
' '
& L / l L / l
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Vds
k

How to Increase the Transistor Performance?
COX
W
I D GS
2 L
(1) VDD 증가
I D
0 V T
On Current 증가
2 V V
V GS
T
(2) Vt 감소
I D
Off Current 증가
0 V T
On Current 증가
V GS
(3) Width 증가
I D
Off Current 증가
0 V T
VDD는 감소 추세 Stand-by Power 증가 면적 증가
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On Current 증가
V GS

How to Increase the Transistor Performance?
COX
W
I D GS
2 L
(4) Gate Length 감소
I D
0 V T
On Current 증가
Off Current 증가
2 V V
V GS
T
(5) Gate Oxide thickness 감소
I D
Off Current 감소
0 V T
On Current 증가
Transistor margin 열화 Best Practice !!
V GS
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New Approaches for Peripheral Tr.
Structural
Change
Material
Change
Substrate
Change
eff COX
W
IOP GS
2 L
▶ Elevated S/D
▶ FinFET
▶ Multi-channel MOSFET
▶ SOI Wafer
▶ Hybrid Oriented Substrate
▶ High Mobility Substrate
▶ High-k / Metal Gate
▶ Strained Si
2 V V
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T

Homework
1. “Peripheral Transistor Scaling” 하기위한 많은 Paper 들이 있습니다.
다양한 Paper들 중 위 내용에 해당되는 Paper 한 개를 선택하여 요약 하십시오.
- Title
- Author
- Journal name (IEDM, SOVT 등)
- 기존 문제 및 연구 목적
- 목적을 달성하기 위한 기본 원리 (무엇을 개선하기 위해 어떤 기술을 사용했는지)
- 결과 (무엇이 얼마나 개선되었는지)
- A4 1~2 Page 분량
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Thank you