ASML/Micronic Technology Developments - Sematech

Optical Maskless Lithography (OML)
Project Status
Timothy O’Neil, Arno Bleeker, Kars Troost
/ Slide 1
SEMATECH ML2 Conference
January 2005

Agenda
Introduction and Principles of Operation
DARPA Program Activities
w Contrast Device Test Stands
w Systems Engineering
w Modeling Results
Micronic SIGMA 7300 results
Summary and Conclusions
/ Slide 2

Project Status within ASML
ASML views OML as natural extension of the optical
lithography roadmap, especially for low wafer/mask situations
Throughout 2004, technical and commercial studies have
been performed
w Technical
• SLM contrast device
Projection and illumination optics
Datapath
w Commercial
Customer applications
Product positioning and roadmap
/ Slide 3

Advantages of OML
Fab transparency (e.g. same resist platform as mask-based)
Advances in conventional mask-based lithography are readily
extendable to OML
w Wavelength reduction
w Immersion
w OPC
w Strong phase-shifting
Maskless lithography provides
w Reduced cost of introduction and faster time-to-market for new designs
w Reduced cost of manufacturing of low-volume designs
Leverages TWINSCAN® platform and optics expertise at
customer and within ASML
/ Slide 4

OML: Projected Key Specifications
Technology node: 65/45nm half pitch
Wavelength: 193 nm
Illumination: Conventional, Annular, Dipole,
Quasar, .....
Throughput: 5 wph (300mm)
/ Slide 5
Optical
Maskless
Scanner
TWIN
SCAN
XT
MASK
LESS

Optical Maskless Lithography
System Overview
Concept
w Illumination light is reflected from a
dynamic pattern generating device
(Spatial Light Modulator, or SLM)
w SLM contains a section of a desired
circuit pattern
w Pattern is imaged onto a substrate
through a high de-magnification
projection lens
First Technology Use: Micronic
w Sigma 7300 photomask writing
system (results reported in this
meeting)
w One SLM (16 µm mirrors, 1 MPixel)
(1): Sandström, et al. Micronic Laser Systems. “Pattern Generation with SLM Imaging”.
Proceedings of SPIE Vol. 4562 (2002)
/ Slide 6
(1)

DUV
Laser
Imaging Engine of the OML Scanner
The Spatial Light Modulator (SLM)
OML Scanner
Illum
Optics
SLM Contrast
Devices
>100x Proj
Optics
Image
Plane
/ Slide 7
Example Contrast
Device:
Micronic / Fraunhofer SLM
16 µm square tilting pixels
8 mm x 33mm active area
512 x 2048 pixels
(1.048 MPixels per SLM)
Multiple devices are used
in parallel to achieve
throughput requirements
Multiple contrast device technologies are being evaluated.
(2) Sandström, et al. Micronic Laser Systems. “Pattern Generation with SLM Imaging”.
Proceedings of SPIE Vol. 4562 (2002)
(2)
(2)

Systems Engineering
Alternative Pixel Geometries
Tilt
Phase-Step Tilt
Piston
ASML is actively engaging with all SLM suppliers to evaluate
actuation principles and alternatives.
/ Slide 8
Operating Principle Phase & Intensity Range
Phase interference between
each half of mirror creates net
intensity thru tilt.
Like tilt with λ/4 phase step.
Provides balanced intensity
range for 0 o and 180 o phase.
Pure phase manipulation.
Interference with neighboring
mirrors manipulates intensity.
0 o phase: 0% - 100%
180 o phase: 0% - 4%
0 o phase: 0% - 50%
180 o phase: 0% - 50%
Any phase between 0 o and
360 o : 0% - 100%

Tilt SLMs
Principle of Image Formation
Bright (full reflection into
pupil) when mirror is at zero
tilt
Gray Tone (partial reflection
into pupil) at intermediate tilt
positions
Attenuated Phase Shift
(reflection into pupil with 180o phase shift) when mirror tilt is
beyond λ/4 height difference
edge-to-edge
Capable of emulating the
imaging capabilities of binary
and att-PSM masks.
/ Slide 9
Tilt Mirror Intensity

Phase-Step Tilt SLMs
emulate alt-PSM and
CPLTM Masks
Dark (no reflection into pupil)
when mirror is at zero tilt
Bright (70% reflection),
symmetrical in positive and
negative phase
Gray Tone (partial reflection
into pupil) at intermediate tilt
positions for both positive and
negative phase
/ Slide 10
Im(Refl)
[Phase]
Re(Refl)
[Amplitude]
Amplitude
+0.7
0
-0.7
Clear
Dark
Attenuated
Shifted
Tilt α

Piston SLMs emulate
also alt-PSM, CPLTM
and multi-phase masks
Gray Tone (grouped mirrors
for destructive interference) by
alternating pistons in
checkerboard pattern.
w Gray-tone based on relative
heights in checkerboard
w Phase based on the average
height of the checkerboard
Phase Edge (line interference)
by alternating rows / columns
of height.
/ Slide 11

Writing Strategy:
Loading and Writing a Pattern
1. Break die pattern into stripes.
Idealized pattern SLM
data calibration
5. For each stamp, apply pixel calibration data
and send final processed image to SLM.
/ Slide 12
+ =
2. Break stripe into micro-stripes.
Each micro-stripe spans one row of
SLMs in the array.
Micro-shot n Micro-shot n+1 Micro-shot n+2
4. Address the position of the next stamp in the
micro-stripe. This address determines the pattern
data from the die to be included in stamp.
3. Load full micro-stripes
into each SLMs drive
electronics.
Data to be sent
to SLM 6. Wafer is printed by controlling the
sequence of stamps and stripes across
all SLMs in the array.

Writing Strategy:
Field Writing Strategies
Field Writing Strategy I
A given stripe in all fields on
the wafer is exposed before
proceeding to the next stripe
/ Slide 13
Field Writing Strategy II
All stripes in a given row of
fields are exposed proceeding
to the next row of fields
Field Writing Strategy III
All stripes in a given field are
exposed proceeding to the next
field in the column
The data path architecture can be configured for
different field writing strategies.

Data Path: In-line Rasterization
Once
per Design
[60... min]
Once
per Lot
[60 min]
Once
per wafer
[12 min]
Once
per Die
525GB
(800GB)
Parse
convert
0.2 GB/s
/ Slide 14
Design file:
525 GB ATP
800GB Max.
750GB
(1.2TB)
Rasterization
supersample
2 GPix/s
Extraction & Rasterisation
twice per wafer
80% eff. writing time,
Image cache:
I/O bandwidth: 2.8 GB/s
34 servers (9TB)
Invariant pixel
manipulations
2 GPix/s
2 x 26 GB
Variant pixel
Manipulations
250 GPix/s
Print buffer:
holds 2 image
stripes (SDRAM)
To DAC’s,
Amp’s &
SLM

Data Path: Off-line Rasterization
Once
per Lot
[60 min]
Design file:
525 GB ATP
800GB Max.
Once
per Design
[60... min]
Once
per wafer
[12 min]
Once
per Die
525GB
(800GB)
/ Slide 15
Intermediate storage:
IO bandwidth: 0.4 GB/s
8 servers (2TB)
Parse
Convert
0.2GB/s
750GB
(1.2TB)
Rasterize
Supersample
0.4GPix/s
860GB
(1.4TB)
1.4GB/s
Invariant pixel
manipulations
2 GPix/s
Image cache:
I/O bandwidth: 1.6 GB/s
22 servers (6TB)
2x0.7 TB
Variant pixel
Manipulations
250 GPix/s
Print buffer:
Holds 2 shots for
entire die (SDRAM)
To DAC’s,
Amp’s &
SLM

Technical Challenges OML
SLM Contrast Device
w Mirror variability
w Calibration
w Manufacturability
Lasers with improved pulse-to-pulse stability and jitter
performance
Rasterization for different contrast device types
Logistics for seamless factory integration of OML
/ Slide 16

Agenda
Introduction and Principles of Operation
DARPA Program Activities
w Contrast Device Test Stands
w Systems Engineering
w Modeling Results
Micronic SIGMA 7300 results
Summary and Conclusions
/ Slide 17

Program Activities
DARPA Contract Awarded to ASML, June 30, 2004
Development of calibration and imaging test stands
w Characterize SLM mechanical properties, including shape, dynamic response,
flatness, height variation, repeatability, drift, etc.
Test Bench 1: White Light Interferometer
w Demonstrate SLM imaging capabilities with aerial image measurements at target
wavelength.
Test Bench 2: SLM Calibration and Imaging Test Stand
Characterize and image multiple candidate contrast devices
w Working closely with Fraunhofer and DARPA-sponsored contrast device suppliers
Systems Engineering
w Pixel Geometry Tradeoff Study -- developing modeling tools to simulate the
lithographic imaging performance of different SLM types (e.g. tilt, piston, etc.), and
the imaging impact of known imperfections
w System Requirements and Error Budgets -- developing system performance
budgets to be able to place specifications on critical contrast device parameters
w Calibration and Rasterization Algorithm Development -- developing calibration
and pattern generation schemes for optimizing the imaging performance of each
contrast device type and incorporating low k1 imaging enhancements (e.g. off-axis
illumination, OPC, etc.)
/ Slide 18

White Light Interferometer Measurements
Zygo NewView 5000 Series System for Surface Profiling
/ Slide 19
Images courtesy of Zygo Corportation
http://www.zygo.com/nv5000/nv5000.htm
Z resolution ~ 0.1nm
Lateral resolution ~ 0.5 µm

Zygo White Light Tester
Device Independent Infrastructure
IBM Workstation
Control Software:
LabVIEW 7.1 / C
Frame grabber
Serial port
GPIB Interface
TCP/IP Network
/ Slide 20
Camera &
Interferometer
Zygo NewView 5032
Contrast Device Drive Electronics
ASML Computer interfaces with Zygo NewView 5032
Illumination Source
Stages
DUT

Slide 21

Aerial Image Tester
Optical Magnification of SLM Image
Available magnifications
are 3, 9.6 and 24 x
In the tester, SLM mirrors
are not resolved at image
plane.
The optical design mimics
the condition of a future
OML tool.
Contrast Device
Mirror Array
/ Slide 22
Image at CCD

Aerial Image Tester
Device Independent Infrastructure
IBM Workstation
Control Software:
LabVIEW 7.1 / C
Frame grabber
Serial port
GPIB Interface
/ Slide 23
Camera & Controller 193 nm Litho Laser
Hamamatsu CCD
ASML Aerial Image
Tester
Contrast Device Drive Electronics
Lambda NovaLine A2010
XY Stage & Controller
Physik Instrumente
ASML Computer Controls laser, drives stages, collects camera images
DUT

Pattern Generator & Device Drive Electronics
Architecture Supports Multiple Contrast Devices
2 meter
flexible
interconnect
/ Slide 24
Pattern Generator PCB (host)
Memory
Data Path Transfers Mirror
Contrast
Pattern from PC Device to Driver Contrast PCB
FPGA
(plug in module)
Device
USB 2.0
Interface
1 GByte
Pattern Generator PCB (Host)
Accepts Contrast Device Driver PCB plug-in
module (customizable plug-in)
Required mirror settings are downloaded over
USB port and stored in 1 GByte of memory
Field Programmable Gate Array (FPGA) drives
18 channels of 12 bits @ 20 Mhz (4.3 Gbps)
FPGA is re-configurable via the USB port to
support multiple contrast devices
Digital Interface
DAC Amp
Analog Outputs
Contrast
Device
Interface
PCB
DUT
1/2 meter flexible
interconnect
Contrast Device Driver PCB (Module)
150 x 150 mm CMC plug-in module
Baseline design drives 16 analog outputs with
30V swing and 10 bit accuracy at 10-20 MHz
Modules will be developed as needed to drive
specific contrast devices
Host / module are scalable to drive more lines by
using multiple boards

Calibration and Imaging Test Stand
Status
Tester Optical Design has been completed
w Mag Lenses and electronics have been designed to accommodate
different SLM from Silicon Light Machines, Micronic, and Lucent
Technologies.
Projection Optics Optical fabrication complete Jan 2005
Illumination Optics fabrication complete Feb 2005
Optical assembly expected completion Feb 2005
Datapath/Electronics Complete March of 2005
Integration of imaging tester complete March 2005
Testing of static contrast devices March 2005
Testing of final devices Q4 05
/ Slide 25

Systems Engineering
Impact of SLM Imperfections
Imperfection
Mirror Reflectance
Mirror Height Variation
Mirror Flatness (Intra-Mirror)
Mirror Gap Properties
SLM Global Flatness
/ Slide 26
Impact on Imaging
Non-uniform intensity, resulting in
contrast reduction, poor uniformity,
errors in CDU and overlay
Non-uniform phase, resulting in
contrast reduction, poor uniformity,
errors in CDU and overlay
Non-uniform intensity and phase across
the mirror, resulting in contrast
reduction, poor uniformity, errors in
CDU and overlay
Stray light and/or undesired
interference with mirrors, resulting in
image degradation
Non-flat chip results in telecentricity
effects at the wafer

Systems Engineering
Height Variation and its Impact on the Aerial Image thru Focus
-50 nm defocus,
2.25% uniformity
/ Slide 27
-25 nm defocus,
1.3% uniformity
Best focus,
0.4% uniformity
+25 nm defocus,
1.2% uniformity
+50 nm defocus,
2% uniformity

Applications
Sample Imaging Applications with OML
Double-dipole elbow
Isolated line exposure dose window
Memory cell
Alternating Phase Shift with Trim
OPC with Gray Scaling
Dense Contact Holes
/ Slide 28

Applications
Double Dipole Decomposition of 70 nm Elbows
Simulation
w NA 0.93, 193 nm
w Dipole, sigma
0.7/0.8/30o w Tilt Mirror SLM
w High-NA vector
unpolarized model
w No OPC
Results
w Elbow features print the
same in mask-based
and OML
w Any OPC needed is
exactly the same for
mask-based and OML
/ Slide 29
Data + =
Exp. 1 Exp. 2
Y (nm)
-400
-300
Vertical Component
-200
-200
Mask
-100
0
100 +
-100
0
100 =
200
200
Y (nm)
-400
-300
300
Horisontal Component
400
-400 -200 0
X (nm)
200 400
Y (nm)
300
400
-400 -200 0
X (nm)
200 400
-400
-300
Vertical Component
-200
-200
OML
-100
0
100 +
-100
0
100 =
200
200
Y (nm)
-400
-300
300
Horisontal Component
400
-400 -200 0
X (nm)
200 400
300
400
-400 -200 0
X (nm)
200 400
Y (nm)
Y (nm)
-400
-300
-200
-100
0
100
200
300
Resulting Image
400
-400 -200 0
X (nm)
200 400
-400
-300
-200
-100
100
200
300
0
Resulting Image
400
-400 -200 0
X (nm)
200 400
Courtesy of Micronic

Applications
Exposure Dose Window, 50 nm Isolated Line w/ Scatter Bars
Simulation:
w NA 0.93, 193 nm, dipole illumination
w Tilt Mirror SLM
w High-NA vector unpolarized model
w 30 nm OML pixels (wafer scale)
Line: 1.67 pixels wide
Scatter Bars: 0.67 pixels wide
Result: Matched Exposure Latitude with Mask-Based & OML
6% Att-PSM Reticle
/ Slide 30
OML
20
Data
50
220

Applications
Memory Cell Gate Layer with OPC and Custom Illumination
Original Pattern
Aerial Image Intensity thru Focus
/ Slide 31
Rasterized Pattern w/ OPC Optimized Illuminaton
for Improved Depth of Focus
Best Focus -50 nm de-focus -100 nm de-focus

Applications
Alternating PSM with Binary Trim Mask
Mask
+
/ Slide 32
Contrast Device
35 nm
+
Height (nm)
250
200
150
100
w Phase-Step Tilt Mirror SLM, 30 nm wafer scale,
0.93 NA in resist
w Printed linewidth is 35 nm
w Linewidth and resist cross-section is
maintained as the image is shifted through the
mirror grid
50
Resist Cross Sections
Grid shift 0 nm
Grid shift 5 nm
Grid shift 10 nm
Grid shift 15 nm
Grid shift 20 nm
Grid shift 25 nm
Grid shift 30 nm
0
-100 -50 0
X (nm)
50 100
Height (nm)
20
15
10
5
0
15 20
X (nm)
Courtesy of Micronic

Applications
Optical Proximity Correction (OPC) with Gray Scaling
Without OPC
With OPC
/ Slide 33
Mirror Tilt
[mrad]
7
6
5
4
3
2
1
0

80 nm Half-Pitch Contact Holes
/ Slide 34
Shift = 0 nm

80 nm Half-Pitch Contact Holes
/ Slide 35
Shift = 5 nm

80 nm Half-Pitch Contact Holes
/ Slide 36
Shift = 10 nm

80 nm Half-Pitch Contact Holes
/ Slide 37
Shift = 15 nm

80 nm Half-Pitch Contact Holes
/ Slide 38
Shift = 20 nm

80 nm Half-Pitch Contact Holes
/ Slide 39
Grayscaling makes
aerial image
independent of grid
position
Shift = 20 nm

Agenda
Introduction and Principles of Operation
DARPA Program Activities
w Contrast Device Test Stands
w Systems Engineering
w Modeling Results
SLM based Printing Results: Micronic SIGMA 7300
Summary and Conclusions
/ Slide 40

Slide 41
Micronic Sigma7300
SLM-based mask writer for 65 and 45 nm reticles

Micronic Sigma7300
Second generation SLM-based mask writer
Status January 2005
Product development finalized
β-shipment late 2003
Field evaluation completed at major mask
shop. System selected.
Shipping to customers
Major application space
Quick turn-around and cost-effective
production of 65 nm and 45 nm node
reticles
Interconnect layers (manhattan &
X-design)
2nd 150 nm dense
on mask
level printing of advanced PSM
(alt-PSM, CPL)
/ Slide 42
150 nm space
on mask

Sigma7300 Technical Data
Laser
SLM
Optics
Data channel
Throughput
/ Slide 43
KrF (248nm), 2 kHz excimer
One SLM Gen. 2B
512 x 2048 mirrors
16 x 16 µm Al alloy mirror
Lifetime ~6 months (24/7 op.)
0.82 NA
200x de-magnification
FPGA
Supports 2 Gpixel/sec
On-line pattern accuracy
enhancements, e.g. Corner
Enhancement (CE)
3-hour 6” reticle write time (using
four exposure passes)
Independent of design and OPC
(>100 Gb mask data volume)
SLM chip module in Sigma7300
16x16 µm Al alloy
micro mirrors

Corner Enhancement (CE)
CAD data
/ Slide 44
Gray pixel data
in pass #1
SEM image
Sigma7300 exposure
Gray scale enhancements at corners for increased pattern fidelity
Line-end shortening, corner pullback and OPC fidelity match 50 keV VSB
Pattern matching to 1st level for 2nd level printing of advanced PSM
On-line enhancement in FPGA Adjustment Processor
No throughput penalty

Corner Enhancement (CE)
CAD data
/ Slide 45
Gray pixel data
in pass #1
SEM image
Sigma7300 exposure
Gray scale enhancements at corners for increased pattern fidelity
Line-end shortening, corner pullback and OPC fidelity match 50 keV VSB
Pattern matching to 1st level for 2nd level printing of advanced PSM
On-line enhancement in FPGA Adjustment Processor
No throughput penalty

Total job time (hours)
Throughput
Write time in high-quality mode (4-pass) is typically 3 hours
Throughput only depends on the mask layout
Independent of pattern design and OPC (>100 Gb mask data volume)
3-pass or 2-pass write modes for looser mask requirements. Same resolution and
address unit as in 4-pass mode.
Non-critical patterns, e.g. text and barcodes, printed with 1-pass
10
9
8
7
6
5
4
3
2
1
0
Total mask write times, including overhead, in different write modes
Typical 90-nm node metal layer reticle
4-pass 4-pass with CE 3-pass 2-pass
/ Slide 46
Mask layout

Performance on Mask
Resolution
w Min. dark assist line 130 nm
w Min. clear assist line 170 nm
w CD linearity, iso space

CD Linearity
CD Linearity
Isolated lines and spaces

Global CD Uniformity
132x132 mm. Composite 260 nm isolated spaces.
X Y
Linewidth
3-sigma
Range/2
260 nm
6,2
5,7
/ Slide 49
5 nm
- 5 nm
Linewidth
3-sigma
Range/2
260 nm
5,0
5,0
5 nm
- 5 nm

Any Angle Performance
Good performance for X-design
Angular CD variation
w 4.4 nm (0,45,90,135 degree)
w 5.5 nm (any angle)
CDU and LER almost independent
of pattern orientation
Throughput independent of pattern
orientation
/ Slide 50
CD (nm)
520
510
500
490
480
0
30
60
90
120
150
180
210
Angle (Deg)
240
270
300
330
360

Second Layer Alignment for PSM
Sigma7300 PSM alignment monitor plate, May-October 2004.
Layer to layer overlay (nm)
Layer to layer overlay (nm)
60
50
40
30
20
10
0
60
50
40
30
20
10
0
1
1
3
3
5
5
/ Slide 51
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
Plate # (May-Oct. 2004)
31
Plate # (May-Oct. 2004)
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
X 3s
X Mean
Y 3s
Y Mean

Conclusions
Sigma7300, a second generation SLM-based mask writer, is shipping to
customers
Performance on mask meets or exceeds expectations
Field evaluation completed at major mask shop. System selected.
Major application space:
w 65 and 45 nm interconnect layer reticles
w Second layer printing of advanced PSM (AAPSM, CPL)
/ Slide 52

Agenda
Introduction and Principles of Operation
DARPA Program Activities
w Contrast Device Test Stands
w Systems Engineering
w Modeling Results
SLM based Printing Results: Micronic SIGMA 7300
Summary and Conclusions
/ Slide 53

Summary OML Advantages
Save money on mask costs
Improve time to market for prototype, low-volume,
and medium-volume wafer runs
w Fab transparency with the same lithographic processes l, NA,
resists, (OPC)
Enable strong-phase shift applications that are
impossible or prohibitively expensive with masks
Make Engineering and Development easier
w Enable more characterization tests for processes / design libraries
w Evaluate alternative designs and design iterations in resist
/ Slide 54

Current Wafer Fab
All designs
All reticles
/ Slide 55
All wafers
Regular
scanners
All output
wafers

Vision on Future Wafer Fab
High volume designs
Few reticles
New designs
/ Slide 56
Most wafers
Few wafers
New and Low-Volume and
Medium-Volume Designs
Maskless
scanners
Regular
scanners
High volume
wafers
Low volume
and design
prototype wafers

Conclusions
ASML is actively investigating OML as lower-NRE, more
flexible alternative to mask-based lithography for
w Lower cost and faster design verification in silicon
w Lower cost low-volume production of ASICs and SOCs
Micronic SIGMA 7300 results proves SLM based printing
The SLM for a 5-wph 65/45nm OML Scanner is actively
addressed through US (DARPA) and European cooperation
w Supporting mask-equivalent 65/45nm imaging performance
ASML Views “FAB Transparency” as a key advantage of OML
Acknowledgements
w This work is partly sponsored by DARPA under Contract # N66001-04-
C-8027
/ Slide 57