Synopsys FPGA Licensing Guide
Synopsys FPGA Licensing Guide
Synopsys FPGA Licensing Guide
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Copyright and License Agreement<br />
LO<br />
Copyright and License Agreement<br />
<strong>Synopsys</strong>, Inc. makes no representations or warranties, either expressed or<br />
implied, by or with respect to anything in this manual, and shall not be liable<br />
for any implied warranties of merchantability or fitness for a particular<br />
purpose of for any indirect, special or consequential damages.<br />
Copyright Notice<br />
Copyright © 2008 <strong>Synopsys</strong>, Inc. All Rights Reserved.<br />
<strong>Synopsys</strong> software products contain certain confidential information of<br />
<strong>Synopsys</strong>, Inc. Use of this copyright notice is precautionary and does not<br />
imply publication or disclosure. No part of this publication may be reproduced,<br />
transmitted, transcribed, stored in a retrieval system, or translated<br />
into any language in any form by any means without the prior written<br />
permission of <strong>Synopsys</strong>, Inc. While every precaution has been taken in the<br />
preparation of this book, <strong>Synopsys</strong>, Inc. assumes no responsibility for errors<br />
or omissions. This publication and the features described herein are subject<br />
to change without notice.<br />
Trademarks<br />
Registered Trademarks (®)<br />
<strong>Synopsys</strong>, AMPS, Astro, Behavior Extracting Synthesis Technology, Cadabra,<br />
CATS, Certify, Design Compiler, DesignWare, Formality, HDL Analyst,<br />
HSPICE, Identify, iN-Phase, Leda, MAST, ModelTools, NanoSim, OpenVera,<br />
PathMill, Physical Compiler, PrimeTime, SiVL, SCOPE, Simply Better Results,<br />
SNUG, SolvNet, Synplicity, the Synplicity logo, Synplify, Synplify Pro,<br />
Synthesis Constraints Optimization Environment, TetraMAX, VCS, Vera, and<br />
YIELDirector are registered trademarks of <strong>Synopsys</strong>, Inc.<br />
ii Synplicity <strong>Licensing</strong> User <strong>Guide</strong>, October 2008