Preliminary

D
C
B
A
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8 7 6
5 4 3 2 1
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
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Table of Contents
System Block Diagram
Power Block Diagram
BOM Configuration
Revision History
JTAG Scan Chain
FUNC TEST
Power Aliases
SIGNAL ALIAS
CPU FSB
CPU Power & Ground
CPU Decoupling
eXtended Debug Port (XDP)
MCP CPU Interface
MCP Memory Interface
MCP Memory Misc
MCP PCIe Interfaces
MCP Ethernet & Graphics
MCP PCI & LPC
MCP SATA & USB
MCP HDA & MISC
MCP Power & Ground
MCP79 A01 Silicon Support
MCP Standard Decoupling
MCP Graphics Support
SB Misc
FSB/DDR3 Vref Margining
DDR3 SO-DIMM Connector A
DDR3 SO-DIMM Connector B
DDR3 Support
Right Clutch Connector
VENICE CONNECTOR
Ethernet PHY (RTL8211CL)
Ethernet & AirPort Support
ETHERNET CONNECTOR
Schematic / PCB #’s
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
T18_MLB
DRAGON
M97_MLB
M97_MLB
M97_MLB
M97_MLB
T18_MLB
T18_MLB
RAYMOND
T18_MLB
T18_MLB
T18_MLB
T18_MLB
T18_MLB
T18_MLB
T18_MLB
T18_MLB
T18_MLB
T18_MLB
T18_MLB
T18_MLB
T18_MLB
RAYMOND
T18_MLB
M97 MLB SCHEMATIC
REFERENCED FROM T18
08/27/2008
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PVT BUILD
051-7537 1 SCHEM,MLB,M97
SCH
CRITICAL
820-2327 1
PCBF,MLB,M97
Contents
PCB
BEN
BEN
BEN
BEN
BEN
CRITICAL
Sync
T17_MLB
YITE
YITE
SUMA
SUMA
SUMA
Date
08/22/2007
12/12/2007
03/13/2008
04/04/2008
04/21/2008
12/12/2007
12/12/2007
03/31/2008
12/12/2007
04/04/2008
04/04/2008
04/04/2008
04/04/2008
04/04/2008
04/04/2008
04/04/2008
06/26/2008
04/04/2008
03/08/2008
04/04/2008
12/12/2007
04/05/2008
03/31/2008
06/30/2008
05/09/2008
04/04/2008
04/22/2008
03/13/2008
05/23/2008
07/01/2008
04/04/2008
(.csa)
Page Contents
36
45
SATA Connectors
04/14/2008
CHANGZHANG
37
46
External USB Connectors
YUAN.MA
01/18/2008
38
48
Front Flex Support
YUAN.MA
05/28/2008
39
49
SMC
T18_MLB
06/26/2008
40
50
SMC Support
YUAN.MA
05/28/2008
41
51
LPC+SPI Debug Connector
05/09/2008
CHANGZHANG
42
52
M97 SMBUS CONNECTIONS
BEN
04/21/2008
43
53
VOLTAGE SENSING
YUNWU
02/04/2008
44
54
Current Sensing
YUNWU
04/07/2008
45
55
Thermal Sensors
YUNWU
03/20/2008
46
56
Fan
01/18/2008
CHANGZHANG
47
57
WELLSPRING 1
YUAN.MA
04/22/2008
48
58
WELLSPRING 2
YUAN.MA
05/09/2008
49
59
SMS
YUNWU
06/26/2008
50
61
SPI ROM
05/02/2008
CHANGZHANG
51
62
AUDIO: CODEC
AUDIO
07/01/2008
52
63
AUDI0: MIKEY
AUDIO
07/03/2008
53
66
AUDI0: SPEAKER AMP
AUDIO
07/01/2008
54
67
AUDIO: JACK
AUDIO
07/01/2008
55
68
AUDIO: JACK TRANSLATORS
AUDIO
07/01/2008
56
69
DC-In & Battery Connectors
JACK
03/13/2008
57
70
PBUS Supply/Battery Charger
RAYMOND
01/31/2008
58
72
5V/3.3V SUPPLY
RAYMOND
02/08/2008
59
73
1.5V/0.75V DDR3 SUPPLY
RAYMOND
01/31/2008
60
74
IMVP6 CPU VCore Regulator
RAYMOND
01/31/2008
61
75
MCP VCORE REGULATOR
RAYMOND
01/31/2008
62
76
CPU VTT(1.05V) SUPPLY
RAYMOND
02/08/2008
63
77
MISC POWER SUPPLIES
RAYMOND
01/23/2008
64
78
POWER SEQUENCING
YUAN.MA
04/22/2008
65
79
POWER FETS
YUAN.MA
04/04/2008
66
90
LVDS CONNECTOR
NMARTIN
04/04/2008
67
93
DISPLAYPORT SUPPORT
AMASON
04/18/2008
68
94
DisplayPort Connector
AMASON
06/30/2008
69
97
YITE
08/12/2008
06/30/2008
70
98
LCD BACKLIGHT DRIVER
LCD Backlight Support
YITE
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DIMENSIONS ARE IN MILLIMETERS
THIRD ANGLE PROJECTION
DESIGNER
DESCRIPTION OF CHANGE
APPLE INC.
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
8 7 6 5 4 3 2 1
Sync
Date
XX
X.XX
X.XXX
ANGLES
71 CPU/FSB Constraints
72 Memory Constraints
73 MCP Constraints 1
74 MCP Constraints 2
75 Ethernet Constraints
76 SMC Constraints
DO NOT SCALE DRAWING
DRAFTER
ENG APPD
QA APPD
RELEASE
METRIC
MATERIAL/FINISH
NOTED AS
APPLICABLE
REV ZONE ECN
(.csa)
Page Contents
DESIGN CK
MFG APPD
SCALE
NONE
SIZE
D
TITLE
DRAWING NUMBER
Sync
CK
APPD
100 01/04/2008
T18_MLB
101 01/04/2008
T18_MLB
102 01/04/2008
T18_MLB
103 12/14/2007
T18_MLB
104 03/19/2008
T18_MLB
106 01/04/2008
77
107
M97 SPECIAL CONSTRAINTS
T18_MLB
M97_MLB
78
109
M97 RULE DEFINITIONS
M97_MLB
Preliminary
Date
DATE
A 625211 PRODUCTION RELEASED 08/29/08 ?
SCHEM,MLB,M97
051-7537
REV.
SHT 1 OF
ENG
APPD
A
DATE
109
D
C
B
A

D
C
B
A
8 7 6 5 4 3 2 1
J4510
J4520
J9000
J9400
SATA
Conn
LVDS
CONN
PG 71
DISPLAY PORT
CONN
PG 71
CLK
SATA
TMDS OUT
J3400 U3900
Mini PCI-E
AirPort
PG 28
Conn
HD
SATA
ODD
PG 38
PG 38
1.05V/3GHZ.
1.05V/3GHZ.
GPIOs
SYNTH
PG 19
LVDS OUT
RGB OUT
DP OUT
HDMI OUT
DVI OUT
PG 16
PG 17
UP TO 20 LANES3
PCI-E
U1000
U3700
RGMII
PG 17
GB
E-NET
88E1116
PG 31
E-NET
Conn
PG 33
INTEL CPU
2.X OR 3.X GHZ
PENRYN
PG 9
PG 13
FSB INTERFACE
NVIDIA
MCP79
U1400
FSB
64-Bit
PCI
(UP TO FOUR PORTS)
800/1067/1333 MHz
LPC
USB
PG 19
MAIN
MEMORY
PG 14
Misc
PG 24
SPI
PG 20
PG 18
PWR
CTRL
(UP TO 12 DEVICES)
SMB
PG 20
HDA
PG 20
0 1 2 3 4 5 6 7 8 9
U1300
J4720
2 UDIMMs
PG 40
XDP CONN
8 7 6 5 4 3 2 1
J6800,6801,6802,6803
J4710
U6301 U6400
U6500
Amp
PG 54
PG 12
DDR2-800MHZ
DDR3-1067/1333MHZ
Bluetooth
J2900
J4700
DIMM
PG 25,26
U6100
TRACKPAD/
KEYBOARD
PG 40
DIMM’s
U6200
HEADPHONE
PG 55
SPI
Boot ROM
PG 52
Audio
Codec
PG 53
Audio
Conns
PG 59
J4900
IR
PG 40
B,0
Line Out
PG 56
BSB
SMC
J4710
PG 41
ADC
PG 40
Fan
CAMERA
SMB
CONN
PG 44
U6600,6605,6610,6620
Speaker
Amps
PG 57
Ser
Prt
J6950
U4900
J3900,4635,4655
EXTERNAL
USB
PG 39
DC/BATT
TEMP SENSOR
PG 41
POWER SENSE
PG 45
J5650,5600,5610,5611,5660,5720,5730,5750
FAN CONN AND CONTROL
Connectors
PG 48,49
J5100
LPC Conn
Port80,serial
PG 43
POWER SUPPLY
Preliminary
PG 18
Line In
Amp Amp
PG 60
SYNC_MASTER=T18_MLB
APPLE INC.
System Block Diagram
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
051-7537
SHT OF
2
SYNC_DATE=12/12/2007
REV.
109
A
D
C
B
A

D
C
B
A
15-1
8 7 6 5 4 3 2 1
AC
ADAPTER
IN
DCIN(16.5V)
6A FUSE
J6950
3S2P
(9 TO 12.6V)
MCP79
PM_SLP_S4_L
U1400
PCI_RESET0#
RC
DELAY
RC
DELAY
RC
DELAY
RC
DELAY
SLP_S3#
11
15
15
Q3801
PM_SLP_S3_L
P1V8S0_EN
MCPDDR_EN
CPUVTTS0_EN
MCPCORES0_EN
16-3
16-2
16-3
16-4
11-1
11-3
RC
DELAY
11-2
U7970
16
A
SMC_DCIN_ISENSE
BATT_POS_F
PM_SLP_S3_L
RC
DELAY
PM_ENET_EN_L
01
Q3802
WOL_EN
Q7050
SMC_ADAPTER_EN 04-1
P1V05S0_EN
(S0)
P3V3S0_EN
(S0)
PBUSVSENS_EN
(S0)
P5VRTS0_EN_L
(S0)
ENABLES
VIN
CHGR_EN
(S5)
VOUT
PBUS SUPPLY/
BATTERY CHARGER
CHGR_BGATE
P3V3S3_EN
DDRREG_EN
P5VLTS3_EN
16-2
PPVBAT_G3H_CHGR_OUT
M97 POWER SYSTEM ARCHITECTURE
U4900 04
P60
SMC_PM_G2_EN
(S5)
=DDTVTT_EN
S5
S3
7A FUSE
PPVBAT_G3H_CHGR_REG
TPS51116
U7300
U5403
SMC_BATT_ISENSE
IMVP_VR_ON
SMC_PM_G2_EN
PPVOUT_S0_LCDBKLT
1.2V YUKON
VIN U3850
VOUT1
RUN1
LTC34074
RUN2
VOUT2
25
P5VRTS0_EN_L
16-2 MCP_CORE
VOUT2
MCPCORES0_EN
EN2
16-2
16-1
ISL6258A
U7000
SMC
BKLT_EN
P16
=DDRREG_EN
PPBUS_G3H
VIN
11-2
02
02
01
A
GOSHAWK6P
U9701
ENA VOUT
ENETADD_EN
P1V2ENET_EN
P5VLTS3_EN
Q7800
02
D6905
D6905
RC
DELAY
14
02
06
P1V05_S5_EN
05
P3V3S5_EN_L
S3 TO S0
FETS
(Q7901 & Q7971)
EN1
VIN
ISL6236
U7500
PPVIN_G3H_P3V42G3H
PPBUS_G3H
02
3.3V
TPS51125
U7200
P5V3V3_PGOOD
(1.9V)
PPVOUT_ENET_AVDD_REG
(0.8A MAX CURRENT)
PP1V2_ENET_REG
(0.8A MAX CURRENT)
VOUT1
CPU VCORE
VOUT
VIN
ISL9504B
VR_ON
PGOOD
U7400
PP1V5_S0_FET
06
VIN
EN1 5V
(RT) VOUT1
EN2
PGOOD1,2
V
Q5315
CPUVTTS0_EN
(S0)
U5480
1.05V (S5)
U7750 VOUT
R5491
PP0V75_S0_REG
(1A MAX CURRENT)
12
02
PP1V5_S3_REG
(12A MAX CURRENT)
ENABLE
3.425V G3HOT
LT3470
PP1V05_S5_REG
(44A MAX CURRENT)
PP1V05_S0_FET
1.8V LDO
TPS79918DRV PP1V8_S0_REG
U7760
MCP_PS_PWRGD
8 7 6 5 4 3 2 1
V
SMC_CPU_ISENSE
08
PP1V5_S0
02
(1.05V)
21
28
20
PPVCORE_S0_MCP_REG_R R5490
PPVCORE_S0_MCP
(25A MAX CURRENT)
PP5VLT_S3_REG
PBUS_VSENSE
VOUT2
VREG3
(7A MAX CURRENT)
A
VR_PWRGOOD_DELAY
P1V05S0_EN
TPS62510
PP5VRT_S0_REG
(4A MAX CURRENT)
PP3V3_S5_REG
(4A MAX CURRENT)
VIN
EN_PSV VOUT
CPUVTT
TPS51117
U7600
PGOOD
U6990 VOUT
CPUVTTS0_PGOOD
SMC_CPU_VSENSE
1.05V SO
FETS
(Q7951 TO Q7953)
PP5VLT_S3
P3V3ENET_EN_L
PP3V42_G3H_REG
PPCPUVTT_S0_REG_R
(8A MAX CURRENT)
PPVCORE_CPU_S0_REG
Q7910
Q7930
P3V3S3_EN
P3V3S0_EN
P3V3_ENET_FET
26
03
23
22
R5492
PP3V3_S0_FET
19-1
PP3V3_S0
PP1V5_S0
PP1V05_S0
SMC PWRGD
RN5VD30A-F
U5000
18
04
PPCPUVTT_S0
4.6V AUDIO
VIN MAX8902A
PP4V6_AUDIO_ANALOG
U6201
EN
VOUT
PP5VRT_S0
PP3V3_S5
PP3V3_S3_FET
MCPCORESO_PGOOD
CPUVTTS0_PGOOD
P5V_LT_S3_PGOOD
S0PGOOD_PWROK
V1
V2
V3
RST*
17
07
13
P5V3V3_PGOOD
U2850
ALL_SYS_PWRGD
09
24
29
RSMRST_PWRGD
SMC_ONOFF_L
05
SLP_S5_L
SLP_S4_L
SLP_S3_L
PS_PWRGD
CPUPWRGD(GPIO49)
APPLE INC.
MCP79
U1400
RSMRST*
CPU_RESET# FSB_CPURST_L
CPU
RESET*
U1000
PWRGD(P12) 99ms DLY
IMVP_VR_ON(P16)
RSMRST_IN(P13)
PLT_RST*
PWR_BUTTON(P90)
P17(BTN_OUT)
Preliminary
VIN
1.5V
VOUT1
0.75V
VOUT2
5V (LT)
Q3810
LTC2909
U7870
SLP_S4_L(P94)
SLP_S3_L(P93)
U4900
PWRBTN*
PLTRST*
PWRGOOD
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
LPC_RESET_L
32
DRAWING NUMBER
NONE
06-1
31
CPU_PWRGD
30
SMC
10
RSMRST_OUT(P15) PM_RSMRST_L
SLP_S5_L(P95)
RST*
IMVP_VR_ON
25
PM_PWRBTN_L
SMC_RESET_L
Power Block Diagram
SYNC_MASTER=DRAGON SYNC_DATE=03/13/2008
051-7537
SHT OF
3
REV.
109
A
D
C
B
A

D
C
B
A
BOM Variants
BOM NUMBER
BOM GROUP
8 7 6 5 4 3 2 1
BOM NAME
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
BOM OPTIONS
BOM OPTIONS
630-9554 PCBA,MLB,BETTER,M97 M97_COMMON,CPU_2_0GHZ,EEE_2KA
630-9314 PCBA,MLB,BEST,M97
M97_COMMON,CPU_2_4GHZ,EEE_1DJ
BOM Groups
Module Parts
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
Programmable Parts
Alternate Parts
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
PART NUMBER
152S0778
M97_MCP
M97_DEBUG_ENG SMC_DEBUG_YES,XDP,XDP_CONN,LPCPLUS,VREFMRGN,TPAD_DEBUG
M97_DEBUG_PVT
M97_DEBUG_PROD
337S3622
337S3646
1
1
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
SMC_DEBUG_YES,XDP,LPCPLUS,NO_VREFMRGN
SMC_DEBUG_YES,XDP,LPCPLUS_NOT,NO_VREFMRGN
PDC,QJGL,QS,2.0,25W,1066,M0,3M,BGA U1000 CRITICAL
CPU_2_0GHZ_QS
337S3625 1 PDC,QDYJ,QS,2.4,25W,1066,M0,3M,BGA
U1000 CRITICAL
CPU_2_4GHZ_QS
PDC,SLG8E,PRQ,2.0,25W,1066,M0,3M,BGA U1000 CRITICAL
CPU_2_0GHZ
337S3653 1 PDC,SL3BU,PRQ,2.26,25W,1066,C0,3M,BGA
U1000 CRITICAL
CPU_2_26GHZ
337S3639 1
PDC,SLB4N,PRQ,2.4,25W,1066,M0,3M,BGA
U1000 CRITICAL
CPU_2_4GHZ
338S0540 1
IC,GMCP,MCP79,35X35MM,BGA1437,A01 U1400 CRITICAL MCP_A01
338S0603 1 IC,GMCP,MCP79,35X35MM,BGA1437,A01Q U1400
CRITICAL
MCP_A01Q
338S0600 1 IC,GMCP,MCP79,35X35MM,BGA1437,B01 U1400
CRITICAL
MCP_B01
335S0610
1
IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP
CRITICAL
BOOTROM_BLANK
341S2285 1 IC,PRGRM,EFI BOOTROM,UNLOCK,M97
U6100
CRITICAL
BOOTROM_PROG
152S0796 152S0685 ALL CYNTEC AS ALTERNATE
157S0058 157S0055
ALL
104S0018 104S0023 ALL DALE/VISHAY AS ALTERNATE
128S0093 128S0218
ALL KEMET AS ALTERNATE
152S0874
M97_COMMON
M97_MISC
338S0570 1
MCP_B02,MCP_PROD,MEMRESET_HW,MEMRESET_MCP,BOOT_MODE_USER,MCPSEQ_SMC,MCP_CS1_NO
341S2287 1
IC,SMC,M97
U4900
CRITICAL SMC_PROG
341S2348
1 IC,WELLSPRING CONTROLLER,M97
U5701
CRITICAL WELLSPRING_PROG
152S0693 ALL CYNTEC AS ALTERNATE
152S0516
DELTA AS ALTERNATE
ALL MAGLAYERS AS ALTERNATE
152S0847 152S0586
ALL MAGLAYERS AS ALTERNATE
514-0612 514-0607
ALL
FOXLINK AS ALTERNATE
514-0613 514-0608
ALL FOXLINK AS ALTERNATE
ONEWIRE_PU,BKLT_PLL_NOT,DP_ESD,ENG_BMON,MIKEY
337S3624 1 PDC,QDYD,QS,2.26,25W,1066,M0,3M,BGA
U1000
CRITICAL CPU_2_26GHZ_QS
338S0635 1 IC,GMCP,MCP79,35X35MM,BGA1437,B02
U1400 CRITICAL MCP_B02
338S0375
341S2093 1
IC,RTL8211CL,GIGE TRANSCEIVER,48P,TQFP U3700
CRITICAL
U6100
1 IC,CY7C63833,ENCORE II,USB CONTROLLER
U4800
CRITICAL IR_BLANK
337S2983 1 IC,PSOC+ W/ USB,56 PIN,MLF,CY8C24794
U5701
CRITICAL WELLSPRING_BLANK
152S0694 152S0138 ALL MAGLAYERS AS ALTERNATE
COMMON,ALTERNATE,M97_MCP,M97_MISC,M97_DEBUG_PVT,M97_PROGPARTS
M97_PROGPARTS BOOTROM_PROG,SMC_PROG,IR_PROG,WELLSPRING_PROG
338S0591 1 IC,GMCP,MCP79,35X35MM,BGA1437,A01P U1400 CRITICAL
MCP_A01P
338S0563 1 IC,SMC,HS8/2117,9X9MM,TLP,HF
U4900 CRITICAL
SMC_BLANK
IC,IR CONTROLLER,M97 U4800
CRITICAL
IR_PROG
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
Bar Code Labels / EEE #’s
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEE:2K9] CRITICAL
EEE_2K9
826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM
[EEE:2KA] CRITICAL
EEE_2KA
826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEE:1DJ] CRITICAL EEE_1DJ
M97 BOARD STACK-UP
Top
2
3
4
5
6
7
8
9
10
11
BOTTOM
SIGNAL
GROUND
SIGNAL(High Speed)
SIGNAL(High Speed)
GROUND
POWER
POWER
GROUND
SIGNAL(High Speed)
SIGNAL(High Speed)
GROUND
SIGNAL
Preliminary
SYNC_MASTER=M97_MLB
8 7 6 5 4 3 2 1
APPLE INC.
BOM Configuration
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
SHT OF
4
REV.
051-7537 A
109
D
C
B
A

D
C
B
A
Revision History
8 7 6 5 4 3 2 1
NOTE: All page numbers are .csa, not PDF. See page 1 for .csa -> PDF mapping.
Preliminary
SYNC_MASTER=M97_MLB
APPLE INC.
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
8 7 6 5 4 3 2 1
SIZE
D
SCALE
DRAWING NUMBER
NONE
A
051-7537
SHT OF
5 109
REV.
A
D
C
B
A

D
C
B
A
8 7 6 5 4 3 2 1
1.05V TO 3.3V LEVEL TRANSLATOR (M97: ON ICT FIXTURE)
=PP3V3_S0_XDP
13D6 8C5
=PP1V05_S0_CPU
12B6 11C6 10D5 8D7
13D6
JTAG_ALLDEV
R0601
10K
5%
1/16W
MF-LF
1
402
2
NOSTUFF
1
R0602 0
5%
1/16W
MF-LF
402
2
71A3 13B6 10C6 10A6 6C6
71A3 13B3 10C6 10B6 6C6
71A3 13B3 10C6 10A6 6C6
JTAG_ALLDEV
1 C0601
0.1UF
20%
2
10V
CERM
402
XDP_TCK
XDP_TMS
XDP_TRST_L
JTAG_ALLDEV
1 C0602
0.1UF
20%
2
10V
CERM
402
JTAG_LVL_TRANS_EN_L 12
OE*
1
11
VCCA VCCB
U0600
NLSV4T244
2 A1
UQFN
B1 10
3 A2
B2 9
4
5
A3
A4
B3
JTAG_ALLDEV
B4
8
7
GND
6
From XDP connector
71A3 13B6 10C6 10A6 6C7
71A3 13B3 10C6 10B6
71A3 13B3 10C6 10B6 6C7
IN
IN
IN
71A3 13B3 10C6 10A6 6C7 IN
XDP_TCK
XDP_TDI
XDP_TMS
XDP_TRST_L
From XDP connector
or via level translator
JTAG_MCP_TCK
JTAG_MCP_TDI
JTAG_MCP_TMS
JTAG_MCP_TRST_L
13B6 21B7
13C3 21B7 23C5
13C3 21B7 23C5
13C3 21B7
U1000
CPU
U1400
MCP
To XDP connector
and/or level translator
XDP_TDO
0
XDP_TDO_CONN
8 7 6 5 4 3 2 1
71A3 10C6 10B6
21B7
XDP
R0603
5%
1/16W
MF-LF
402
XDP
R0604
JTAG_MCP_TDO
0
JTAG_MCP_TDO_CONN
5%
1/16W
MF-LF
402
OUT 13B3
XDP connector
OUT 13C3
XDP connector
Preliminary
SYNC_MASTER=BEN
APPLE INC.
JTAG Scan Chain
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
051-7537
SYNC_DATE=04/04/2008
SHT OF
6 109
REV.
A
D
C
B
A

D
C
B
A
I12
I15
I16
I238
I237
I239
I227
I226
I228
I230
I229
I231
I232
I233
I259
I258
I260
I245
I262
I261
I256
I257
I255
I252
I253
I254
I250
I251
I313
I246
I247
I248
I249
I264
I268
I269
I267
I265
I266
I312
I304
I305
I306
I322
I321
I320
I326
I323
I324
I325
I310
I311
I309
I308
I307
8 7 6 5 4 3 2 1
Fan Connectors
TRUE PP5VRT_S0
TRUE FAN_RT_PWM
TRUE FAN_RT_TACH
(NEED TO ADD 3 GND TP)
MIC FUNC_TEST
TRUE MIC_HI_CONN
TRUE MIC_LO_CONN
TRUE MIC_SHLD_CONN
SPEAKER FUNC_TEST
TRUE SPKRAMP_L_N_OUT
TRUE SPKRAMP_L_P_OUT
TRUE SPKRAMP_R_N_OUT
TRUE SPKRAMP_R_P_OUT
TRUE SPKRAMP_SUB_N_OUT
TRUE SPKRAMP_SUB_P_OUT
(NEED 3 TP)
THERMAL FUNC_TEST
TRUE
TRUE
MCPTHMSNS_D2_P
MCPTHMSNS_D2_N
45B5
45B5
LVDS FUNC_TEST
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
PP3V3_LCDVDD_SW_F 7C3
PP3V3_S0_LCD_F
66C3
PPVOUT_S0_LCDBKLT 7C3
LVDS_IG_DDC_CLK 18A3
LVDS_IG_DDC_DATA 18A3
LVDS_IG_A_DATA_N
LVDS_IG_A_DATA_P
LVDS_IG_A_DATA_N
LVDS_IG_A_DATA_P
LVDS_IG_A_DATA_N
LVDS_IG_A_DATA_P
LVDS_IG_A_CLK_F_N 66B2
LVDS_IG_A_CLK_F_P 66B2
LED_RETURN_1
66B3
LED_RETURN_2
66B3
LED_RETURN_3
66B3
LED_RETURN_4
66B3
LED_RETURN_5
66B3
LED_RETURN_6
66B3
(NEED TO ADD 5 GND TP)
SATA ODD CONN
TRUE PP5V_SW_ODD (NEED 4 TP)
TRUE SMC_ODD_DETECT
36B7 39B8
TRUE SATA_ODD_D2R_C_P 36B5 73A3
TRUE SATA_ODD_D2R_C_N 36B5 73A3
TRUE SATA_ODD_R2D_P
36B5 73A3
TRUE SATA_ODD_R2D_N
7C5 36B5
(NEED TO ADD 4 GND TP)
DC POWER CONN
TRUE PP18V5_DCIN_FUSE
TRUE ADAPTER_SENSE
(NEED TO ADD 4 GND TP)
7D3 8D5
54B1 54D2
54B1 54D2
54D2 55A6
53A2 54C2
53B2 54C2
53C3 54C2
53C3 54C2
53B2 54C2
53B2 54C2
66B2 69B3 69C1
18B3 66C2 73B3
(NEED 3 TP)
BATT POWER CONN
TRUE PPVBAT_G3H_CONN_F (NEED 3 TP)
TRUE GND_BATT_CONN (NEED 3 TP)
TRUE SMBUS_SMC_BSA_SCL 7A7 42C5 76D3
TRUE SMBUS_SMC_BSA_SCL 7A7 42C5 76D3
TRUE SMC_BS_ALRT_L
39C5 40B2 56A8
BATT SIGNAL CONN
(NEED 3 TP)
TRUE PP3V42_G3H
7B5 7C3
TRUE SMBUS_SMC_BSA_SCL 7A7 42C5
TRUE SMBUS_SMC_BSA_SCL 7A7 42C5
TRUE SMC_BIL_BUTTON_DB_L 56A5
(NEED TO ADD 3 GND TP)
18B3 66C2 73B3
18B3 66C2 73B3
18B3 66C2 73B3
18B3 66C2 73B3
18B3 66C2 73B3
FRONT FLEX CONN
TRUE PP3V42_G3H_LIDSWITCH_R
TRUE PP5V_S3_IR_R
38B6
TRUE IR_RX_OUT
38A4 38C4
TRUE SMC_LID_R
38B6
TRUE SYS_LED_ANODE_R 38B6
(NEED TO ADD 2 GND TP)
46B4
46C4
56D7
77D3
77D3
66C2
66C5
66B5
73B3
73B3
69C1
69B1
69B1
69B1
69B1
69B1
7C3 36D3
73A3
8D1
76D3
76D3
38B6
56D6
56A8
56A8
I303
I301
I302
I300
I299
I298
I293
I297
I294
I288
I292
I296
I291
I295
I290
I271
I289
I319
I314
I315
I318
I317
I316
I375
I374
I373
I372
I370
I371
I369
I368
I361
I366
I367
I365
I363
I364
I362
I360
I359
I357
I358
I377
I378
I354
I355
I344
I345
I346
I347
I349
I348
I350
I352
I351
I353
I327
I328
I329
I343
I342
I341
I339
I340
I338
I336
I337
I333
I335
I334
I332
I330
I331
I356
Functional Test Points
RIGHT CLUTCH CONN
TRUE PP5V_S3_BTCAMERA_F 31B7
TRUE PCIE_MINI_D2R_P 17B6 31C7 73D3
TRUE PCIE_MINI_D2R_N 17B6 31C7 73D3
TRUE PCIE_MINI_R2D_P 31C7 73D3
TRUE PCIE_MINI_R2D_N 31C7 73D3
TRUE PCIE_CLK100M_MINI_CONN_P
TRUE PCIE_CLK100M_MINI_CONN_N
TRUE USB_CAMERA_CONN_P 31B7 74C3
TRUE USB_CAMERA_CONN_N 31B7 74C3
TRUE PP5V_WLAN
7C3 31C5
TRUE PCIE_WAKE_L
17B6 23C5 31C7
TRUE SMBUS_SMC_A_S3_SCL 7B5 42D2 76D3
TRUE SMBUS_SMC_A_S3_SDA 7B5 42D2 76D3
TRUE CONN_USB2_BT_P
31B7 74B3
TRUE CONN_USB2_BT_N
31B7 74B3
TRUE MINI_CLKREQ_Q_L 31C7
TRUE MINI_RESET_CONN_L 31A7
(NEED TO ADD 3 GND TP)
SATA HDD CONN
(NEED 4 TP)
TRUE PP5V_S0_HDD_FLT 7C3 36A7
TRUE SATA_HDD_R2D_P
36A7 73A3
TRUE SATA_HDD_R2D_N
36A7 73A3
TRUE SATA_HDD_D2R_C_P 36A7 73A3
TRUE SATA_HDD_D2R_C_N 36A7 73A3
TRUE SATA_ODD_R2D_N
7B7 36B5 73A3
(NEED TO ADD 4 GND TP)
IPD_FLEX_CONN
TRUE PP3V3_S3_LDO
TRUE PP18V5_S3
TRUE TPAD_GND_F
TRUE Z2_CS_L
TRUE Z2_DEBUG3
TRUE Z2_MOSI
TRUE Z2_MISO
TRUE Z2_SCLK
TRUE Z2_BOOST_EN
TRUE Z2_HOST_INTN
TRUE Z2_BOOT_CFG1
TRUE Z2_CLKIN
TRUE Z2_KEY_ACT_L
TRUE Z2_RESET
TRUE PSOC_MISO
TRUE PSOC_MOSI
TRUE PSOC_SCLK
TRUE SMBUS_SMC_A_S3_SDA
TRUE SMBUS_SMC_A_S3_SCL
TRUE PSOC_F_CS_L
TRUE PICKB_L
KEYBOARD CONN
7C3 48B4 48C3
7C3 48C1 48D3
48B4 48C3 48C4 48C7
47C8 48C3
47C8 48C3
47C8 48C3
47C8 48C3
47C8 48C3
48C3 48C5
47D8 48C3
47C8 48C3
47B6 48C3
47C8 48C1
47C8 48C1
47C8 48C1
47C8 48C1
47C8 48C1
7C5 42D2 76D3
7D5 42D2 76D3
47C8 48C1
47D8 48C1
TRUE PP3V3_S3
7D3 8D3
TRUE PP3V42_G3H
7A7 7C3 8D1
TRUE WS_KBD1
47C6 47D2
TRUE WS_KBD2
47C6 47D2
TRUE WS_KBD3
47C6 47D2
TRUE WS_KBD4
47C6 47D2
TRUE WS_KBD5
47C6 47D2
TRUE WS_KBD6
47C6 47D2
TRUE WS_KBD7
47C6 47D2
TRUE WS_KBD8
47C6 47D2
TRUE WS_KBD9
47C6 47D2
TRUE WS_KBD10
47C6 47D2
TRUE WS_KBD11
47C2 47C6
TRUE WS_KBD12
47C2 47C6
TRUE WS_KBD13
47C2 47C6
TRUE WS_KBD14
47C2 47C6
TRUE WS_KBD15_CAP
47C2
TRUE WS_KBD16_NUM
47C2
TRUE WS_KBD17
47C2 47C6
TRUE WS_KBD18
47C2 47D7
TRUE WS_KBD19
47C2 47D7
TRUE WS_KBD20
47C2 47D7
TRUE WS_KBD21
47C2 47D7
TRUE WS_KBD22
47C2 47D7
TRUE WS_KBD23
47C2 47D7
TRUE WS_KBD_ONOFF_L
47C2
TRUE WS_LEFT_SHIFT_KBD 47B3 47B5
TRUE WS_LEFT_OPTION_KBD 47B3 47B5
TRUE WS_CONTROL_KBD
47B3 47B5
(NEED TO ADD 1 GND TP)
KBD BACKLIGHT CONN
TRUE KBDLED_ANODE
48A4
(NEED TO ADD 2 GND TP)
47C2
47C2
47C2
31C8 73D3
31C8 73D3
DEBUG VOLTAGE
TRUE PPVCORE_S0_CPU
8D7
TRUE PPCPUVTT_S0
8D7
TRUE PPVCORE_S0_MCP
8C7
TRUE PP0V75_S0
8C7
TRUE PP1V05_S0
8C7
TRUE PP1V5_S0
8B7
TRUE PP1V8_S0
8B7
TRUE PP5VRT_S0
7D7 8D5
TRUE PP3V3_S0
8C5
TRUE PP1V5_S3
8D3
TRUE PP3V3_S3
7B5 8D3
TRUE PP5VLT_S3
8C3
TRUE PP1V1R1V05_S5
8B3
TRUE PP3V3_S5
8B3
TRUE PP3V42_G3H
7A7 7B5
TRUE PPBUS_G3H
8C1
TRUE PP3V3_ENET_PHY
8B1
TRUE PP1V2R1V05_ENET 8B1
TRUE PP3V3_G3_RTC
21C8
TRUE PP5V_WLAN
7D5 31C5
TRUE PP5V_SW_ODD
7B7 36D3
TRUE PP5V_S0_HDD_FLT 7C5 36A7
TRUE PP3V3_S5_AVREF_SMC 39D4
TRUE PP18V5_S3
7C5 48C1
TRUE PP3V3_S3_LDO
7C5 48B4
TRUE PP3V3_LCDVDD_SW_F 7C7 66C2
TRUE PPVOUT_S0_LCDBKLT 7C7 66B2
TRUE BKL_VREF_4V9
69A8
TRUE PP4V6_AUDIO_ANALOG 51A3
TRUE SMC_PM_G2_EN
39D5
TRUE PM_SLP_S4_L
21C3
TRUE PM_SLP_S3_L
21C3
(NEED TO ADD 4 GND TP)
8 7 6 5 4 3 2 1
I287
I286
I285
I284
I280
I281
I282
I376
I283
I279
I278
I270
I379
I273
I274
I275
I276
I272
I393
I392
I391
I390
I389
I388
I387
I386
I385
I384
I383
I382
I381
I380
8D1
22A5 26D4
40B6
48D3
48C3
69B3 69C1
69B6 69C4 69C8
51D3 52D6
64D8
39C5 40A2 64C8
34B7 39C5 41A5 64D5 68D8
Preliminary
SYNC_MASTER=M97_MLB
APPLE INC.
FUNC TEST
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
051-7537
SHT OF
7
REV.
109
A
D
C
B
A

D
C
B
A
61C1
44D8
44D7
22D5
24D8
61B1
60D1
65A6 62C2
8 7 6 5 4 3 2 1
=PPVCORE_S0_CPU_REG
(CPU VCORE PWR)
=PPCPUVTT_S0_REG
=PPMCPCORE_S0_REG
=PPVCORE_S0_MCP_REG_R
(MCP VCORE REG. OUTPUT)
=PPVCORE_S0_MCP
(MCP VCORE AFTER SENSE RES)
59C8
65A5
=PP0V75_S0_REG
=PP1V05_S0_FET
65D1 =PP1V5_S0_FET
44C8 =PP1V5_S0_FET_R
(DDR PWR REG. OUTPUT)
44C7 =PP1V5_S0
(DDR PWR AFTER SENSE RES.)
=PP1V8_S0_REG
24D1 PP1V05_S0_MCP_PEX_AVDD
MAKE_BASE=TRUE
206 mA (A01)
24D8 8B7 =PP1V05_S0_MCP_PEX_DVDD
206 mA (A01)
24C2 PP1V05_S0_MCP_SATA_AVDD
MAKE_BASE=TRUE
127 mA (A01)
24D6 8B7 =PP1V05_S0_MCP_SATA_DVDD
127 mA (A01)
"S0,S0M" RAILS
PPVCORE_S0_CPU
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.3 MM
VOLTAGE=1.25V
MAKE_BASE=TRUE
=PPVCORE_S0_CPU
=PPVCORE_S0_CPU_VSENSE
PPCPUVTT_S0
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
MAKE_BASE=TRUE
=PP1V05_S0_CPU
=PP1V05_S0_MCP_FSB
=PP1V05_S0_SMC_LS
PPVCORE_S0_MCP_R
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
=PPVCORE_S0_MCP_VSENSE
PPVCORE_S0_MCP
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
PP0V75_S0
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V
MAKE_BASE=TRUE
=PPVTT_S0_VTTCLAMP
=PP0V75_S0_MEM_VTT_A
=PP0V75_S0_MEM_VTT_B
PP1V05_S0
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.1V
MAKE_BASE=TRUE
=PP1V05_S0_MCP_PEX_DVDD
=PP1V05_S0_MCP_AVDD_UF
=PP1V05_S0_MCP_PLL_UF
=PP1V05_S0_MCP_SATA_DVDD
=PP1V05_S0_MCP_HDMI_VDD
=PP1V05_S0_VMON
PP1V5_S0_R
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.5V
MAKE_BASE=TRUE
=PP1V5_S0_CPU
=PP1V5_S0_VMON
=PP1V5_FC_CON
PP1V5_S0
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.5V
MAKE_BASE=TRUE
=PP1V8R1V5_S0_MCP_MEM
=PP1V5_S0_MEM_MCP
PP1V8_S0
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.8V
MAKE_BASE=TRUE
=PP3V3R1V8_S0_MCP_IFP_VDD
11B5 11D6 12D6
63C2 7D3
6D8 10D5 11C6 12B6 13D6
9C2 14A2 14B7 22D3 24C8
16C3 16C7 24C8
PEX & SATA AVDD/DVDD aliases
7D3
43D8
7D3
7D3
65B3
28A4
29A4
7D3
7D3
43D8
40D3
8A8 24D8
24D4
24C4
8A8 24D6
18A6 25D7
64A8
11B6 12B6
64A8
32C3
7D3
29B3
18B6 25D7
65C6
=PP1V05_S0_MCP_PEX_AVDD0
=PP1V05_S0_MCP_PEX_AVDD1
=PP1V05_S0_MCP_PEX_DVDD0
=PP1V05_S0_MCP_PEX_DVDD1
=PP1V05_S0_MCP_SATA_AVDD0
=PP1V05_S0_MCP_SATA_AVDD1
=PP1V05_S0_MCP_SATA_DVDD0
=PP1V05_S0_MCP_SATA_DVDD1
=PP5VRT_S0_REG PP5VRT_S0
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
MAKE_BASE=TRUE
=PP5V_S0_HDD
=PP5V_S0_LPCPLUS
=PP5V_S0_FAN_RT
=PP5V_S0_CPU_IMVP
=PP5V_S0_ODD
=PP5V_S0_KBDLED
=PP5V_S0_DP_AUX_MUX
=PP5V_S0_CPUVTTS0
58B8 7D3 7D7
=PP3V3_S0_FET
17B3
17A3
17B6
17A6
20B6
20A6
20B6
20B6
206 mA (A01)
57 mA (A01)
127 mA (A01)
43 mA (A01)
PP3V3_S0
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
MAKE_BASE=TRUE
=PP3V3_S0_XDP
=PP3V3_S0_MCP
=PP3V3_S0_MCP_DAC_UF
=PP3V3_S0_MCP_VPLL_UF
=PP3V3_S0_ODD
=PP3V3_S0_LPCPLUS
=PP3V3_S0_SMBUS_SMC_0_S0
=PP3V3_S0_SMBUS_SMC_B_S0
=PP3V3_S0_SMBUS_MCP_0
=PP3V3_S0_FAN_RT
=PP3V3_S0_AUDIO
=PP3V3_S0_IMVP
=PP3V3_S0_LCD
=PP3V3_S0_MCP_GPIO
=PP3V3_S0_HDCPROM
=PP3V3_S0_MCP_PLL_UF
=PP3V3R1V5_S0_MCP_HDA
=PP3V3_S0_SMC
=PP3V3_S0_MCPTHMSNS
=PP3V3_S0_CPUTHMSNS
=PP5VR3V3_S0_MCPCOREISNS
=PP3V3_S0_DPCONN
=PPSPD_S0_MEM_A
=PPSPD_S0_MEM_B
=PP3V3_S0_PWRCTL
=PP3V3_S0_VMON
=PP3V3_S0_MCPDDRISNS
=PP3V3_S0_CPUVTTISNS
=PPVIN_S0_P1V8S0
=PP3V3_FC_CON
=PP3V3_S0_TPAD
=PP3V3_S0_SMBUS_MCP_1
36A5
41D5
46C5
60D8
36D5
48A5
67B6
62C8
7D3
6D8 13D6
21C2 22B3 24B8
25D4
25B7
36B7 36D5
41C3
42D5
42C3
42D8
46C5
51A7 51D8 52D6 54D8 55B5
60D8
66C5
18C1 19D1 21A4
25B8
24B6
21D3 21D8 24A8
40A1 40D2
45C6
45D6
44D7
68A8 68B8
28A8
29A8
64A5
64B8
44C7
44B7
63C5
32C3
48A6
42C8
=PP1V5_S3_REG
=PP3V3_S3_FET
=PP5VLT_S3_REG
=PPVTT_S3_DDR_BUF
=PP1V05_S5_REG
=PP3V3_S5_REG
"S3" RAILS
PP1V5_S3
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.5V
MAKE_BASE=TRUE
=PP1V5_S3_P1V5S0FET
=PP1V5_S3_MEM_A
=PP1V5_S3_MEM_B
=PP1V5_S3_MEMRESET
PP3V3_S3
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
MAKE_BASE=TRUE
=PP3V3_S3_SMBUS_SMC_A_S3
=PP3V3_S3_PDCISENS
=PP3V3_S3_SMBUS_SMC_MGMT
=PP3V3_S3_VREFMRGN
=PP3V3_S3_WLAN
=PP3V3_S3_MCP_GPIO
=PP3V3_S3_TPAD
=PP3V3_S3_SMS
PP5VLT_S3
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
MAKE_BASE=TRUE
=PP5V_S3_EXTUSB
=PP5V_S3_IR
=PP5V_S3_BTCAMERA
=PP5V_S3_VTTCLAMP
=PP5V_S3_MCPDDRFET
=PP5V_S3_SYSLED
=PP5V_S3_TPAD
=PP5V_S3_WLAN
=PP5V_S3_1V5S30V75S0
=PP5V_S3_AUDIO
=PP5V_S3_AUDIO_AMP
=PP5V_S3_P1V05S0FET
PPVTT_S3_DDR_BUF
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0.75V
MAKE_BASE=TRUE
"S5" RAILS
PP1V1R1V05_S5
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
=PP1V05_S5_MCP_VDD_AUXC
=PP1V05_ENET_P1V05ENETFET
=PP1V05_S5_P1V05S0FET
PP3V3_S5
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
MAKE_BASE=TRUE
=PP3V3_S5_MCP_GPIO
=PP3V3_S5_ROM
=PP3V3_S5_LCD
=PP3V3_S5_MCP
=PP3V3_S5_MCPPWRGD
=PP3V3_S5_SMBUS_MCP_1
=PP3V3_S5_MCP_A01
=PP3V3_S5_PWRCTL
=PP3V3_S5_P1V05ENETFET
=PP3V3_S5_P3V3S3FET
=PP3V3_S5_P3V3S0FET
=PP3V3_S5_P1V05S5
=PP3V3_S5_P1V05FET
=PP3V3_S5_MEMRESET
=PP3V3_S5_P3V3ENETFET
=PP3V3_S5_DP_PORT_PWR
=PP3V42_G3H_REG
=PP18V5_DCIN_CONN
=PPCPUVCORE_VTT_ISNS
(AFTER HIGH SIDE CPU VCORE
& CPU VTT SENSING RES.)
"G3H" RAILS
"ENET" RAILS
SYNC_MASTER=BEN
8 7 6 5 4 3 2 1
61C8
59D7 27D3
63B4
59B1
65D6
7D3
65D3
28D7
29D7
30C6
7B5 7D3
27D8
31A6
21A3
47A6 47B5 56D1 56B8
47C5 47D2
49B7 49D6
37C7
38B4 38D7
65D4
51A7 55D4
53B8 53C8 53D8
7C3
22A3 24C8
34C4
65B6
18C7 20C1
41B5 41C7 50C6
66C8
22B3 24B8
26B8
42C7
23C4 41B4
64B3 64C4
34D2
34B2
56B4
57C1
44B7
=PPBUS_G3H
=PP3V3_ENET_FET
=PP1V05_ENET_FET
Preliminary
58B1
42D3
59B3
42B5
7D3
31B3
65A3
40B8
48C8
31C1
59C5
65B8
7C3
34C5
65D8
65C8
63B7
65A8
30C6
34D5
68D8
APPLE INC.
PP3V42_G3H
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.42V
MAKE_BASE=TRUE
=PPVIN_S5_SMCVREF
=PP3V42_G3H_SMBUS_SMC_BSA
=PP3V42_G3H_PWRCTL
=PP3V42_G3H_CHGR
=PP3V42_G3H_SMCUSBMUX
=PP3V42_G3H_LIDSWITCH
=PP3V42_G3H_TPAD
=PP3V42_G3H_BATT
=PP3V3_S5_SMC
=PP3V3_S5_LPCPLUS
=PP3V42_G3H_RTC_D
=PP3V42_G3H_BMON_ISNS
PP18V5_G3H
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.3 MM
VOLTAGE=18.5V
MAKE_BASE=TRUE
=PP18V5_G3H_CHGR
PPBUS_G3H
7C3
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.3 MM
VOLTAGE=12.6V
MAKE_BASE=TRUE
=PPBUS_S0_LCDBKLT
=PPVIN_S0_MCPCORES0
=PPVIN_S0_MCPREG_VIN
=PPVIN_S5_1V5S30V75S0
=PPVIN_S5_3V3S5
=PPVIN_S0_5VRTS0
=PPVIN_S3_5VLTS3
=PPBUS_G3HRS5
=PPCPUVCORE_VTT_ISNS_R
(BEFORE HIGH SIDE SENSING RES.)
PPBUS_G3H_CPU_ISNS
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.3 MM
VOLTAGE=12.6V
MAKE_BASE=TRUE
=PPVIN_S0_CPUVTTS0
=PPVIN_S5_CPU_IMVP
PP3V3_ENET_PHY
7C3
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
=PP3V3_ENET_MCP_RMGT 18C7 18D3 24A6 24B6
=PP3V3_ENET_PHY
PP1V2R1V05_ENET 7C3
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
=PP1V05_ENET_MCP_PLL_MAC
=PP1V05_ENET_MCP_RMGT
=PP1V05_ENET_PHY
Power Aliases
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
33D7
33D2
051-7537
24A8
18D3 24C6
SHT OF
8
7A7 7B5 7C3
40B8
42C5
64B3 64D3 64D8
57A8 57C6 57D5
37B8
38B4
47B3 47B5 47C2
47C5
56A3 56B3
39D4 40C1 40C7
40D8 49D7
41B7 41C3 41C7
41D5
26D8
44A8
57D8
70D8
61C3
61C6
59C2
58B3
58B6 58C6
61D8
43B8
44B8
62C6
60C2 60D4 60D8
REV.
109
A
D
C
B
A

D
C
B
A
8 7 6 5 4 3 2 1
HEATSINK STANDOFFS
PCI-E ALIASES
UNUSED GPU LANES
17D6 17C6 =PEG_D2R_N
NC_PEG_D2R_N
DACS ALIASES
UNUSED CRT & TV-OUT INTERFACE
SO-DIMM ALIASES
UNUSED ADDRESS PINS
Z0902
1
LEFT OF CPU
Z0903
1
Z0901
STDOFF-4.5OD.98H-1.1-3.48-TH
1
ABOVE CPU
Z0904
STDOFF-4.5OD.98H-1.1-3.48-TH
1
NO_TEST=TRUE MAKE_BASE=TRUE
17D6 17C6 =PEG_D2R_P
NC_PEG_D2R_P
NO_TEST=TRUE MAKE_BASE=TRUE
17D3 17C3 =PEG_R2D_C_N NC_PEG_R2D_C_N
NO_TEST=TRUE MAKE_BASE=TRUE
17D3 17C3 =PEG_R2D_C_P NC_PEG_R2D_C_P
NO_TEST=TRUE MAKE_BASE=TRUE
17C6 PEG_PRSNT_L
TP_PEG_PRSNT_L
MAKE_BASE=TRUE
17C3 PEG_CLK100M_P
TP_PEG_CLK100M_P
MAKE_BASE=TRUE
17C3 PEG_CLK100M_N
TP_PEG_CLK100M_N
MAKE_BASE=TRUE
UNUSED FW LANE
18C6 MCP_TV_DAC_RSET
18C6 MCP_TV_DAC_VREF
18C6 MCP_CLK27M_XTALIN
18C6 MCP_CLK27M_XTALOUT
18C3 CRT_IG_R_C_PR
18C3 CRT_IG_G_Y_Y
18C3 CRT_IG_B_COMP_PB
18B3 CRT_IG_HSYNC
NC_MCP_TV_DAC_RSET
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_MCP_TV_DAC_VREF
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_MCP_CLK27M_XTALIN
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_MCP_CLK27M_XTALOUT
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_CRT_IG_R_C_PR
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_CRT_IG_G_Y_Y
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_CRT_IG_B_COMP_PB
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_CRT_IG_HSYNC
NO_TEST=TRUE
MAKE_BASE=TRUE
BELOW MCP
BELOW CPU
17B6 PCIE_FW_D2R_P
17B6 PCIE_FW_D2R_N
TP_PCIE_FW_D2R_P
MAKE_BASE=TRUE
TP_PCIE_FW_D2R_N
18B3 CRT_IG_VSYNC NC_CRT_IG_VSYNC
NO_TEST=TRUE
MAKE_BASE=TRUE
17B3 PCIE_FW_R2D_C_P
MAKE_BASE=TRUE
TP_PCIE_FW_R2D_C_P
MAKE_BASE=TRUE
LVDS ALIASES
FAN STANDOFF
Z0905
STDOFF-4.5OD.98H-1.1-3.48-TH
1
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V
17B3 PCIE_FW_R2D_C_N
17C6 PCIE_FW_PRSNT_L
17C6 FW_CLKREQ_L
17C3 PCIE_CLK100M_FW_P
17C3 PCIE_CLK100M_FW_N
TP_PCIE_FW_R2D_C_N
MAKE_BASE=TRUE
TP_PCIE_FW_PRSNT_L
MAKE_BASE=TRUE
TP_FW_CLKREQ_L
MAKE_BASE=TRUE
TP_PCIE_CLK100M_FW_P
MAKE_BASE=TRUE
TP_PCIE_CLK100M_FW_N
MAKE_BASE=TRUE
UNUSED LVDS SIGNALS
18B3 LVDS_IG_A_DATA_P NC_LVDS_IG_A_DATA_P3
NO_TEST=TRUE MAKE_BASE=TRUE
18B3 LVDS_IG_A_DATA_N NC_LVDS_IG_A_DATA_N3
NO_TEST=TRUE MAKE_BASE=TRUE
18B3 LVDS_IG_B_CLK_P
NC_LVDS_IG_B_CLK_P
NO_TEST=TRUE
MAKE_BASE=TRUE
18B3 LVDS_IG_B_CLK_N
NC_LVDS_IG_B_CLK_N
NO_TEST=TRUE
MAKE_BASE=TRUE
18B3 LVDS_IG_B_DATA_P NC_LVDS_IG_B_DATA_P
NO_TEST=TRUE MAKE_BASE=TRUE
UNUSED EXPRESS CARD LANE
18B3 LVDS_IG_B_DATA_N NC_LVDS_IG_B_DATA_N
NO_TEST=TRUE
MAKE_BASE=TRUE
17B6 PCIE_EXCARD_D2R_P
TP_PCIE_EXCARD_D2R_P
MAKE_BASE=TRUE
AUDIO CHASSIS GND
GND_CHASSIS_AUDIO
MAKE_BASE=TRUE
54B8 54A8 =GND_CHASSIS_AUDIO_JACK
55A4 54A3 =GND_CHASSIS_AUDIO_MIC
OMIT
Z0906
TH
1
SL-3.10X2.70
17B6 PCIE_EXCARD_D2R_N
17B3 PCIE_EXCARD_R2D_C_P
17B3 PCIE_EXCARD_R2D_C_N
17C6 PCIE_EXCARD_PRSNT_L
17C6 EXCARD_CLKREQ_L
17C3 PCIE_CLK100M_EXCARD_P
TP_PCIE_EXCARD_D2R_N
MAKE_BASE=TRUE
TP_PCIE_EXCARD_R2D_C_P
MAKE_BASE=TRUE
TP_PCIE_EXCARD_R2D_C_N
MAKE_BASE=TRUE
TP_PCIE_EXCARD_PRSNT_L
MAKE_BASE=TRUE
TP_EXCARD_CLKREQ_L
MAKE_BASE=TRUE
TP_PCIE_CLK100M_EXCARD_P
MAKE_BASE=TRUE
MISC MCP79 ALIASES
14B6 CPU_PECI_MCP
TP_CPU_PECI_MCP
MAKE_BASE=TRUE
19B7 FW_PME_L TP_FW_PME_L
MAKE_BASE=TRUE
17B6 GMUX_JTAG_TCK_L
TP_GMUX_JTAG_TCK_L
MAKE_BASE=TRUE
17B6 GMUX_JTAG_TDO
TP_GMUX_JTAG_TDO
MAKE_BASE=TRUE
19D4 GMUX_JTAG_TDI
TP_GMUX_JTAG_TDI
MAKE_BASE=TRUE
19D4 GMUX_JTAG_TMS
TP_GMUX_JTAG_TMS
17C3 PCIE_CLK100M_EXCARD_N
TP_PCIE_CLK100M_EXCARD_N
MAKE_BASE=TRUE
MAKE_BASE=TRUE
STDOFF-4.5OD.98H-1.1-3.48-TH
STDOFF-4.5OD.98H-1.1-3.48-TH
OMIT
3R2P5
Z0908
1
OMIT
Z0911
3R2P5
1
VENICE BOARD STANDOFFS
VENICE
VENICE
Z0914
Z0915
STDOFF-4.0OD3.0H-TH
1
ZS0900
1.4DIA-SHORT-EMI-MLB-M97-M98
SM
1
ZS0904
2.0DIA-TALL-EMI-MLB-M97-M98
SM
1
AIRPORT CARD PRESENT SIGNAL
31D7 17C6
MAKE_BASE=TRUE
MLB MOUNTING SCREW HOLES LAN ALIASES
OMIT
3R2P5
Z0909
1
OMIT
3R2P5
Z0912
1
STDOFF-4.0OD3.0H-TH
1
EMI IO POGO PINS
ZS0901
1.4DIA-SHORT-EMI-MLB-M97-M98
SM
EMI POGO PINS
1
ZS0905
2.0DIA-TALL-EMI-MLB-M97-M98
SM
1
OMIT
3R2P5
Z0910
1
OMIT
3R2P5
Z0913
1
VENICE
Z0916
STDOFF-4.0OD3.0H-TH
1
ZS0902
1.4DIA-SHORT-EMI-MLB-M97-M98
SM
ZS0906
2.0DIA-TALL-EMI-MLB-M97-M98
SM
1
1
17B6
17B6
17B3
17B3
17B6
17B6
17B3
17B3
PCIE_MINI_PRSNT_L
FOR VENICE CARD
TP_PE4_CLKREQ_L
FC_CLKREQ_L
20C3
20C3
20D3
20D3
20C3
20C3
TP_PE4_PRSNT_L
TP_PCIE_CLK100M_PE4P
TP_PCIE_CLK100M_PE4N
TP_PCIE_PE4_D2RP
TP_PCIE_PE4_D2RN
TP_PCIE_PE4_R2D_CP
TP_PCIE_PE4_R2D_CN
20D3
20D3
USB ALIASES
USB_EXTC_P
UNUSED USB PORTS
TP_USB_EXTC_P
USB_EXTC_N
TP_USB_EXTC_N
USB_EXTD_P
TP_USB_EXTD_P
USB_EXTD_N
TP_USB_EXTD_N
USB_EXCARD_P
TP_USB_EXCARD_P
USB_EXCARD_N
TP_USB_EXCARD_N
USB_MINI_P
USB_MINI_N
1.4DIA-SHORT-EMI-MLB-M97-M98
SM
ZS0907
2.0DIA-TALL-EMI-MLB-M97-M98
SM
1
ZS0903
1
FC_PRSNT_L
PCIE_CLK100M_FC_P
PCIE_CLK100M_FC_N
32C5
MAKE_BASE=TRUE
32B3
MAKE_BASE=TRUE
32C5 73D3
MAKE_BASE=TRUE
32C5 73C3
MAKE_BASE=TRUE
PCIE_FC_D2R_P 32B5 73D3
MAKE_BASE=TRUE
PCIE_FC_D2R_N 32B5 73D3
MAKE_BASE=TRUE
PCIE_FC_R2D_C_P 32C6 73D3
MAKE_BASE=TRUE
PCIE_FC_R2D_C_N 32C6 73D3
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
TP_USB_MINI_P
MAKE_BASE=TRUE
TP_USB_MINI_N
MAKE_BASE=TRUE
=MCP_MII_RXER
=MCP_MII_COL
=MCP_MII_CRS
DP HOTPLUG PULL-DOWN
=DVI_HPD_GMUX_INT
IN
CPU FSB FREQUENCY STRAPS
71B3 60C7 14A3 10B2 OUT
71C3 14B6 10D6 OUT
71C3 14A3 13B2 10D6 OUT
8 7 6 5 4 3 2 1
18D6
18C6
18C6
18B6
MCP_MII_PD
MAKE_BASE=TRUE
HPLUG_DET2
MAKE_BASE=TRUE
1
R0930
47K
5%
1/16W
MF-LF
2 402
1 R0940
20K
5%
1/16W
MF-LF
2 402
71C3 10B4 10A4
28C5
29C5
MEM_A_A
MEM_B_A
34C5 =P3V3ENET_EN
34B5 =P1V05ENET_EN
33C2 =PP3V3_ENET_PHY_VDDREG
33C2 =RTL8211_REGOUT
33C6 =RTL8211_ENSWREG
CPU_BSEL
MAKE_BASE=TRUE
24C8 22D3 14B7 14A2 8D7 =PP1V05_S0_MCP_FSB
71C3 14A3 10B8 OUT
71C3 14A3 10B8 OUT
ETHERNET ALIASES
Extra FSB Pull-ups
Exist in MRB but not Intel designs. Here for CYA.
If found to be necessary, will move to page14.csa
APPLE INC.
0 0 0
266
0 0 1
133
=MCP_BSEL OUT 14A7 0 1 0
200
0 1 1 (166)
1 0 0
333
1 0 1
100
1 1 0 (400)
1 1 1 (RSVD)
MCP_A01&MCP_A01P&MCP_A01Q
1
R0950
220
5%
1/16W
MF-LF
402
2
CPU_DPRSTP_L
FSB_BREQ0_L
FSB_CPURST_L
CPU_INTR
CPU_NMI
Preliminary
TP_MEM_A_A15
TP_MEM_B_A15
PM_SLP_RMGT_L
MAKE_BASE=TRUE
SYNC_MASTER=M97_MLB
NO STUFF
1
R0960
62
5%
1/16W
MF-LF
2
402
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
BSEL
NO STUFF
1
R0970
200
5%
1/16W
MF-LF
402
2
MAKE_BASE=TRUE
MAKE_BASE=TRUE
21C3
MAKE_BASE=TRUE
TP_PP3V3_ENET_PHY_VDDREG
MAKE_BASE=TRUE
NC_RTL8211_REGOUT
MAKE_BASE=TRUE
FSB MHZ
NO STUFF
1
R0990
NO STUFF
1
R0980
150
5%
1/16W
MF-LF
2
402
SIGNAL ALIAS
051-7537
SHT OF
9
150
5%
1/16W
MF-LF
402
2
REV.
109
A
D
C
B
A

D
C
B
A
8 7 6 5 4 3 2 1
71D3 14D6
71D3 14D6
71D3 14D6
71D3 14D6
71D3 14C6
71D3 14C6
71D3 14C6
71D3 14C6
71D3 14C6
71D3 14C6
71D3 14C6
71D3 14C6
71D3 14C6
71D3 14C6
71C3 14B6
71C3 14B6
71C3 14B6
71C3 14B6
71C3 14B6
71C3 14B6
71C3 14C6
71C3 14C6
71C3 14C6
71C3 14C6
71C3 14C6
71C3 14C6
71C3 14C6
71C3 14C6
71C3 14C6
71C3 14C6
71C3 14C6
71C3 14C6
71C3 14C6
71C3 14C6
71C3 14C6
71C3 14C6
71C3 14B6
71C3 14B6
71C3 14B6
71C3 14B6
71C3 14A3
71C3 14B7
71C3 14A3
71B3 14A3
71C3 14A3 9B2
71C3 14A3 9B2
71B3 14A3
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
OUT
IN
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_ADSTB_L
FSB_REQ_L
FSB_REQ_L
FSB_REQ_L
FSB_REQ_L
FSB_REQ_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_ADSTB_L
CPU_A20M_L
CPU_FERR_L
CPU_IGNNE_L
IN CPU_STPCLK_L
IN CPU_INTR
IN CPU_NMI
IN CPU_SMI_L
TP_CPU_RSVD_M4
TP_CPU_RSVD_N5
TP_CPU_RSVD_T2
TP_CPU_RSVD_V3
TP_CPU_RSVD_B2
TP_CPU_RSVD_F6
TP_CPU_RSVD_D2
TP_CPU_RSVD_D22
TP_CPU_RSVD_D3
J4 A3* U1000
L5 A4* PENRYN
L4
K5
A5*
A6*
FCBGA
1 OF 4
M3 A7*
N2 A8*
J1 A9*
N3 A10*
P5 A11*
P2 A12*
L2 A13*
P4 A14*
P1 A15*
R1 A16*
M1 ADSTB0*
K3
H2
K2
J3
L1
Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1
REQ0*
REQ1*
REQ2*
REQ3*
REQ4*
A17*
A18*
A19*
A20*
A21*
A22*
A23*
A24*
A25*
A26*
A27*
A28*
A29*
A30*
A31*
A32*
A33*
A34*
A35*
ADSTB1*
A6 A20M*
A5 FERR*
C4 IGNNE*
D5
C6
B4
A3
M4
N5
T2
V3
B2
F6
D2
D22
D3
STPCLK*
LINT0
LINT1
SMI*
RSVD0
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
ADDR GROUP0
ADDR GROUP1
ICH
RESERVED
CONTROL
XDP/ITP SIGNALS
THERMAL
BR0*
LOCK*
THERMTRIP*
H CLK
SYNC FROM T18
CHANGE CPU FROM SOCKET TO BGA SYMBOL
OMIT
ADS* H1
BNR* E2
BPRI* G5
DEFER* H5
DRDY* F21
DBSY* E1
F1
IERR* D20 71B3 CPU_IERR_L
INIT* B3 CPU_INIT_L
H4
RESET* C1
RS0* F3
RS1* F4
RS2* G3
TRDY* G2
HIT* G6
HITM* E4
BPM0* AD4
BPM1* AD3
BPM2* AD1
BPM3* AC4
PRDY* AC2
PREQ* AC1
TCK AC5
TDI AA6
TDO AB3
TMS AB5
TRST* AB6
DBR* C20
PROCHOT* D21
THERMDA A24
THERMDC B25
C7
BCLK0 A22
BCLK1 A21
FSB_ADS_L
FSB_BNR_L
FSB_BPRI_L
FSB_DEFER_L
FSB_DRDY_L
FSB_DBSY_L
FSB_BREQ0_L
FSB_LOCK_L
FSB_CPURST_L
FSB_RS_L
FSB_RS_L
FSB_RS_L
FSB_TRDY_L
FSB_HIT_L
FSB_HITM_L
XDP_BPM_L
XDP_BPM_L
XDP_BPM_L
XDP_BPM_L
XDP_BPM_L
XDP_BPM_L
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST_L
XDP_DBRESET_L
CPU_PROCHOT_L
CPU_THERMD_P
CPU_THERMD_N
PM_THRMTRIP_L
FSB_CLK_CPU_P
FSB_CLK_CPU_N
71A3 13B3 10C6 6C7 6C6 XDP_TMS
71A3 13B3 10C6 6C6 XDP_TDI
71A3 10C6 6C4 XDP_TDO
BI
BI
BI
BI
BI
BI
BI
IN
BI
IN
IN
IN
IN
IN
BI
BI
BI
BI
BI
BI
BI
IN
IN
OUT 6C4 10B6 71A3
IN
IN
OUT 13B3 26A3
OUT 45D5 77D3
OUT 45D5 77D3
OUT 14B7 40C4 71B3
IN
IN
14B6 71C3
14B6 71C3
14B3 71C3
14B3 71C3
14B6 71C3
14B6 71C3
9B2 14B6 71C3
14A3 71C3
14B6 71C3
9B2 13B2 14A3 71C3
14A6 71C3
14A6 71C3
14A6 71C3
14B6 71C3
14B6 71C3
14B6 71C3
13C6 71A3
13C6 71A3
13C6 71A3
13C6 71A3
13C6 71A3
6C6 6C7 10A6 13B6 71A3
6C6 10B6 13B3 71A3
6C6 6C7 10B6 13B3 71A3
6C6 6C7 10A6 13B3 71A3
14B3 71B3
14B3 71B3
CPU JTAG Support
R1091
54.9
1
2
1%
1/16W
MF-LF
402
R1094
649
1
2
1%
1/16W
MF-LF
402
R1000
1
54.9
1%
1/16W
MF-LF
402
2
R1001
54.9
1%
1/16W
MF-LF
402
2
R1002
R1090
54.9
1
2
1%
1/16W
MF-LF
402
R1092
54.9
1
2
PLACEMENT_NOTE=Place R1092 near ITP connector (if present) 1%
1/16W
MF-LF
402
71A3 13B6 10C6 6C7 6C6 XDP_TCK
71A3 13B3 10C6 6C7 6C6 XDP_TRST_L
R1093
54.9
1
2
1%
1/16W
MF-LF
402
1
1
68
5%
1/16W
MF-LF
402
2
=PP1V05_S0_CPU
BI
OUT 14B6 40D4 60C8 71B3
1
R1005
1K
1%
1/16W
MF-LF
402
2
1
R1006
2.0K
1%
1/16W
MF-LF
402
2
13C6 71A3
NO STUFF
1
R1011
1K
5%
1/16W
MF-LF
402
2
NO STUFF
R1010
0
1
2
5%
1/16W
MF-LF
402
6D8 8D7 11C6 12B6 13D6
NO STUFF
1 C1014
0.1uF
10%
16V
X5R
2
402
NO STUFF
1
R1012
1K
5%
1/16W
MF-LF
2
402
71D3 14D3 BI
71D3 14D3 BI
71D3 14D3 BI
71D3 14D3 BI
71D3 14D3 BI
71D3 14D3 BI
71D3 14D3 BI
71D3 14D3 BI
71D3 14D3 BI
71D3 14D3 BI
71D3 14D3 BI
71D3 14D3 BI
71D3 14D3 BI
71D3 14D3 BI
71D3 14D3 BI
71D3 14D3 BI
71D3 14D6 BI
71D3 14D6 BI
71D3 14D6 BI
71D3 14D3 BI
71D3 14D3 BI
71D3 14D3 BI
71D3 14C3 BI
71D3 14C3 BI
71D3 14C3 BI
71D3 14C3 BI
71D3 14C3 BI
71D3 14C3 BI
71D3 14C3 BI
71D3 14C3 BI
71D3 14C3 BI
71D3 14C3 BI
71D3 14C3 BI
71D3 14C3 BI
71D3 14C3 BI
71D3 14D6 BI
71D3 14D6 BI
71D3 14D6 BI
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_DSTB_L_N
FSB_DSTB_L_P
FSB_DINV_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_DSTB_L_N
FSB_DSTB_L_P
FSB_DINV_L
71B3 27B1 CPU_GTLREF
CPU_TEST1
CPU_TEST2
TP_CPU_TEST3
CPU_TEST4
TP_CPU_TEST5
TP_CPU_TEST6
TP_CPU_TEST7
71C3 9C2 OUT CPU_BSEL
71C3 9C2 OUT CPU_BSEL
71C3 9C2 OUT CPU_BSEL
PLACEMENT_NOTE=Place C1014 within 12.7mm of CPU.
PLACEMENT_NOTE=Place R1005 within 12.7mm of CPU.
PLACEMENT_NOTE=Place R1006 within 12.7mm of CPU.
8 7 6 5 4 3 2 1
N22 D16*
K25 D17*
P26 D18*
R23 D19*
L23 D20*
M24 D21*
L22 D22*
M23 D23*
P25 D24*
P23 D25*
P22 D26*
T24 D27*
R24 D28*
L25 D29*
T25 D30*
N25 D31*
L26 DSTBN1*
M26 DSTBP1*
N24 DINV1*
AD26 GTLREF
C23 TEST1
D25 TEST2
C24 TEST3
AF26 TEST4
AF1 TEST5
A26 TEST6
C3 TEST7
B22 BSEL0
B23 BSEL1
C21 BSEL2
DATA GRP 0
DATA GRP 1
OMIT
U1000
E22 D0* D32* Y22
F24 D1* PENRYN D33* AB24
E26 D2*
FCBGA D34* V24
G22 D3* 2 OF 4 D35* V26
F23 D4*
D36* V23
G25 D5*
D37* T22
E25 D6*
D38* U25
E23 D7*
D39* U23
K24 D8*
D40* Y25
G24 D9*
D41* W22
J24 D10*
D42* Y23
J23 D11*
D43* W24
H22 D12*
D44* W25
F26 D13*
D45* AA23
K22 D14*
D46* AA24
H23 D15*
D47* AB25
J26 DSTBN0*
DSTBN2* Y26
H26 DSTBP0*
DSTBP2* AA26
H25 DINV0*
DINV2* U22
MISC
DATA GRP 3 DATA GRP 2
D48* AE24
D49* AD24
D50* AA21
D51* AB22
D52* AB21
D53* AC26
D54* AD20
D55* AE22
D56* AF23
D57* AC25
D58* AE21
D59* AD21
D60* AC22
D61* AD23
D62* AF22
D63* AC23
DSTBN3* AE25
DSTBP3* AF24
DINV3* AC20
COMP0 R26 71A3 CPU_COMP
COMP1 U26 71A3 CPU_COMP
COMP2 AA1 71A3 CPU_COMP
COMP3 Y1 71B3 CPU_COMP
DPRSTP* E5
DPSLP* B5
DPWR* D24
PWRGOOD D6
SLP* D7
PSI* AE6
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_DSTB_L_N
FSB_DSTB_L_P
FSB_DINV_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_DSTB_L_N
FSB_DSTB_L_P
FSB_DINV_L
Preliminary
CPU_DPRSTP_L
CPU_DPSLP_L
FSB_DPWR_L
CPU_PWRGD
FSB_CPUSLP_L
CPU_PSI_L
BI 14C3 71D3
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
IN
IN
IN
OUT 60C7
14C3 71D3
14C3 71D3
14C3 71D3
14C3 71D3
14C3 71D3
14C3 71D3
14C3 71D3
14C3 71D3
14C3 71D3
14C3 71D3
14C3 71D3
14C3 71D3
14B3 71D3
14B3 71D3
14B3 71D3
14D6 71D3
14D6 71D3
14D6 71D3
14B3 71D3
14B3 71D3
14B3 71D3
14B3 71D3
14B3 71D3
14B3 71D3
14B3 71D3
14B3 71D3
14B3 71D3
14B3 71D3
14B3 71D3
14B3 71D3
14B3 71D3
14B3 71D3
14B3 71D3
14B3 71D3
14D6 71D3
14D6 71D3
14D6 71D3
9B2 14A3 60C7 71B3
14A3 71B3
14A3 71B3
13C7 14A3 71B3
14A3 71B3
PLACEMENT_NOTE (all 4 resistors):
APPLE INC.
R1023
54.9
1%
1/16W
MF-LF
402
2
Place within 12.7mm of CPU
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
1
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
1
27.4
1%
1/16W
MF-LF
402
2
DRAWING NUMBER
NONE
R1021
R1022
1
54.9
1%
1/16W
MF-LF
402
2
CPU FSB
27.4
1%
1/16W
MF-LF
402
2
SHT OF
10
1
R1020
SYNC_MASTER=T18_MLB SYNC_DATE=12/12/2007
REV.
051-7537 A
109
D
C
B
A

D
C
B
A
8 7 6 5 4 3 2 1
VCC
(BR1#)
3 OF 4
VCC
VCCP
B26
VCCA C26
VID0 AD6
VID1 AF5
VID2 AE5
VID3 AF4
VID4 AE3
VID5 AF3
VID6 AE2
VCCSENSE AF7
VSSSENSE AE7
SYNC FROM T18
CHANGE CPU FROM SOCKET TO BGA SYMBOL
Current numbers from Merom for Santa Rosa EMTS, doc #20905.
A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18
OMIT
U1000
PENRYN
FCBGA
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
(CPU CORE POWER)
=PPVCORE_S0_CPU
(CPU IO POWER 1.05V)
=PP1V05_S0_CPU
(CPU INTERNAL PLL POWER 1.5V)
=PP1V5_S0_CPU
CPU_VID
CPU_VID
CPU_VID
CPU_VID
CPU_VID
CPU_VID
CPU_VID
CPU_VCCSENSE_P
CPU_VCCSENSE_N
130 mA
8D7 11B5 12D6
OUT 60C7 71A3
4500 mA (before VCC stable)
2500 mA (after VCC stable)
OUT 60C7 71A3
OUT 60C7 71A3
OUT 60C7 71A3
OUT 60C7 71A3
OUT 60C7 71A3
OUT 60C7 71A3
44 A (SV Design Target)
41 A (SV HFM)
30.4 A (SV LFM)
23 A (LV Design Target)
6D8 8D7 10D5 12B6 13D6
8B7 12B6
R1100
100
1
OUT 60A5 71A3
PLACEMENT_NOTE=Place R1100 within 25.4mm of CPU, no stubs.
PLACEMENT_NOTE=Place R1101 within 25.4mm of CPU, no stubs.
OUT 60A5 71A3
R1101
100
1
=PPVCORE_S0_CPU
1%
1/16W
MF-LF
402
2
1%
1/16W
MF-LF
402
2
8D7 11D6 12D6
FCBGA
4 OF 4
VSS VSS
8 7 6 5 4 3 2 1
A4
A8
A11
A14
A16
A19
A23
AF2
B6
B11
B13
B16
B19
B21
B24
C5
C8
C11
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
P3
B1
U1000
PENRYN
(Socket-P KEY)
P6
P21
P24
R2
R5
R22
R25
B8 T23
Preliminary
OMIT
T1
T4
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25
APPLE INC.
CPU Power & Ground
SYNC_MASTER=T18_MLB SYNC_DATE=12/12/2007
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
SHT OF
11 109
REV.
051-7537 A
D
C
B
A

D
C
B
A
8 7 6 5 4 3 2 1
11D6 11B5 8D7 =PPVCORE_S0_CPU
11B6 8B7 =PP1V5_S0_CPU
13D6 11C6 10D5 8D7 6D8 =PP1V05_S0_CPU
CPU VCore HF and Bulk Decoupling
4X 330UF. 20X 22UF 0805
PLACEMENT_NOTE (C1200-C1219):
Place inside socket cavity on secondary side.
PLACEMENT_NOTE (C1240-C1243):
VCCA (CPU AVdd) DECOUPLING
1x 10uF, 1x 0.01uF
VCCP (CPU I/O) DECOUPLING
1x 330uF, 6x 0.1uF 0402
SYNC FROM T18
REMOVE NO STUFF CAPS C1220 TO C1231
REMOVE C1244 & C1245
CHANGE C1240-C1243 AND C1260 FROM 128S0241(9 MILLI-OHM) TO 128S0231(6 MILLI-OHM)
C1250
1
10uF
20%
6.3V
X5R
2
603
CRITICAL
C1260
1
330UF
20%
2.0V 2
POLY-TANT
D2T-SM2
CRITICAL
1 C1200
22UF
20%
6.3V
2
CERM-X5R
805
CRITICAL
1 C1210
22UF
20%
6.3V
2
CERM-X5R
805
PLACEMENT_NOTE=Place C1260 between CPU & NB.
3
1 C1251
0.01UF
10%
16V
2
CERM
402
1 C1261
0.1UF
20%
10V
2
CERM
402
CRITICAL
1 C1201
22UF
20%
6.3V
2
CERM-X5R
805
CRITICAL
1 C1211
22UF
20%
6.3V
2
CERM-X5R
805
Place on secondary side.
1 C1262
0.1UF
20%
10V
2
CERM
402
CRITICAL
1 C1202
22UF
20%
6.3V
2
CERM-X5R
805
CRITICAL
1 C1212
22UF
20%
6.3V
2
CERM-X5R
805
CRITICAL CRITICAL CRITICAL
1
C1240
1
C1241
1
C1242
330UF
330UF
330UF
20%
20%
20%
3 2 2.0V
POLY-TANT
3 2 2.0V
POLY-TANT
3 2 2.0V
POLY-TANT
D2T-SM2
D2T-SM2
D2T-SM2
1 C1263
0.1UF
20%
10V
2
CERM
402
CRITICAL
1 C1203
22UF
20%
6.3V
2
CERM-X5R
805
CRITICAL
1 C1213
22UF
20%
6.3V
2
CERM-X5R
805
CRITICAL
1
C1243
330UF
20%
3 2 2.0V
POLY-TANT
D2T-SM2
PLACEMENT_NOTE=Place C1281 near CPU pin B26.
1 C1264
0.1UF
20%
10V
2
CERM
402
8 7 6 5 4 3 2 1
CRITICAL
1 C1204
22UF
20%
6.3V
2
CERM-X5R
805
CRITICAL
1 C1214
22UF
20%
6.3V
2
CERM-X5R
805
1 C1265
0.1UF
20%
10V
2
CERM
402
CRITICAL
1 C1205
22UF
20%
6.3V
2
CERM-X5R
805
CRITICAL
1 C1215
22UF
20%
6.3V
2
CERM-X5R
805
Preliminary
1 C1266
0.1UF
20%
10V
2
CERM
402
CRITICAL
1 C1206
22UF
20%
6.3V
2
CERM-X5R
805
CRITICAL
1 C1216
22UF
20%
6.3V
2
CERM-X5R
805
CRITICAL
1 C1207
22UF
20%
6.3V
2
CERM-X5R
805
CRITICAL
1 C1217
22UF
20%
6.3V
2
CERM-X5R
805
CRITICAL
1 C1208
22UF
20%
6.3V
2
CERM-X5R
805
CRITICAL
1 C1218
22UF
20%
6.3V
2
CERM-X5R
805
CRITICAL
1 C1209
22UF
20%
6.3V
2
CERM-X5R
805
CRITICAL
1 C1219
22UF
20%
6.3V
2
CERM-X5R
805
APPLE INC.
CPU Decoupling
SYNC_MASTER=RAYMOND SYNC_DATE=03/31/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
SHT OF
12 109
REV.
051-7537 A
D
C
B
A

D
C
B
A
8 7 6 5 4 3 2 1
71B3 14A3
10B2 IN
CPU_PWRGD
XDP
R1399
1K
1
2
71A3 10C5 BI
71A3 10C6 BI
71A3 10C6 BI
5%
1/16W
MF-LF
402
23C5 19C4
74B3 42D8 21C3
74B3 42D8 21C3
71A3 10C6 10A6 6C7 6C6
8C5 6D8 =PP3V3_S0_XDP
12B6 11C6 10D5 8D7 6D8 =PP1V05_S0_CPU
71A3 10C6
71A3 10C6
71A3 10C6
SYNC FROM T18
CHANGE STANDARD XDP CONNECTOR TO SMALLER ONE 516S0625
RENAME JTAG_MCP_TDO TO JTAG_MCP_TDO_CONN
RENAME XDP_TDO TO XDP_TDO_CONN
21B7 6C5
IN
IN
IN
IN
OUT
BI
BI
OUT
XDP_BPM_L
XDP_BPM_L
XDP_BPM_L
XDP_BPM_L
XDP_BPM_L
XDP_BPM_L
TP_XDP_OBSFN_B0
TP_XDP_OBSFN_B1
TP_XDP_OBSDATA_B0
TP_XDP_OBSDATA_B1
TP_XDP_OBSDATA_B2
TP_XDP_OBSDATA_B3
XDP_PWRGD
PM_LATRIGGER_L
JTAG_MCP_TCK
SMBUS_MCP_0_DATA
SMBUS_MCP_0_CLK
XDP_TCK
XDP
1
R1315
54.9
1%
1/16W
MF-LF
402
2
XDP_OBS20
MCP79-specific pinout
OBSFN_A0
OBSFN_A1
OBSDATA_A0
OBSDATA_A1
OBSDATA_A2
OBSDATA_A3
OBSFN_B0
OBSFN_B1
PWRGD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
SDA
SCL
TCK1
TCK0
NC
516S0625
8 7 6 5 4 3 2 1
OBSFN_C0
OBSFN_C1
OBSDATA_C0
OBSDATA_C1
OBSDATA_C2
OBSDATA_C3
OBSFN_D0
OBSFN_D1
OBSDATA_B0 27 28
OBSDATA_D0
OBSDATA_B1
29 30
OBSDATA_D1
31 32
OBSDATA_B2
OBSDATA_B3
XDP
1 C1300
0.1uF
10%
16V
X5R 2
402
XDP_CONN
CRITICAL
J1300
6-1747769-0
F-ST-SM
64
62
1
3
5
7
9
11
13
15
17
19
21
23
25
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
2
4
6
8
10
12
14
16
18
20
22
24
26
34
36
38
40
42
44
46
48
50
52
54
56
58
60
OBSDATA_D2
OBSDATA_D3
0.1uF
10%
16V
2 X5R
402
JTAG_MCP_TDO_CONN
JTAG_MCP_TRST_L
MCP_DEBUG
MCP_DEBUG
MCP_DEBUG
MCP_DEBUG
JTAG_MCP_TDI
JTAG_MCP_TMS
MCP_DEBUG
MCP_DEBUG
MCP_DEBUG
MCP_DEBUG
IN 6C3
OUT 6C5 21B7
BI
BI
BI
BI
OUT 6C5 21B7 23C5
OUT 6C5 21B7 23C5
BI
BI
BI
BI
19D7 74D3
19D7 74D3
19D7 74D3
19D7 74D3
19D7 74D3
19D7 74D3
19D7 74D3
19D7 74D3
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
FSB_CLK_ITP_P
FSB_CLK_ITP_N
71A3 XDP_CPURST_L
IN
IN
14A3 71B3
14A3 71B3
XDP
R1303
1K
1
2 FSB_CPURST_L
IN 9B2 10D6 14A3 71C3
DBR#/HOOK7
XDP_DBRESET_L
NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.
TDO
XDP_TDO_CONN
OUT 10C6 26A3
IN 6C3
5%
1/16W
MF-LF
402
PLACEMENT_NOTE=Place close to CPU to minimize stub.
TRSTn
XDP_TRST_L
OUT 6C6 6C7 10A6 10C6 71A3
TDI
XDP_TDI
OUT 6C6 10B6 10C6 71A3
TMS
XDP_PRESENT#
XDP
1 C1301
XDP_TMS
OUT 6C6 6C7 10B6 10C6 71A3
Preliminary
SYNC_MASTER=T18_MLB
APPLE INC.
eXtended Debug Port (XDP)
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
051-7537
SHT OF
13
SYNC_DATE=12/12/2007
REV.
109
A
D
C
B
A

D
C
B
A
8 7 6 5 4 3 2 1
24C8 22D3 14A2 9C2 8D7 =PP1V05_S0_MCP_FSB
71B3 40C4 10C6
71C3 10C8
IN
IN
9C1 IN
9C1
9C1
IN
IN
PM_THRMTRIP_L
CPU_FERR_L
=MCP_BSEL
=MCP_BSEL
=MCP_BSEL
R1410
54.9
1%
1/16W
MF-LF
402
1
2
NO STUFF
R1420
1K
5%
1/16W
MF-LF
402
1
2
R1415
62
5%
1/16W
MF-LF
402
1
2
NO STUFF
R1421
1K
5%
1/16W
MF-LF
402
1
2
NO STUFF
1
R1422
1K
5%
1/16W
MF-LF
402
2
R1430
49.9
1%
1/16W
MF-LF
402
1
2
R1431
49.9
1%
1/16W
MF-LF
402
1
2
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
1
R1416
62
5%
1/16W
MF-LF
402
2
1
R1435
49.9
1%
1/16W
MF-LF
402
2
1
R1436
49.9
1%
1/16W
MF-LF
402
2
71D3 10C4
71D3 10C4
71D3 10C4
71D3 10B4
71D3 10B4
71D3 10B4
71D3 10C2
71D3 10C2
71D3 10C2
71D3 10B2
71D3 10B2
71D3 10B2
71D3 10D8
71D3 10D8
71D3 10D8
71D3 10D8
71D3 10D8
71D3 10D8
71D3 10D8
71D3 10D8
71D3 10D8
71D3 10D8
71D3 10D8
71D3 10D8
71D3 10D8
71D3 10D8
71C3 10C8
71C3 10C8
71C3 10C8
71C3 10C8
71C3 10C8
71C3 10C8
71C3 10C8
71C3 10C8
71C3 10C8
71C3 10C8
71C3 10C8
71C3 10C8
71C3 10C8
71C3 10C8
71C3 10C8
71C3 10C8
71C3 10C8
71C3 10C8
71C3 10C8
71C3 10D8
71C3 10C8
71C3 10D8
71C3 10D8
71C3 10D8
71C3 10D8
71C3 10D8
9C4
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
71B3 60C8 40D4 10C5 OUT
71C3 10D6 OUT
71C3 10D6 OUT
71C3 10D6 OUT
FSB_DSTB_L_P
FSB_DSTB_L_N
FSB_DINV_L
FSB_DSTB_L_P
FSB_DSTB_L_N
FSB_DINV_L
FSB_DSTB_L_P
FSB_DSTB_L_N
FSB_DINV_L
FSB_DSTB_L_P
FSB_DSTB_L_N
FSB_DINV_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_A_L
FSB_ADSTB_L
FSB_ADSTB_L
FSB_REQ_L
FSB_REQ_L
FSB_REQ_L
FSB_REQ_L
FSB_REQ_L
71C3 10D6 BI FSB_ADS_L
71C3 10D6 BI FSB_BNR_L
71C3 10D6 9B2 BI FSB_BREQ0_L
71C3 FSB_BREQ1_L
71C3 10D6 BI FSB_DBSY_L
71C3 10D6 BI FSB_DRDY_L
71C3 10C6 BI FSB_HIT_L
71C3 10C6 BI FSB_HITM_L
71C3 10D6 IN FSB_LOCK_L
71C3 10D6 OUT FSB_TRDY_L
(MCP_BSEL)
(MCP_BSEL)
(MCP_BSEL)
270 mA (A01)
71B3 MCP_BCLK_VML_COMP_VDD
71B3 MCP_BCLK_VML_COMP_GND
206 mA
20 mA
29 mA
15 mA
T40 CPU_DSTBP0#
U40 CPU_DSTBN0#
V41 CPU_DBI0#
W39 CPU_DSTBP1#
W37 CPU_DSTBN1#
V35 CPU_DBI1#
N37 CPU_DSTBP2#
L36 CPU_DSTBN2#
N35 CPU_DBI2#
M39 CPU_DSTBP3#
M41 CPU_DSTBN3#
J41 CPU_DBI3#
AC34 CPU_A3#
AE38 CPU_A4#
AE34 CPU_A5#
AC37 CPU_A6#
AE37 CPU_A7#
AE35 CPU_A8#
AB35 CPU_A9#
AF35 CPU_A10#
AG35 CPU_A11#
AG39 CPU_A12#
AE33 CPU_A13#
AG37 CPU_A14#
AG38 CPU_A15#
AG34 CPU_A16#
AN38 CPU_A17#
AL39 CPU_A18#
AG33 CPU_A19#
AL33 CPU_A20#
AJ33 CPU_A21#
AN36 CPU_A22#
AJ35 CPU_A23#
AJ37 CPU_A24#
AJ36 CPU_A25#
AJ38 CPU_A26#
AL37 CPU_A27#
AL34 CPU_A28#
AN37 CPU_A29#
AJ34 CPU_A30#
AL38 CPU_A31#
AL35 CPU_A32#
AN34 CPU_A33#
AR39 CPU_A34#
AN35 CPU_A35#
AE36 CPU_ADSTB0#
AK35 CPU_ADSTB1#
AC38 CPU_REQ0#
AA33 CPU_REQ1#
AC39 CPU_REQ2#
AC33 CPU_REQ3#
AC35 CPU_REQ4#
AD42 CPU_ADS#
AD43 CPU_BNR#
AE40 CPU_BR0#
AL32 CPU_BR1#
AD39 CPU_DBSY#
AD41 CPU_DRDY#
AB42 CPU_HIT#
AD40 CPU_HITM#
AC43 CPU_LOCK#
AE41 CPU_TRDY#
E41 CPU_PECI
AJ41 CPU_PROCHOT#
AG43 CPU_THERMTRIP#
AH40 CPU_FERR#
F42 CPU_BSEL2
D42 CPU_BSEL1
F41 CPU_BSEL0
AC41 CPU_RS0#
AB41 CPU_RS1#
AC42 CPU_RS2#
AG27 +V_DLL_DLCELL_AVDD
AH27 +V_PLL_MCLK
AG28 +V_PLL_FSB
AH28 +V_PLL_CPU
AM39 BCLK_VML_COMP_VDD
AM40 BCLK_VML_COMP_GND
AM43 CPU_COMP_VCC
AM42 CPU_COMP_GND
FSB
CPU_D0# Y43
CPU_D1# W42
CPU_D2# Y40
CPU_D3# W41
CPU_D4# Y39
CPU_D5# V42
CPU_D6# Y41
CPU_D7# Y42
CPU_D8# P42
CPU_D9# U41
CPU_D10# R42
CPU_D11# T39
CPU_D12# T42
CPU_D13# T41
CPU_D14# R41
CPU_D15# T43
CPU_D16# W35
CPU_D17# AA37
CPU_D18# W33
CPU_D19# W34
CPU_D20# AA36
CPU_D21# AA34
CPU_D22# AA38
CPU_D23# AA35
CPU_D24# U38
CPU_D25# U36
CPU_D26# U35
CPU_D27# U33
CPU_D28# U34
CPU_D29# W38
CPU_D30# R33
CPU_D31# U37
CPU_D32# N34
CPU_D33# N33
CPU_D34# R34
CPU_D35# R35
CPU_D36# P35
CPU_D37# R39
CPU_D38# R37
CPU_D39# R38
CPU_D40# L37
CPU_D41# L39
CPU_D42# L38
CPU_D43# N36
CPU_D44# N38
CPU_D45# J39
CPU_D46# J38
CPU_D47# J37
CPU_D48# L42
CPU_D49# M42
CPU_D50# P41
CPU_D51# N41
CPU_D52# N40
CPU_D53# M40
CPU_D54# H40
CPU_D55# K42
CPU_D56# H41
CPU_D57# L41
CPU_D58# H43
CPU_D59# H42
CPU_D60# K41
CPU_D61# J40
CPU_D62# H39
CPU_D63# M43
CPU_BPRI# AA41
CPU_DEFER# AA40
BCLK_OUT_CPU_P G42
BCLK_OUT_CPU_N G41
BCLK_OUT_ITP_P AL43
BCLK_OUT_ITP_N AL42
BCLK_OUT_NB_P AL41
BCLK_OUT_NB_N AK42
BCLK_IN_N AK41
BCLK_IN_P AJ40
CPU_A20M# AF41
CPU_IGNNE# AH39
CPU_INIT# AH42
CPU_INTR AF42
CPU_NMI AG41
CPU_SMI# AH41
CPU_PWRGD AH43
CPU_RESET# H38
CPU_SLP# AM33
CPU_DPSLP# AN33
CPU_DPWR# AM32
CPU_STPCLK# AG42
CPU_DPRSTP# AN32
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT 10D6 71C3
OUT 10D6 71C3
OUT 10B6 71B3
OUT 10B6 71B3
OUT 13C3 71B3
OUT 13B3 71B3
Loop-back clock for delay matching.
OUT 10C8 71C3
OUT 10C8 71C3
OUT 10D6 71C3
OUT 9B2 10B8 71C3
OUT 9B2 10B8 71C3
OUT 10B8 71B3
OUT 9B2 10D6 13B2 71C3
OUT 10A2 71B3
OUT 10B2 71B3
OUT 10B2 71B3
OUT 10B8 71B3
OUT 9B2 10B2 60C7 71B3
8 7 6 5 4 3 2 1
OMIT
U1400
MCP79-TOPO-B
BGA
(1 OF 11)
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_D_L
FSB_BPRI_L
FSB_DEFER_L
Preliminary
CPU_PECI_MCP
CPU_PROCHOT_L
FSB_RS_L
FSB_RS_L
FSB_RS_L
24C2 PP1V05_S0_MCP_PLL_FSB
71B3 MCP_CPU_COMP_VCC
71B3 MCP_CPU_COMP_GND
FSB_CLK_CPU_P
FSB_CLK_CPU_N
FSB_CLK_ITP_P
FSB_CLK_ITP_N
71B3 FSB_CLK_MCP_P
71B3 FSB_CLK_MCP_N
CPU_A20M_L
CPU_IGNNE_L
CPU_INIT_L
CPU_INTR
CPU_NMI
CPU_SMI_L
CPU_PWRGD
FSB_CPURST_L
FSB_CPUSLP_L
CPU_DPSLP_L
FSB_DPWR_L
CPU_STPCLK_L
CPU_DPRSTP_L
10C4 71D3
10C4 71D3
10C4 71D3
10C4 71D3
10C4 71D3
10C4 71D3
10C4 71D3
10C4 71D3
10C4 71D3
10C4 71D3
10C4 71D3
10C4 71D3
10C4 71D3
10C4 71D3
10C4 71D3
10C4 71D3
10C4 71D3
10C4 71D3
10C4 71D3
10B4 71D3
10B4 71D3
10B4 71D3
10B4 71D3
10B4 71D3
10B4 71D3
10B4 71D3
10B4 71D3
10B4 71D3
10B4 71D3
10B4 71D3
10B4 71D3
10B4 71D3
10C2 71D3
10C2 71D3
10C2 71D3
10C2 71D3
10C2 71D3
10C2 71D3
10C2 71D3
10C2 71D3
10C2 71D3
10C2 71D3
10C2 71D3
10C2 71D3
10C2 71D3
10C2 71D3
10C2 71D3
10C2 71D3
10C2 71D3
10C2 71D3
10C2 71D3
10B2 71D3
10B2 71D3
10B2 71D3
10B2 71D3
10B2 71D3
10B2 71D3
10B2 71D3
10B2 71D3
10B2 71D3
10B2 71D3
10B2 71D3
10B2 71D3
10B2 71D3
=PP1V05_S0_MCP_FSB
NO STUFF
1
R1440
150
5%
1/16W
MF-LF
402
2
OUT 10B2 13C7 71B3
8D7 9C2 14B7 22D3 24C8
SYNC_MASTER=T18_MLB
APPLE INC.
MCP CPU Interface
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
051-7537
SHT OF
14
SYNC_DATE=04/04/2008
REV.
109
A
D
C
B
A

D
C
B
A
8 7 6 5 4 3 2 1
72D3 28A5
72D3 28A5
72D3 28A7
72D3 28A7
72D3 28A7
72D3 28A7
72D3 28A5
72D3 28A5
72D3 28B5
72D3 28B7
72D3 28B5
72D3 28B7
72D3 28B7
72D3 28B5
72D3 28B7
72D3 28B5
72D3 28B7
72D3 28B7
72D3 28B7
72D3 28B7
72D3 28B5
72D3 28B5
72D3 28B5
72D3 28B5
72D3 28B5
72D3 28B7
72D3 28B5
72D3 28B5
72D3 28B5
72D3 28B7
72D3 28B7
72D3 28B7
72D3 28C2
72D3 28C4
72D3 28C2
72D3 28C2
72D3 28C2
72D3 28C4
72D3 28C4
72D3 28C4
72D3 28B4
72D3 28B2
72D3 28B4
72D3 28C4
72D3 28B2
72D3 28C2
72D3 28C2
72D3 28B4
72D3 28C4
72D3 28C2
72D3 28C2
72D3 28C4
72D3 28C2
72D3 28C4
72D3 28C2
72D3 28C4
72D3 28C4
72D3 28C4
72D3 28D2
72D3 28D2
72D3 28C2
72D3 28C2
72D3 28C4
72D3 28D4
72C3 28A7
72C3 28B5
72C3 28B7
72C3 28B5
72C3 28C2
72C3 28B4
72C3 28C2
72C3 28C4
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DM
MEM_A_DM
MEM_A_DM
MEM_A_DM
MEM_A_DM
MEM_A_DM
MEM_A_DM
MEM_A_DM
AL8 MDQ0_63
AL9 MDQ0_62
AP9 MDQ0_61
AN9 MDQ0_60
AL6 MDQ0_59
AL7 MDQ0_58
AN6 MDQ0_57
AN7 MDQ0_56
AR6 MDQ0_55
AR7 MDQ0_54
AV6 MDQ0_53
AW5 MDQ0_52
AN10 MDQ0_51
AR5 MDQ0_50
AU6 MDQ0_49
AV5 MDQ0_48
AU7 MDQ0_47
AU8 MDQ0_46
AW9 MDQ0_45
AP11 MDQ0_44
AW6 MDQ0_43
AY5 MDQ0_42
AU9 MDQ0_41
AV9 MDQ0_40
AU11 MDQ0_39
AV11 MDQ0_38
AV13 MDQ0_37
AW13 MDQ0_36
AR11 MDQ0_35
AT11 MDQ0_34
AR14 MDQ0_33
AU13 MDQ0_32
AR26 MDQ0_31
AU25 MDQ0_30
AT27 MDQ0_29
AU27 MDQ0_28
AP25 MDQ0_27
AR25 MDQ0_26
AP27 MDQ0_25
AR27 MDQ0_24
AP29 MDQ0_23
AR29 MDQ0_22
AP31 MDQ0_21
AR31 MDQ0_20
AV27 MDQ0_19
AN29 MDQ0_18
AV29 MDQ0_17
AN31 MDQ0_16
AU31 MDQ0_15
AR33 MDQ0_14
AV37 MDQ0_13
AW37 MDQ0_12
AT31 MDQ0_11
AV31 MDQ0_10
AT37 MDQ0_9
AU37 MDQ0_8
AW39 MDQ0_7
AV39 MDQ0_6
AR37 MDQ0_5
AR38 MDQ0_4
AV38 MDQ0_3
AW38 MDQ0_2
AR35 MDQ0_1
AP35 MDQ0_0
AN5 MDQM0_7
AU5 MDQM0_6
AR10 MDQM0_5
AN13 MDQM0_4
AN27 MDQM0_3
AW29 MDQM0_2
AV35 MDQM0_1
AR34 MDQM0_0
OMIT
U1400
MCP79-TOPO-B
BGA
(2 OF 11)
MEMORY PARTITION 0
MDQS0_7_P AL10
MDQS0_7_N AL11
MDQS0_6_P AR8
MDQS0_6_N AR9
MDQS0_5_P AW7
MDQS0_5_N AW8
MDQS0_4_P AP13
MDQS0_4_N AR13
MDQS0_3_P AV25
MDQS0_3_N AW25
MDQS0_2_P AU30
MDQS0_2_N AU29
MDQS0_1_P AT35
MDQS0_1_N AU35
MDQS0_0_P AU39
MDQS0_0_N AT39
MRAS0# AV17
MCAS0# AP17
MWE0# AR17
MBA0_2 AP23
MBA0_1 AP19
MBA0_0 AW17
MA0_14 AR23
MA0_13 AU15
MA0_12 AN23
MA0_11 AW21
MA0_10 AN19
MA0_9 AV21
MA0_8 AR22
MA0_7 AU21
MA0_6 AP21
MA0_5 AR21
MA0_4 AN21
MA0_3 AV19
MA0_2 AU19
MA0_1 AT19
MA0_0 AR19
MEMORY
CONTROL
0A
MCLK0A_2_P
MCLK0A_2_N
AW33
AV33
MCLK0A_1_P BA24
MCLK0A_1_N AY24
MCLK0A_0_P BB20
MCLK0A_0_N BC20
MCS0A_1# AT15
MCS0A_0# AR18
MODT0A_1 AP15
MODT0A_0 AV15
MCKE0A_1 AU23
MCKE0A_0 AT23
MEM_A_DQS_P
MEM_A_DQS_N
MEM_A_DQS_P
MEM_A_DQS_N
MEM_A_DQS_P
MEM_A_DQS_N
MEM_A_DQS_P
MEM_A_DQS_N
MEM_A_DQS_P
MEM_A_DQS_N
MEM_A_DQS_P
MEM_A_DQS_N
MEM_A_DQS_P
MEM_A_DQS_N
MEM_A_DQS_P
MEM_A_DQS_N
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
MEM_A_BA
MEM_A_BA
MEM_A_BA
MEM_A_A
MEM_A_A
MEM_A_A
MEM_A_A
MEM_A_A
MEM_A_A
MEM_A_A
MEM_A_A
MEM_A_A
MEM_A_A
MEM_A_A
MEM_A_A
MEM_A_A
MEM_A_A
MEM_A_A
TP_MEM_A_CLK2P
TP_MEM_A_CLK2N
MEM_A_CLK_P
MEM_A_CLK_N
MEM_A_CLK_P
MEM_A_CLK_N
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
28A5 72C3
28A5 72C3
28B7 72C3
28B7 72C3
28B5 72C3
28B5 72C3
28B7 72C3
28B7 72C3
28C4 72C3
28C4 72C3
28B2 72C3
28B2 72C3
28C4 72C3
28C4 72C3
28C2 72C3
28C2 72C3
OUT 28C5 72D3
OUT 28C7 72D3
OUT 28C7 72D3
OUT 28C7 72D3
OUT 28C5 72D3
OUT 28C7 72D3
OUT 28C5 72D3
OUT 28C7 72D3
OUT 28C7 72D3
OUT 28C5 72D3
OUT 28C7 72D3
OUT 28C7 72D3
OUT 28C7 72D3
OUT 28C5 72D3
OUT 28C5 72D3
OUT 28C7 72D3
OUT 28C5 72D3
OUT 28C7 72D3
OUT 28C5 72D3
OUT 28C7 72D3
OUT 28C5 72D3
OUT 28C5 72D3
OUT 28C5 72D3
OUT 28C7 72D3
OUT 28C7 72D3
OUT 28C7 72D3
OUT 28C5 72D3
OUT 28C5 72D3
OUT 28C5 72D3
OUT 28D5 72D3
OUT 28D7 72D3
8 7 6 5 4 3 2 1
72B3 29A5
72B3 29A5
72B3 29A7
72B3 29A7
72B3 29A5
72B3 29A7
72B3 29A5
72B3 29A7
72B3 29B7
72B3 29B7
72B3 29B7
72B3 29B5
72B3 29B5
72B3 29B5
72B3 29B7
72B3 29B5
72B3 29B7
72B3 29B7
72B3 29B7
72B3 29B5
72B3 29B5
72B3 29B5
72B3 29B7
72B3 29B5
72B3 29B7
72B3 29B5
72B3 29B7
72B3 29B5
72B3 29B7
72B3 29B5
72B3 29B5
72B3 29B7
72B3 29B4
72B3 29B2
72B3 29C2
72B3 29B4
72B3 29B2
72B3 29B4
72B3 29C2
72B3 29C4
72B3 29C2
72B3 29C4
72B3 29C2
72B3 29C4
72B3 29C4
72B3 29C2
72B3 29C4
72B3 29C2
72B3 29C4
72B3 29C4
72B3 29C4
72B3 29C2
72B3 29C2
72B3 29C4
72B3 29C2
72B3 29C2
72B3 29C2
72B3 29C4
72B3 29D2
72B3 29D2
72B3 29C4
72B3 29C2
72B3 29D4
72B3 29C4
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
72A3 29A7 OUT MEM_B_DM
72A3 29B5 OUT MEM_B_DM
72B3 29B7 OUT MEM_B_DM
72B3 29B5 OUT MEM_B_DM
72B3 29B4 OUT MEM_B_DM
72B3 29C2 OUT MEM_B_DM
72B3 29C2 OUT MEM_B_DM
72B3 29C4 OUT MEM_B_DM
AT4 MDQ1_63
AT3 MDQ1_62
AV2 MDQ1_61
AV3 MDQ1_60
AR4 MDQ1_59
AR3 MDQ1_58
AU2 MDQ1_57
AU3 MDQ1_56
AY4 MDQ1_55
AY3 MDQ1_54
BB3 MDQ1_53
BC3 MDQ1_52
AW4 MDQ1_51
AW3 MDQ1_50
BA3 MDQ1_49
BB2 MDQ1_48
BB5 MDQ1_47
BA5 MDQ1_46
BA8 MDQ1_45
BC8 MDQ1_44
BB4 MDQ1_43
BC4 MDQ1_42
BA7 MDQ1_41
AY8 MDQ1_40
BA9 MDQ1_39
BB10 MDQ1_38
BB12 MDQ1_37
AW12 MDQ1_36
BB8 MDQ1_35
BB9 MDQ1_34
AY12 MDQ1_33
BA12 MDQ1_32
BC32 MDQ1_31
AW32 MDQ1_30
BA35 MDQ1_29
AY36 MDQ1_28
BA32 MDQ1_27
BB32 MDQ1_26
BA34 MDQ1_25
AY35 MDQ1_24
BC36 MDQ1_23
AW36 MDQ1_22
BA39 MDQ1_21
AY40 MDQ1_20
BA36 MDQ1_19
BB36 MDQ1_18
BA38 MDQ1_17
AY39 MDQ1_16
BB40 MDQ1_15
AW40 MDQ1_14
AV42 MDQ1_13
AV41 MDQ1_12
BA40 MDQ1_11
BC40 MDQ1_10
AW42 MDQ1_9
AW41 MDQ1_8
AT40 MDQ1_7
AT41 MDQ1_6
AP41 MDQ1_5
AN40 MDQ1_4
AU40 MDQ1_3
AU41 MDQ1_2
AR41 MDQ1_1
AP42 MDQ1_0
AT5 MDQM1_7
BA2 MDQM1_6
AY7 MDQM1_5
BA11 MDQM1_4
BB34 MDQM1_3
BB38 MDQM1_2
AY43 MDQM1_1
AR42 MDQM1_0
OMIT
U1400
MCP79-TOPO-B
BGA
(3 OF 11)
MEMORY PARTITION 1
MDQS1_7_P AT2
MDQS1_7_N AT1
MDQS1_6_P AY2
MDQS1_6_N AY1
MDQS1_5_P BB6
MDQS1_5_N BA6
MDQS1_4_P BA10
MDQS1_4_N AY11
MDQS1_3_P BB33
MDQS1_3_N BA33
MDQS1_2_P BB37
MDQS1_2_N BA37
MDQS1_1_P BA43
MDQS1_1_N AY42
MDQS1_0_P AT42
MDQS1_0_N AT43
MRAS1# AW16
MCAS1# BA15
MWE1# BA16
MBA1_2 BB29
MBA1_1 BB18
MBA1_0 BB17
MA1_14 BA29
MA1_13 BA14
MA1_12 AW28
MA1_11 BC28
MA1_10 BA17
MA1_9 BB28
MA1_8 AY28
MA1_7 BA28
MA1_6 AY27
MA1_5 BA27
MA1_4 BA26
MA1_3 BB26
MA1_2 BA25
MA1_1 BB25
MA1_0 BA18
MEMORY
CONTROL
1A
MCLK1A_2_P
MCLK1A_2_N
BA42
BB42
MCLK1A_1_P BB22
MCLK1A_1_N BA22
MCLK1A_0_P BA19
MCLK1A_0_N AY19
MCS1A_1# BB14
MCS1A_0# BB16
MODT1A_1 BB13
MODT1A_0 AY15
MCKE1A_1 AY31
MCKE1A_0 BB30
MEM_B_DQS_P
MEM_B_DQS_N
MEM_B_DQS_P
MEM_B_DQS_N
MEM_B_DQS_P
MEM_B_DQS_N
MEM_B_DQS_P
MEM_B_DQS_N
MEM_B_DQS_P
MEM_B_DQS_N
MEM_B_DQS_P
MEM_B_DQS_N
MEM_B_DQS_P
MEM_B_DQS_N
MEM_B_DQS_P
MEM_B_DQS_N
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
MEM_B_BA
MEM_B_BA
MEM_B_BA
MEM_B_A
MEM_B_A
MEM_B_A
MEM_B_A
MEM_B_A
MEM_B_A
MEM_B_A
MEM_B_A
MEM_B_A
MEM_B_A
MEM_B_A
MEM_B_A
MEM_B_A
MEM_B_A
MEM_B_A
TP_MEM_B_CLK2P
TP_MEM_B_CLK2N
MEM_B_CLK_P
MEM_B_CLK_N
MEM_B_CLK_P
MEM_B_CLK_N
Preliminary
MEM_A_CS_L
MEM_A_CS_L
MEM_A_ODT
MEM_A_ODT
MEM_A_CKE
MEM_A_CKE
MEM_B_CS_L
MEM_B_CS_L
MEM_B_ODT
MEM_B_ODT
MEM_B_CKE
MEM_B_CKE
APPLE INC.
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT 29C5 72B3
OUT 29C7 72B3
OUT 29C7 72B3
OUT 29C7 72B3
OUT 29C5 72B3
OUT 29C7 72B3
OUT 29C5 72B3
OUT 29C7 72B3
OUT 29C7 72B3
OUT 29C5 72B3
OUT 29C7 72B3
OUT 29C7 72B3
OUT 29C7 72B3
OUT 29C5 72B3
OUT 29C5 72B3
OUT 29C7 72B3
OUT 29C5 72B3
OUT 29C7 72B3
OUT 29C5 72B3
OUT 29C7 72B3
OUT 29C5 72B3
OUT 29C5 72B3
OUT 29C5 72B3
OUT 29C7 72B3
OUT 29C7 72B3
OUT 29C7 72B3
OUT 29C5 72B3
OUT 29C5 72B3
OUT 29C5 72B3
OUT 29D5 72B3
OUT 29D7 72B3
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
29A5 72A3
29A5 72A3
29B7 72A3
29B7 72A3
29B5 72A3
29B5 72A3
29B7 72A3
29B7 72A3
29B2 72A3
29B2 72A3
29C4 72A3
29C4 72A3
29C4 72A3
29C4 72A3
29C2 72A3
29C2 72A3
MCP Memory Interface
SYNC_MASTER=T18_MLB SYNC_DATE=04/04/2008
DRAWING NUMBER
NONE
SHT OF
15
REV.
051-7537 A
109
D
C
B
A

D
C
B
A
8 7 6 5 4 3 2 1
24C8 16C3 8B7 =PP1V8R1V5_S0_MCP_MEM
R1610
40.2
1%
1/16W
MF-LF
402
1
2
R1611
40.2
1%
1/16W
MF-LF
402
1
2
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
TP_MEM_A_CLK5P
TP_MEM_A_CLK5N
TP_MEM_A_CLK4P
TP_MEM_A_CLK4N
TP_MEM_A_CLK3P
TP_MEM_A_CLK3N
TP_MEM_A_CS_L
TP_MEM_A_CS_L
TP_MEM_A_ODT
TP_MEM_A_ODT
TP_MEM_A_CKE
TP_MEM_A_CKE
24B2 PP1V05_S0_MCP_PLL_CORE
87 mA (A01)
72A3 MCP_MEM_COMP_VDD
72A3 MCP_MEM_COMP_GND
17 mA
12 mA
19 mA
39 mA
AU33 MCLK0B_2_P
AU34 MCLK0B_2_N
BB24 MCLK0B_1_P
BC24 MCLK0B_1_N
BA21 MCLK0B_0_P
BB21 MCLK0B_0_N
AU17 MCS0B_0#
AR15 MCS0B_1#
AN17 MODT0B_0
AN15 MODT0B_1
AV23 MCKE0B_0
AN25 MCKE0B_1
T27 +V_PLL_XREF_XS
U28 +V_PLL_DP
U27 +V_PLL_CORE
T28 +V_VPLL
AN41 MEM_COMP_VDD
AM41 MEM_COMP_GND
AA22 GND1
AP12 GND2
G30 GND3
P10 GND4
T10 GND5
T6 GND6
V10 GND7
V34 GND8
W5 GND9
AA39 GND10
AB22 GND11
AB7 GND12
AD22 GND13
AE20 GND14
AF24 GND15
AG24 GND16
AH35 GND17
AK7 GND18
AM28 GND19
AT25 GND20
AP30 GND21
AR36 GND22
AU10 GND23
F28 GND24
BC21 GND25
AY9 GND26
BC9 GND27
D34 GND28
F24 GND29
G32 GND30
H31 GND31
K7 GND32
M38 GND33
M5 GND34
M6 GND35
M7 GND36
M9 GND37
N39 GND38
N8 GND39
P33 GND40
P34 GND41
P37 GND42
P4 GND43
P40 GND44
P7 GND45
R36 GND46
R40 GND47
R43 GND48
R5 GND49
T18 GND50
T20 GND51
AK11 GND52
T24 GND53
T26 GND54
U1400
MCP79-TOPO-B
BGA
(4 OF 11)
MEMORY CONTROL 0B
OMIT
MEMORY CONTROL 1B
MCLK1B_2_P BA41
MCLK1B_2_N BB41
8 7 6 5 4 3 2 1
MCLK1B_1_P AY23
MCLK1B_1_N BA23
MCLK1B_0_P BA20
MCLK1B_0_N AY20
MCS1B_0# BC16
MCS1B_1# BA13
MODT1B_0 AY16
MODT1B_1 BC13
MCKE1B_0 BA30
MCKE1B_1 BA31
MRESET0# AY32
+VDD_MEM1 AM17
+VDD_MEM2 AM19
+VDD_MEM3 AM21
+VDD_MEM4 AM23
+VDD_MEM5 AM25
+VDD_MEM6 AM27
+VDD_MEM7 AM29
+VDD_MEM8 AN16
+VDD_MEM9 BC29
+VDD_MEM10 AN20
+VDD_MEM11 AN24
+VDD_MEM12 AT17
+VDD_MEM13 AP16
+VDD_MEM14 AN22
+VDD_MEM15 AP20
+VDD_MEM16 AP24
+VDD_MEM17 AV16
+VDD_MEM18 AR16
+VDD_MEM19 AR20
+VDD_MEM20 AR24
+VDD_MEM21 AW15
+VDD_MEM22 AP22
+VDD_MEM23 AP18
+VDD_MEM24 AU16
+VDD_MEM25 AN18
+VDD_MEM26 AU24
+VDD_MEM27 AT21
+VDD_MEM28 AY29
+VDD_MEM29 AV24
+VDD_MEM30 AU20
+VDD_MEM31 AU22
+VDD_MEM32 AW27
+VDD_MEM33 BC17
+VDD_MEM34 AV20
+VDD_MEM35 AY17
+VDD_MEM36 AY18
+VDD_MEM37 AM15
+VDD_MEM38 AU18
+VDD_MEM39 AY25
+VDD_MEM40 AY26
+VDD_MEM41 AW19
+VDD_MEM42 AW24
+VDD_MEM43 BC25
+VDD_MEM44 AL30
+VDD_MEM45 AM31
GND55 T33
GND56 T34
GND57 T35
GND58 T37
GND59 T38
GND60 T7
GND61 T9
GND62 U18
GND63 U20
GND64 U22
TP_MEM_B_CLK5P
TP_MEM_B_CLK5N
TP_MEM_B_CLK4P
TP_MEM_B_CLK4N
TP_MEM_B_CLK3P
TP_MEM_B_CLK3N
TP_MEM_B_CS_L
TP_MEM_B_CS_L
TP_MEM_B_ODT
TP_MEM_B_ODT
TP_MEM_B_CKE
TP_MEM_B_CKE
MCP_MEM_RESET_L
TP or NC for DDR2.
OUT 30B6
=PP1V8R1V5_S0_MCP_MEM
8B7 16C7 24C8
4771 mA (A01, DDR3)
Preliminary
SYNC_MASTER=T18_MLB
APPLE INC.
MCP Memory Misc
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
051-7537
SYNC_DATE=04/04/2008
SHT OF
16 109
REV.
A
D
C
B
A

D
C
B
A
8 7 6 5 4 3 2 1
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
9D6
31D7
31D7 9C6
9D6
9D6
9C6
9C6
9C4
9C4
31C7 23C5 7D5
73D3 31C7 7D5
73D3 31C7 7D5
9D6
9D6
9C6
9C6
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
=PEG_D2R_P
=PEG_D2R_N
=PEG_D2R_P
=PEG_D2R_N
=PEG_D2R_P
=PEG_D2R_N
=PEG_D2R_P
=PEG_D2R_N
=PEG_D2R_P
=PEG_D2R_N
=PEG_D2R_P
=PEG_D2R_N
=PEG_D2R_P
=PEG_D2R_N
=PEG_D2R_P
=PEG_D2R_N
=PEG_D2R_P
=PEG_D2R_N
=PEG_D2R_P
=PEG_D2R_N
=PEG_D2R_P
=PEG_D2R_N
=PEG_D2R_P
=PEG_D2R_N
=PEG_D2R_P
=PEG_D2R_N
=PEG_D2R_P
=PEG_D2R_N
=PEG_D2R_P
=PEG_D2R_N
=PEG_D2R_P
=PEG_D2R_N
PEG_PRSNT_L
MINI_CLKREQ_L
PCIE_MINI_PRSNT_L
FW_CLKREQ_L
PCIE_FW_PRSNT_L
EXCARD_CLKREQ_L
PCIE_EXCARD_PRSNT_L
9C6 TP_PE4_CLKREQ_L
9C6 TP_PE4_PRSNT_L
TP_MCP_GPIO_17
GMUX_JTAG_TCK_L
TP_MCP_GPIO_18
GMUX_JTAG_TDO
PCIE_WAKE_L
PCIE_MINI_D2R_P
PCIE_MINI_D2R_N
PCIE_FW_D2R_P
PCIE_FW_D2R_N
PCIE_EXCARD_D2R_P
PCIE_EXCARD_D2R_N
9B6 TP_PCIE_PE4_D2RP
9B6 TP_PCIE_PE4_D2RN
8A6 =PP1V05_S0_MCP_PEX_DVDD0
57 mA (A01, DVDD0 & 1)
8A6 =PP1V05_S0_MCP_PEX_DVDD1
24C2 PP1V05_S0_MCP_PLL_PEX
84 mA (A01)
NO STUFF
1
R1710
2.37K
1%
1/16W
MF-LF
402
2
PLACEMENT_NOTE=Place within 12.7mm of U1400
F7 PE0_RX0_P
E7 PE0_RX0_N
D7 PE0_RX1_P
C7 PE0_RX1_N
E6 PE0_RX2_P
F6 PE0_RX2_N
E5 PE0_RX3_P
F5 PE0_RX3_N
E4 PE0_RX4_P
E3 PE0_RX4_N
C3 PE0_RX5_P
D3 PE0_RX5_N
G5 PE0_RX6_P
H5 PE0_RX6_N
J7 PE0_RX7_P
J6 PE0_RX7_N
J5 PE0_RX8_P
J4 PE0_RX8_N
L11 PE0_RX9_P
L10 PE0_RX9_N
L9 PE0_RX10_P
L8 PE0_RX10_N
L7 PE0_RX11_P
L6 PE0_RX11_N
N11 PE0_RX12_P
N10 PE0_RX12_N
N9 PE0_RX13_P
P9 PE0_RX13_N
N7 PE0_RX14_P
N6 PE0_RX14_N
N5 PE0_RX15_P
N4 PE0_RX15_N
PE0_REFCLK_P E11
Int PU
C9 PE0_PRSNT_16#
PE0_REFCLK_N D11
D5
Int PU
PEB_CLKREQ#/GPIO_49
D9 PEB_PRSNT# Int PU
E8
Int PU
PEC_CLKREQ#/GPIO_50
C10 PEC_PRSNT# Int PU
M15
Int PU
PED_CLKREQ#/GPIO_51
B10 PED_PRSNT# Int PU
Int PU
L16 PEE_CLKREQ#/GPIO_16
L18 PEE_PRSNT#/GPIO_46
M16
Int PU
Int PU
PEF_CLKREQ#/GPIO_17
M18 PEF_PRSNT#/GPIO_47
M17
Int PU
Int PU
PEG_CLKREQ#/GPIO_18
M19 PEG_PRSNT#/GPIO_48
Int PU
F17 PE_WAKE# Int PU (S5)
K9 PE1_RX0_P
J9 PE1_RX0_N
H9 PE1_RX1_P
G9 PE1_RX1_N
F9 PE1_RX2_P
E9 PE1_RX2_N
H7 PE1_RX3_P
G7 PE1_RX3_N
T17 +DVDD0_PEX1
W19 +DVDD0_PEX2
U17 +DVDD0_PEX3
V19 +DVDD0_PEX4
W16 +DVDD0_PEX5
W17 +DVDD0_PEX6
W18 +DVDD0_PEX7
U16 +DVDD0_PEX8
T19 +DVDD1_PEX1
U19 +DVDD1_PEX2
T16 +V_PLL_PEX
A11 PEX_CLK_COMP
OMIT
U1400
MCP79-TOPO-B
BGA
(5 OF 11)
PCI EXPRESS
PE0_TX0_P C5
PE0_TX0_N D4
PE0_TX1_P C4
PE0_TX1_N B4
PE0_TX2_P A4
PE0_TX2_N A3
PE0_TX3_P B3
PE0_TX3_N B2
PE0_TX4_P C1
PE0_TX4_N D1
PE0_TX5_P D2
PE0_TX5_N E1
PE0_TX6_P E2
PE0_TX6_N F2
PE0_TX7_P F3
PE0_TX7_N F4
PE0_TX8_P G3
PE0_TX8_N H4
PE0_TX9_P H3
PE0_TX9_N H2
PE0_TX10_P H1
PE0_TX10_N J1
PE0_TX11_P J2
PE0_TX11_N J3
PE0_TX12_P K2
PE0_TX12_N K3
PE0_TX13_P L4
PE0_TX13_N L3
PE0_TX14_P M4
PE0_TX14_N M3
PE0_TX15_P M2
PE0_TX15_N M1
PE1_REFCLK_P G11
PE1_REFCLK_N F11
PE2_REFCLK_P J11
PE2_REFCLK_N J10
PE3_REFCLK_P G13
PE3_REFCLK_N F13
PE4_REFCLK_P J13
PE4_REFCLK_N H13
PE5_REFCLK_P L14
PE5_REFCLK_N K14
PE6_REFCLK_P N14
PE6_REFCLK_N M14
PEX_RST0# K11
PE1_TX0_P D8
PE1_TX0_N C8
PE1_TX1_P B8
PE1_TX1_N A8
PE1_TX2_P A7
PE1_TX2_N B7
PE1_TX3_P B6
PE1_TX3_N C6
+AVDD0_PEX1 Y12
+AVDD0_PEX2 AA12
+AVDD0_PEX3 AB12
+AVDD0_PEX4 M12
+AVDD0_PEX5 P12
+AVDD0_PEX6 R12
+AVDD0_PEX7 N12
+AVDD0_PEX8 T12
+AVDD0_PEX9 U12
+AVDD0_PEX10 AC12
+AVDD0_PEX11 AD12
+AVDD0_PEX12 V12
+AVDD0_PEX13 W12
8 7 6 5 4 3 2 1
+AVDD1_PEX1 M13
+AVDD1_PEX2 N13
+AVDD1_PEX3 P13
=PEG_R2D_C_P
=PEG_R2D_C_N
=PEG_R2D_C_P
=PEG_R2D_C_N
=PEG_R2D_C_P
=PEG_R2D_C_N
=PEG_R2D_C_P
=PEG_R2D_C_N
=PEG_R2D_C_P
=PEG_R2D_C_N
=PEG_R2D_C_P
=PEG_R2D_C_N
=PEG_R2D_C_P
=PEG_R2D_C_N
=PEG_R2D_C_P
=PEG_R2D_C_N
=PEG_R2D_C_P
=PEG_R2D_C_N
=PEG_R2D_C_P
=PEG_R2D_C_N
=PEG_R2D_C_P
=PEG_R2D_C_N
=PEG_R2D_C_P
=PEG_R2D_C_N
=PEG_R2D_C_P
=PEG_R2D_C_N
=PEG_R2D_C_P
=PEG_R2D_C_N
=PEG_R2D_C_P
=PEG_R2D_C_N
=PEG_R2D_C_P
=PEG_R2D_C_N
PEG_CLK100M_P
PEG_CLK100M_N
PCIE_CLK100M_MINI_P
PCIE_CLK100M_MINI_N
PCIE_CLK100M_FW_P
PCIE_CLK100M_FW_N
PCIE_CLK100M_EXCARD_P
PCIE_CLK100M_EXCARD_N
TP_PCIE_CLK100M_PE4P
TP_PCIE_CLK100M_PE4N
TP_PCIE_CLK100M_PE5P
TP_PCIE_CLK100M_PE5N
TP_PCIE_CLK100M_PE6P
TP_PCIE_CLK100M_PE6N
PCIE_RESET_L
PCIE_MINI_R2D_C_P
PCIE_MINI_R2D_C_N
PCIE_FW_R2D_C_P
PCIE_FW_R2D_C_N
PCIE_EXCARD_R2D_C_P
PCIE_EXCARD_R2D_C_N
TP_PCIE_PE4_R2D_CP
TP_PCIE_PE4_R2D_CN
Preliminary
73C3 MCP_PEX_CLK_COMP
=PP1V05_S0_MCP_PEX_AVDD0
8A6
206 mA (A01, AVDD0 & 1)
=PP1V05_S0_MCP_PEX_AVDD1
If PE0 interface is not used, ground DVDD0_PEX and AVDD0_PEX.
If PE1 interface is not used, ground DVDD1_PEX and AVDD1_PEX.
OUT 9D6
OUT 9D6
OUT 9D6
OUT 9D6
OUT 9D6
OUT 9D6
OUT 9D6
OUT 9D6
OUT 9D6
OUT 9D6
OUT 9D6
OUT 9D6
OUT 9D6
OUT 9D6
OUT 9D6
OUT 9D6
OUT 9D6
OUT 9D6
OUT 9D6
OUT 9D6
OUT 9D6
OUT 9D6
OUT 9D6
OUT 9D6
OUT 9D6
OUT 9D6
OUT 9D6
OUT 9D6
OUT 9D6
OUT 9D6
OUT 9D6
OUT 9D6
OUT 9D6
OUT 9D6
OUT 31C5 73D3
OUT 31C5 73D3
OUT 9C6
OUT 9C6
OUT 9C6
OUT 9C6
9B6
9B6
OUT 26C4
OUT 31C5 73D3
OUT 31C5 73D3
OUT 9D6
OUT 9D6
OUT 9C6
OUT 9C6
9B6
9B6
8A6
SYNC_MASTER=T18_MLB
APPLE INC.
MCP PCIe Interfaces
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
051-7537
SYNC_DATE=04/04/2008
SHT OF
17 109
REV.
A
D
C
B
A

D
C
B
A
MCP Signal
=MCP_HDMI_TXC_P/N
=MCP_HDMI_TXD_P/N
=MCP_HDMI_TXD_P/N
=MCP_HDMI_TXD_P/N
=MCP_HDMI_DDC_CLK
8 7 6 5 4 3 2 1
TMDS/HDMI
TMDS_IG_TXC_P/N
TMDS_IG_TXD_P/N
TMDS_IG_TXD_P/N
TMDS_IG_TXD_P/N
TMDS_IG_DDC_CLK
=MCP_HDMI_DDC_DATA
TMDS_IG_DDC_DATA
=MCP_HDMI_HPD TMDS_IG_HPD
DP_IG_AUX_CH_P/N
TP_DP_IG_AUX_CHP/N
24B6 24A6 18D3 8B1 =PP3V3_ENET_MCP_RMGT
20C1 8A3 =PP3V3_S5_MCP_GPIO
Interface Mode
DisplayPort
NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used.
NOTE: 20K pull-down required on DP_HPD_DET.
NOTE: 1K pull-down required on DP_IG_AUX_CH_N if DP is used.
DP_IG_ML_P/N
DP_IG_ML_P/N
DP_IG_ML_P/N
DP_IG_ML_P/N
DP_IG_DDC_CLK
DP_IG_DDC_DATA
DP_IG_HPD
DP_IG_AUX_CH_P/N
NOTE: HDMI port requires level-shifting. IFP interface can
be used to provide HDMI or dual-channel TMDS without
level-shifters.
LVDS: Power +VDD_IFPx at 1.8V
Dual-channel TMDS: Power +VDD_IFPx at 3.3V
R1810
49.9
1%
1/16W
MF-LF
402
1
2
R1811
49.9
1%
1/16W
MF-LF
402
1
2
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
41C3
R1820
47K
5%
1/16W
MF-LF
402
1
2
BI
75D3 33C1
75D3 33C1
75D3 33C1
75D3 33B1
75D3 33C1
75D3 33B1
9C4
9C4
9C4
9D4
9D4
9D4
9D4
67A5
9B4
67D3
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
IN
OUT
IN
IN
IN
ENET_RXD
ENET_RXD
ENET_RXD
ENET_RXD
ENET_CLK125M_RXCLK
ENET_RX_CTRL
=MCP_MII_RXER
=MCP_MII_COL
=MCP_MII_CRS
TP_ENET_INTR_L
24A6 PP1V05_ENET_MCP_PLL_MAC
5 mA (A01)
75D3 MCP_MII_COMP_VDD
75D3 MCP_MII_COMP_GND
TP_MCP_RGB_DAC_RSET
TP_MCP_RGB_DAC_VREF
MCP_TV_DAC_RSET
MCP_TV_DAC_VREF
MCP_CLK27M_XTALIN
MCP_CLK27M_XTALOUT
LPCPLUS_GPIO
DP_IG_CA_DET
70A7 69A8 OUT LVDS_IG_BKL_PWM
70C8 70B7 OUT LVDS_IG_BKL_ON
66B8 OUT LVDS_IG_PANEL_PWR
67D3 OUT =MCP_HDMI_TXC_P
67D3 OUT =MCP_HDMI_TXC_N
67D3 OUT =MCP_HDMI_TXD_P
67D3 OUT =MCP_HDMI_TXD_N
67D3 OUT =MCP_HDMI_TXD_P
67D3 OUT =MCP_HDMI_TXD_N
67D3 OUT =MCP_HDMI_TXD_P
67D3 OUT =MCP_HDMI_TXD_N
73B3 67C7 OUT DP_IG_AUX_CH_P
73B3 67B7 OUT DP_IG_AUX_CH_N
=DVI_HPD_GMUX_INT
=MCP_HDMI_HPD
25D7 8A7 =PP3V3R1V8_S0_MCP_IFP_VDD
190 mA (A01, 1.8V)
25B5 PP3V3_S0_MCP_VPLL
16 mA (A01)
25D7 8B7 =PP1V05_S0_MCP_HDMI_VDD
73B3 25C7 OUT
95 mA (A01)
MCP_HDMI_RSET
73B3 25C7 OUT MCP_HDMI_VPROBE
GPIOs 57-59 (if LCD panel is used):
C23 RGMII_RXD0
B23 RGMII_RXD1
E24 RGMII_RXD2
A24 RGMII_RXD3
A23 RGMII_RXC/MII_RXCLK
C22 RGMII_RXCTL/MII_RXDV
F23 MII_RXER/GPIO_36
B26 MII_COL/GPIO_20/MSMB_DATA
B22 MII_CRS/GPIO_21/MSMB_CLK
J22 RGMII_INTR/GPIO_35
T23 +V_DUAL_MACPLL
C27 MII_COMP_VDD
B27 MII_COMP_GND
C39 RGB_DAC_RSET
B38 RGB_DAC_VREF
E36 TV_DAC_RSET
A35 TV_DAC_VREF
C38 XTALIN_TV
D38 XTALOUT_TV
E16 GPIO_6/FERR*/IGPU_GPIO_6
B15 GPIO_7/NFERR*/IGPU_GPIO_7
G39 LCD_BKL_CTL/GPIO_57
E37 LCD_BKL_ON/GPIO_59
F40 LCD_PANEL_PWR/GPIO_58
D35 HDMI_TXC_P/ML0_LANE3_P
E35 HDMI_TXC_N/ML0_LANE3_N
G35 HDMI_TXD0_P/ML0_LANE2_P
F35 HDMI_TXD0_N/ML0_LANE2_N
F33 HDMI_TXD1_P/ML0_LANE1_P
G33 HDMI_TXD1_N/ML0_LANE1_N
J33 HDMI_TXD2_P/ML0_LANE0_P
H33 HDMI_TXD2_N/ML0_LANE0_N
D43 DP_AUX_CH0_P
C43 DP_AUX_CH0_N
C31 HPLUG_DET2/GPIO_22
F31 HPLUG_DET3
M27 +VDD_IFPA
M26 +VDD_IFPB
M28 +V_PLL_IFPAB
M29 +V_PLL_HDMI
T25 +VDD_HDMI
J31 HDMI_RSET
J30 HDMI_VPROBE
In MCP79 these pins have undocumented internal
pull-ups (~10K to 3.3V S0). To ensure pins are low
by default, pull-downs (1K or stronger) must be used.
=DVI_HPD_GMUX_INT:
(See below)
(See below)
8 mA
8 mA
Alias to DVI_HPD for systems using IFP for DVI.
Alias to GMUX_INT for systems with GMUX.
Alias to HPLUG_DET2 for other systems.
Pull-down (20k) required in all cases.
OMIT
U1400
MCP79-TOPO-B
BGA
(6 OF 11)
LAN
DACS
+3.3V_DUAL_RMGT1 J24
+3.3V_DUAL_RMGT2 K24
+V_DUAL_RMGT1 U23
+V_DUAL_RMGT2 V23
MII_VREF E28
RGMII_TXD0 B24
RGMII_TXD1 C24
RGMII_TXD2 C25
RGMII_TXD3 D25
RGMII_TXC/MII_TXCLK D24
RGMII_TXCTL/MII_TXEN C26
RGMII_MDC D21
RGMII_MDIO C21
RGMII_PWRDWN/GPIO_37 G23
BUF_25MHZ E23
MII_RESET# J23
+V_RGB_DAC J32
+V_TV_DAC K32
DDC_CLK0 B31
DDC_DATA0 A31
RGB_DAC_RED B39
RGB_DAC_GREEN A39
RGB_DAC_BLUE B40
RGB_DAC_HSYNC A40
RGB_DAC_VSYNC
TV / Component
A41
C / Pr TV_DAC_RED A36
Y / Y TV_DAC_GREEN B36
Comp / Pb TV_DAC_BLUE C36
FLAT PANEL
TV_DAC_HSYNC/GPIO_44 D36
TV_DAC_VSYNC/GPIO_45 C37
IFPA_TXC_P B35
IFPA_TXC_N C35
IFPA_TXD0_P B32
IFPA_TXD0_N A32
IFPA_TXD1_P D32
IFPA_TXD1_N C32
IFPA_TXD2_P D33
IFPA_TXD2_N C33
IFPA_TXD3_P B34
IFPA_TXD3_N C34
IFPB_TXC_P L31
IFPB_TXC_N K31
IFPB_TXD4_P J29
IFPB_TXD4_N H29
IFPB_TXD5_P L29
IFPB_TXD5_N K29
IFPB_TXD6_P L30
IFPB_TXD6_N K30
IFPB_TXD7_P N30
IFPB_TXD7_N M30
DDC_CLK2/GPIO_23 C30
DDC_DATA2/GPIO_24 B30
DDC_CLK3 D31
DDC_DATA3 E31
IFPAB_RSET E32
IFPAB_VPROBE G31
8 7 6 5 4 3 2 1
RGB ONLY
=PP3V3_ENET_MCP_RMGT
=PP1V05_ENET_MCP_RMGT
MCP_MII_VREF
ENET_TXD
ENET_TXD
ENET_TXD
ENET_TXD
ENET_CLK125M_TXCLK
ENET_TX_CTRL
ENET_MDC
ENET_MDIO
TP_ENET_PWRDWN_L
MCP_CLK25M_BUF0_R
ENET_RESET_L
103 mA
103 mA
CRT_IG_R_C_PR
CRT_IG_G_Y_Y
CRT_IG_B_COMP_PB
CRT_IG_HSYNC
CRT_IG_VSYNC
1
R1850
10K
5%
1/16W
MF-LF
402
2
PP3V3_S0_MCP_DAC
MCP_DDC_CLK0
MCP_DDC_DATA0
TP_MCP_RGB_RED
TP_MCP_RGB_GREEN
TP_MCP_RGB_BLUE
TP_MCP_RGB_HSYNC
TP_MCP_RGB_VSYNC
LVDS_IG_A_CLK_P
LVDS_IG_A_CLK_N
LVDS_IG_A_DATA_P
LVDS_IG_A_DATA_N
LVDS_IG_A_DATA_P
LVDS_IG_A_DATA_N
LVDS_IG_A_DATA_P
LVDS_IG_A_DATA_N
LVDS_IG_A_DATA_P
LVDS_IG_A_DATA_N
LVDS_IG_B_CLK_P
LVDS_IG_B_CLK_N
LVDS_IG_B_DATA_P
LVDS_IG_B_DATA_N
LVDS_IG_B_DATA_P
LVDS_IG_B_DATA_N
LVDS_IG_B_DATA_P
LVDS_IG_B_DATA_N
LVDS_IG_B_DATA_P
LVDS_IG_B_DATA_N
LVDS_IG_DDC_CLK
LVDS_IG_DDC_DATA
=MCP_HDMI_DDC_CLK
=MCP_HDMI_DDC_DATA
MCP_IFPAB_RSET
MCP_IFPAB_VPROBE
8B1 18C7 24A6 24B6
83 mA (A01)
8B1 24C6
131 mA (A01)
IN 24A4
OUT 33C6 75C3
OUT 33C6 75C3
OUT 33C6 75C3
OUT 33B6 75C3
OUT 33C8 75D3
OUT 33B6 75C3
OUT 33B6 75D3
BI
OUT 34A5 75D3
OUT 33B7 75C3
25D2
206 mA (A01)
OUT 9D4
OUT 9D4
OUT 9D4
OUT 9D4
OUT 9D4
OUT 66B3 73B3
OUT 66B3 73B3
OUT 7C7 66C2 73B3
OUT 7C7 66C2 73B3
OUT 7C7 66C2 73B3
OUT 7C7 66C2 73B3
OUT 7C7 66C2 73B3
OUT 7C7 66C2 73B3
OUT 9D4
OUT 9D4
OUT 9C4
OUT 9C4
OUT 9C4
OUT 9C4
OUT 9C4
OUT 9C4
OUT 9C4
OUT 9C4
OUT 9C4
OUT 9C4
OUT 7C7 66C5
BI
OUT 67D3
BI
33B6 75D3
7C7 66B5
67D3
OUT 25C6 73A3
OUT 25C6 73A3
R1860
100K
5%
1/16W
MF-LF
402
1
2
R1861
100K
5%
1/16W
MF-LF
402
2
NOTE: All Apple products set strap to
MII, RGMII products will enable
feature via software. This
avoids a leakage issue since
MCP79 requires a S5 pull-up.
RGB DAC Disable:
TV DAC Disable:
WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases
1
=PP3V3_S0_MCP_GPIO
Preliminary
APPLE INC.
Network Interface Select
Interface
RGMII
MII 0
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
ENET_TXD
Okay to float all RGB_DAC signals.
DDC_CLK0/DDC_DATA0 pull-ups still required.
Okay to float all TV_DAC signals.
Okay to float XTALIN_TV and XTALOUT_TV.
DDC_CLK0/DDC_DATA0 pull-ups still required.
MCP Ethernet & Graphics
SYNC_MASTER=T18_MLB
8C5 19D1 21A4
1
051-7537
SYNC_DATE=04/04/2008
SHT OF
18 109
REV.
A
D
C
B
A

D
C
B
A
8 7 6 5 4 3 2 1
74D3 19D2 PCI_REQ0_L
74D3 19D2 PCI_REQ1_L
19D2 OUT CRTMUX_SEL_TV_L
52C7 OUT AUD_IPHS_SWITCH_EN
19D2 IN MCP_RS232_SIN_L
74D3 13C3
74D3 13C3
74D3 13C3
74D3 13C3
74D3 13C3
74D3 13C3
74D3 13C3
74D3 13C3
BI
BI
BI
BI
BI
BI
BI
BI
T2 PCI_REQ0#
V9 PCI_REQ1#/FANRPM2
T3 PCI_REQ2#/GPIO_40/RS232_DSR#
U9 PCI_REQ3#/GPIO_38/RS232_CTS#
T4 PCI_REQ4#/GPIO_52/RS232_SIN#
MCP_DEBUG
AC3 PCI_AD0
PCI_CBE0# AA3
TP_PCI_C_BE_L
MCP_DEBUG
AE10 PCI_AD1
PCI_CBE1# AA6
TP_PCI_C_BE_L
MCP_DEBUG
AC4 PCI_AD2
PCI_CBE2# AA11
TP_PCI_C_BE_L
MCP_DEBUG
AE11 PCI_AD3
PCI_CBE3# W10
TP_PCI_C_BE_L
MCP_DEBUG
AB3 PCI_AD4
MCP_DEBUG
AC6 PCI_AD5
PCI_DEVSEL# AA9
TP_PCI_DEVSEL_L
MCP_DEBUG
AB2 PCI_AD6
PCI_FRAME# Y4
TP_PCI_FRAME_L
MCP_DEBUG
AC7 PCI_AD7
PCI_IRDY# AA10
TP_PCI_IRDY_L
TP_PCI_AD
AC8 PCI_AD8
PCI_PAR Y1
TP_PCI_PAR
TP_PCI_AD AA2 PCI_AD9
PCI_PERR#/GPIO_43/RS232_DCD# AB9
TP_PCI_PERR_L
TP_PCI_AD
AC9 PCI_AD10
PCI_SERR# AA7
TP_PCI_SERR_L
TP_PCI_AD
AC10 PCI_AD11
PCI_STOP# Y2
TP_PCI_STOP_L
TP_PCI_AD
TP_PCI_AD
TP_PCI_AD
AC11
AA1
AA5
PCI_AD12
PCI_AD13
PCI_AD14
PCI_PME#/GPIO_30
Int PU (S5)
T1
PM_LATRIGGER_L
TP_PCI_AD
Y5 PCI_AD15
TP_PCI_AD
W3 PCI_AD16
PCI_RESET0# R10
MEM_VTT_EN_R
TP_PCI_AD
W6 PCI_AD17
PCI_RESET1# R11
TP_PCI_RESET1_L
TP_PCI_AD
W4 PCI_AD18
TP_PCI_AD
W7 PCI_AD19
TP_PCI_AD
TP_PCI_AD
TP_PCI_AD
TP_PCI_AD
V3
W8
V2
W9
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_CLK0
PCI_CLK1
PCI_CLK2
R6
R7
R8
TP_PCI_CLK0
TP_PCI_CLK1
74C3 PCI_CLK33M_MCP_R
TP_PCI_AD
U3 PCI_AD24
TP_PCI_AD
W11 PCI_AD25
TP_PCI_AD
U2 PCI_AD26
TP_PCI_AD
U5 PCI_AD27
TP_PCI_AD
U1 PCI_AD28
TP_PCI_AD
U6 PCI_AD29
PCI_CLKIN R9
74C3 PCI_CLK33M_MCP
TP_PCI_AD
T5 PCI_AD30
TP_PCI_AD
U7 PCI_AD31
U24 GND65
U26 GND66
U39 GND67
U4 GND68
U8 GND69
V16 GND70
V17 GND71
V18 GND72
V20 GND73
V22 GND74
V24 GND75
V26 GND76
V27 GND77
V28 GND78
V33 GND79
V37 GND80
V4 GND81
V40 GND82
V7 GND83
W20 GND84
W22 GND85
W24 GND86
W36 GND87
W40 GND88
W43 GND89
Y16 GND90
Y17 GND91
Y18 GND92
Y19 GND93
Y20 GND94
Y22 GND95
Y24 GND96
Y25 GND97
OMIT
U1400
MCP79-TOPO-B
BGA
(7 OF 11)
LPC PCI
TP_PCI_INTW_L
P2 PCI_INTW#
TP_PCI_INTX_L
TP_PCI_INTY_L
TP_PCI_INTZ_L
N3
N2
N1
PCI_INTX#
PCI_INTY#
PCI_INTZ#
LPC_FRAME#
LPC_PWRDWN#/GPIO_54/EXT_NMI#
AD4
AE12
41C1 LPC_FRAME_R_L
LPC_PWRDWN_L
R1960 22 1 2
5% 1/16W MF-LF 402
LPC_FRAME_L OUT
OUT
39C8 41D5 74C3
39C5 41D3
LPC_RESET0# AE5
LPC_RESET_L
OUT 26D4 74C3
41D5 39C5 IN
9C4 IN
TP_PCI_TRDY_L
PM_CLKRUN_L
FW_PME_L
TP_LPC_DRQ0_L
Y3
AD11
AE2
AE1
PCI_TRDY#
PCI_CLKRUN#/GPIO_42
LPC_DRQ1#/GPIO_19 Int PU
LPC_DRQ0# Int PU
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
AD3
AD2
AD1
AD5
LPC_AD_R
LPC_AD_R
LPC_AD_R
LPC_AD_R
R1950
R1951
R1952
R1953
22
22
22
22
1
1
1
1
2
2
2
2
5%
5%
5%
5%
1/16W
1/16W
1/16W
1/16W
MF-LF
MF-LF
MF-LF
MF-LF
402
402
402
402
LPC_AD
LPC_AD
LPC_AD
LPC_AD
BI
BI
BI
BI
39C8 41D5 74C3
39C8 41D5 74C3
39C8 41D3 74C3
39C8 41D3 74C3
41D3 39C8 BI LPC_SERIRQ
AE6 LPC_SERIRQ Int PU
LPC_CLK0 AE9
LPC_CLK33M_SMC_R
OUT 26C4 74C3
GND
PCI_GNT0# R3
PCI_GNT1#/FANCTL2 U10
PCI_GNT2#/GPIO_41/RS232_DTR# R4
PCI_GNT3#/GPIO_39/RS232_RTS# U11
PCI_GNT4#/GPIO_53/RS232_SOUT# P3
GND98 Y26
GND99 Y27
GND100 AB18
GND101 H34
GND102 AB20
GND103 AB21
GND104 AB23
GND105 AB24
GND106 AB25
GND107 AB26
GND108 AB27
GND109 AB28
GND110 AB34
GND111 AB37
GND112 AB4
GND113 AB40
GND114 AC22
GND115 AC36
GND116 AC40
GND117 AB33
GND118 AC5
GND119 AD16
GND120 AD17
GND121 AD18
GND122 AD19
GND123 AD20
GND124 AD24
GND125 AD25
GND126 AD26
GND127 AD27
GND128 AD28
GND129 AD33
GND130 AD34
1
TP_PCI_GNT0_L
TP_PCI_GNT1_L
GMUX_JTAG_TMS
GMUX_JTAG_TDI
MCP_RS232_SOUT_L
R1961
10K
5%
1/16W
MF-LF
402
2
8 7 6 5 4 3 2 1
OUT 9C4
OUT 9C4
OUT 19D2
OUT 13B6 23C5
OUT 26C4
R1910
22
5%
1/16W
MF-LF
402
2
PLACEMENT_NOTE=Place close to pin R8
Strap for Boot ROM Selection (See HDA_SDOUT)
1
19D4 MCP_RS232_SOUT_L
74D3 19D7 PCI_REQ0_L
74D3 19D7 PCI_REQ1_L
19D7 CRTMUX_SEL_TV_L
19D7 MCP_RS232_SIN_L
Preliminary
SYNC_MASTER=T18_MLB
APPLE INC.
21A4 18C1 8C5 =PP3V3_S0_MCP_GPIO
R1989 8.2K 1 2
R1990 8.2K 1 2
R1991 8.2K 1 2
R1992 8.2K 1 2
R1994 8.2K 1 2
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
5%
5%
5%
5%
1/16W
1/16W
1/16W
1/16W
MCP PCI & LPC
SHT OF
19
MF-LF
MF-LF
MF-LF
MF-LF
402
402
402
5% 1/16W MF-LF 402
402
SYNC_DATE=04/04/2008
REV.
051-7537 A
109
D
C
B
A

D
C
B
A
8 7 6 5 4 3 2 1
73A3 36A3 OUT
73A3 36A3 OUT
73A3 36A3
73A3 36A3
IN
IN
73A3 36C2 OUT
73A3 36C2 OUT
73A3 36B2
73A3 36B2
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
IN
IN
84 mA (A01)
8A6 =PP1V05_S0_MCP_SATA_DVDD0
43 mA (A01, DVDD0 & 1)
8A6 =PP1V05_S0_MCP_SATA_AVDD0
127 mA (A01, AVDD0 & 1)
1
SATA_HDD_R2D_C_P
SATA_HDD_R2D_C_N
SATA_HDD_D2R_N
SATA_HDD_D2R_P
SATA_ODD_R2D_C_P
SATA_ODD_R2D_C_N
SATA_ODD_D2R_N
SATA_ODD_D2R_P
TP_SATA_C_R2D_CP
TP_SATA_C_R2D_CN
TP_SATA_C_D2RN
TP_SATA_C_D2RP
TP_SATA_D_R2D_CP
TP_SATA_D_R2D_CN
TP_SATA_D_D2RN
TP_SATA_D_D2RP
TP_SATA_E_R2D_CP
TP_SATA_E_R2D_CN
TP_SATA_E_D2RN
TP_SATA_E_D2RP
TP_SATA_F_R2D_CP
TP_SATA_F_R2D_CN
TP_SATA_F_D2RN
TP_SATA_F_D2RP
TP_MCP_SATALED_L
24B2 PP1V05_S0_MCP_PLL_SATA
8A6 =PP1V05_S0_MCP_SATA_DVDD1
8A6 =PP1V05_S0_MCP_SATA_AVDD1
73A3 MCP_SATA_TERMP
R2010
2.49K
1%
1/16W
MF-LF
402
2
AJ7 SATA_A0_TX_P
AJ6 SATA_A0_TX_N
AJ5 SATA_A0_RX_N
AJ4 SATA_A0_RX_P
AJ11 SATA_A1_TX_P
AJ10 SATA_A1_TX_N
AJ9 SATA_A1_RX_N
AK9 SATA_A1_RX_P
AK2 SATA_B0_TX_P
AJ3 SATA_B0_TX_N
AJ2 SATA_B0_RX_N
AJ1 SATA_B0_RX_P
AM4 SATA_B1_TX_P
AL3 SATA_B1_TX_N
AL4 SATA_B1_RX_N
AK3 SATA_B1_RX_P
AN1 SATA_C0_TX_P
AM1 SATA_C0_TX_N
AM2 SATA_C0_RX_N
AM3 SATA_C0_RX_P
AP3 SATA_C1_TX_P
AP2 SATA_C1_TX_N
AN3 SATA_C1_RX_N
AN2 SATA_C1_RX_P
E12 SATA_LED#
AE16 +V_PLL_SATA
AF19 +DVDD0_SATA1
AG16 +DVDD0_SATA2
AG17 +DVDD0_SATA3
AG19 +DVDD0_SATA4
AH17 +DVDD1_SATA1
AH19 +DVDD1_SATA2
AJ12 +AVDD0_SATA1
AN11 +AVDD0_SATA2
AK12 +AVDD0_SATA3
AK13 +AVDD0_SATA4
AL12 +AVDD0_SATA5
AM11 +AVDD0_SATA6
AM12 +AVDD0_SATA7
AN12 +AVDD0_SATA8
AL13 +AVDD0_SATA9
AN14 +AVDD1_SATA1
AL14 +AVDD1_SATA2
AM13 +AVDD1_SATA3
AM14 +AVDD1_SATA4
AE3 SATA_TERMP
OMIT
U1400
MCP79-TOPO-B
BGA
(8 OF 11)
SATA
USB
USB0_P C29
USB0_N D29
USB1_P C28
USB1_N D28
USB2_P A28
USB2_N B28
USB3_P F29
USB3_N G29
USB4_P K27
USB4_N L27
USB5_P J26
USB5_N J27
USB6_P F27
USB6_N G27
USB7_P D27
USB7_N E27
USB8_P K25
USB8_N L25
USB9_P H25
USB9_N J25
USB10_P F25
USB10_N G25
USB11_P K23
USB11_N L23
USB_OC0#/GPIO_25 L21
USB_OC1#/GPIO_26 K21
USB_OC2#/GPIO_27/MGPIO J21
USB_OC3#/GPIO_28/MGPIO H21
+V_PLL_USB L28
USB_RBIAS_GND A27
If all SATA_Ax & Bx pins are not used, ground DVDD0_SATA and AVDD0_SATA.
If all SATA_Cx pins are not used, ground DVDD1_SATA and AVDD1_SATA.
8 7 6 5 4 3 2 1
GND131 AD35
GND132 AD37
GND133 AD38
GND134 AE22
GND135 AE24
GND136 AE39
GND137 AE4
GND138 AD6
GND139 AF16
GND140 AF17
GND141 AF18
GND142 AF20
GND143 AF22
GND144 AF26
GND145 AF27
GND146 AF28
GND147 AF33
GND148 AF34
GND149 AF37
GND150 AF40
GND151 AG18
GND152 AG20
GND153 AG22
GND154 AG26
GND155 AG36
GND156 AG40
GND157 AH18
GND158 AH20
GND159 AH22
GND160 AH24
External A
USB_EXTA_P
USB_EXTA_N
AirPort (PCIe Mini-Card)
USB_MINI_P
USB_MINI_N
External D
USB_EXTD_P
USB_EXTD_N
Camera
IR
USB_CAMERA_P
USB_CAMERA_N
USB_IR_P
USB_IR_N
Geyser Trackpad/Keyboard
USB_TPAD_P
USB_TPAD_N
Bluetooth
USB_BT_P
USB_BT_N
External B
USB_EXTB_P
USB_EXTB_N
ExpressCard
USB_EXCARD_P
USB_EXCARD_N
External C
USB_EXTC_P
USB_EXTC_N
TP_USB_10P
TP_USB_10N
TP_USB_11P
TP_USB_11N
PP3V3_S0_MCP_PLL_USB
74B3 MCP_USB_RBIAS_GND
19 mA (A01)
R2060
806
1%
1/16W
MF-LF
402
1
2
BI 37A8 74C3
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
37A8 74C3
9B6
9B6
9B6
9B6
31B5 74C3
31B5 74C3
38C7 74B3
38C7 74B3
47B8 74B3
47B8 74B3
31B5 74B3
31B5 74B3
37A4 74B3
37A4 74B3
9B6
9B6
9B6
9B6
R2050
8.2K
5%
1/16W
MF-LF
402
1
2
1
R2051
8.2K
5%
1/16W
MF-LF
402
2
R2052
8.2K
5%
1/16W
MF-LF
402
1
2
1
=PP3V3_S5_MCP_GPIO
R2053
8.2K
5%
1/16W
MF-LF
402
2
USB_EXTA_OC_L
USB_EXTB_OC_L
USB_EXTC_OC_L
EXCARD_OC_L
Preliminary
24B4
APPLE INC.
IN 37C7
IN 37C7
IN
IN 40B4
SYNC_MASTER=T18_MLB
8A3 18C7
MCP SATA & USB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
SHT OF
20
SYNC_DATE=04/04/2008
REV.
051-7537 A
109
D
C
B
A

D
C
B
A
C2170
10PF
5%
50V
CERM
402
1
2
8 7 6 5 4 3 2 1
24A8 21D3 8B5 =PP3V3R1V5_S0_MCP_HDA
26D4 22A5 7C3 PP3V3_G3_RTC
R2120
49.9K
1%
1/16W
MF-LF
402
1
2
HDA Output Caps
For EMI Reduction on HDA interface
1
2
C2172
10PF
5%
50V
CERM
402
1
2
C2171
10PF
5%
50V
CERM
402
1
2
HDA_SDOUT_R
HDA_BIT_CLK_R
HDA_RST_R_L
HDA_SYNC_R
C2173
10PF
5%
50V
CERM
402
1
R2110
49.9
1%
1/16W
MF-LF
402
2
1
R2121
49.9K
1%
1/16W
MF-LF
402
2
21D4 74A3
21D4 74B3
21D4 74A3
21C4 74A3
74A3 51C7
40B2 39D5 34B7
39C5 23C5
39B8 23C5
71B3 60D8
39C8 23C5
26A1 23C5
23C5 13C3 6C5
23C5 13C3 6C5
IN
41B1 OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
IN
G15 HDA_SDATA_IN0
Int PD
J14 HDA_SDATA_IN1/GPIO_2/PS2_KB_CLK
Int PD
J15 HDA_SDATA_IN2/GPIO_3/PS2_KB_DATA
Int PD
A15 HDA_PULLDN_COMP
AE18 +V_PLL_NV_H
AE17 +V_PLL_SP_SPREF
L24 GPIO_1/PWRDN_OK/SPI_CS1
L26 GPIO_12/SUS_STAT#/ACCLMTR
K13 A20GATE Int PU
L13 KBRDRSTIN# Int PU
C19 SIO_PME# Int PU (S5)
C18 EXT_SMI/GPIO_32# Int PU (S5)
B20 INTRUDER#
M25 LID# Int PU (S5)
M24 LLB# Int PU (S5)
M22 CPU_DPRSLPVR
C20 RTC_RST#
D20 PWRGD_SB
E20 PS_PWRGD
HDA_SDATA_OUT F15
HDA_BITCLK E15
HDA_RESET# K15
HDA_SYNC L15
THERM_DIODE_P B11
THERM_DIODE_N C11
MCP_VID0/GPIO_13 L20
MCP_VID1/GPIO_14 M20
MCP_VID2/GPIO_15 M21
SPKR C13
SMB_CLK0 L19
SMB_DATA0 K19
SMB_CLK1/MSMB_CLK G21
SMB_DATA1/MSMB_DATA F21
SMB_ALERT#/GPIO_64 M23
FANRPM0/GPIO_60 B12
FANCTL0/GPIO_61 A12
FANRPM1/GPIO_63 D12
FANCTL1/GPIO_62 C12
26A5 IN MCP_CPU_VLD
C17 CPU_VLD
CPUVDD_EN D17
MCP_CPUVDD_EN
OUT 26A8
13C3 6C5
13B6 6C5
IN
26C7 OUT
IN
26C7 OUT
(MXM_OK for MXM systems)
24A2 PP1V05_S0_MCP_PLL_NV
37 mA (A01)
R2150
10K
5%
1/16W
MF-LF
402
1
2
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
39C8
26A5
6C4
26B7
26C7
HDA_SDIN0
TP_MLB_RAM_SIZE
TP_MLB_RAM_VENDOR
74A3 MCP_HDA_PULLDN_COMP
=SPI_CS1_R_L_USE_MLB
SMC_ADAPTER_EN
TP_SB_A20GATE
TP_MCP_KBDRSTIN_L
SMC_WAKE_SCI_L
SMC_RUNTIME_SCI_L
SM_INTRUDER_L
23C5 TP_MCP_LID_L
39B8 23B5 IN PM_BATLOW_L
PM_DPRSLPVR
PM_PWRBTN_L
PM_SYSRST_DEBOUNCE_L
RTC_RST_L
PM_RSMRST_L
MCP_PS_PWRGD
JTAG_MCP_TDI
JTAG_MCP_TDO
JTAG_MCP_TMS
JTAG_MCP_TRST_L
JTAG_MCP_TCK
MCP_CLK25M_XTALIN
MCP_CLK25M_XTALOUT
RTC_CLK32K_XTALIN
RTC_CLK32K_XTALOUT
20 mA
17 mA
1
R2151
100K
5%
1/16W
MF-LF
402
2
C16 PWRBTN# Int PU (S5)
D16 RSTBTN# Int PU
E19 JTAG_TDI Int PU
F19 JTAG_TDO
J19 JTAG_TMS Int PU
J18 JTAG_TRST#
G19 JTAG_TCK
A16 XTALIN
B16 XTALOUT
A19 XTALIN_RTC
B19 XTALOUT_RTC
1
R2140
10K
5%
1/16W
MF-LF
402
2
1
R2141
10K
5%
1/16W
MF-LF
402
2
1
R2142
10K
5%
1/16W
MF-LF
402
2
OMIT
U1400
MCP79-TOPO-B
BGA
(9 OF 11)
HDA
MISC
+V_DUAL_HDA1 J16
+V_DUAL_HDA2 K16
HDA_DOCK_EN#/GPIO_4/PS2_MS_CLK K17
HDA_DOCK_RST#/GPIO_5/PS2_MS_DATA L17
1
R2143
10K
5%
1/16W
MF-LF
402
2
1
R2147
100K
5%
1/16W
MF-LF
402
2
(MGPIO2)
(MGPIO3)
=PP3V3_S0_MCP_GPIO
MCP_GPIO_4
AUD_I2C_INT_L
MEM_EVENT_L
SMC_IG_THROTTLE_L
ARB_DETECT
SLP_S3# G17
SLP_RMGT# J17
SLP_S5# H17
SPI_CS0/GPIO_10 C14
SPI_CLK/GPIO_11 D13
SPI_DI/GPIO_8 C15
SPI_DO/GPIO_9 B14
SUS_CLK/GPIO_34 B18
BUF_SIO_CLK AE7
TEST_MODE_EN K22
PKG_TEST L22
IN 21A4 52C7
OUT 7C3 34B7 39C5 41A5 64D5 68D8
OUT 9D1
OUT 7C3 39C5 40A2 64C8
OUT 45C5 77D3
OUT 45B5 77D3
OUT 21A3 61A8
OUT 21A3 61A8
OUT 21A3 61A8
OUT 13B6 42D8 74B3
BI
OUT 42C8 74B3
BI
OUT 21A3 31D5 34C7
IN 21A4 28A5 29A5 39B8
8 7 6 5 4 3 2 1
1
=PP3V3R1V5_S0_MCP_HDA
R2160
8.2K
5%
1/16W
MF-LF
402
2
74A3 21A7 HDA_SDOUT_R
74B3 21A7 HDA_BIT_CLK_R
74A3 21A7 HDA_RST_R_L
74A3 21A7 HDA_SYNC_R
1
MCP_GPIO_4
AUD_I2C_INT_L
PM_SLP_S3_L
PM_SLP_RMGT_L
PM_SLP_S4_L
MCP_THMDIODE_P
MCP_THMDIODE_N
MCP_VID
MCP_VID
MCP_VID
MCP_SPKR
SMBUS_MCP_0_CLK
SMBUS_MCP_0_DATA
SMBUS_MCP_1_CLK
SMBUS_MCP_1_DATA
AP_PWR_EN
MEM_EVENT_L
ODD_PWR_EN_L
SMC_IG_THROTTLE_L
ARB_DETECT
SPI_CS0_R_L
SPI_CLK_R
SPI_MISO
SPI_MOSI_R
PM_CLK32K_SUSCLK_R
TP_MCP_BUF_SIO_CLK
MCP_TEST_MODE_EN
R2163
10K
5%
1/16W
MF-LF
402
2
1
R2155
22K
5%
1/16W
MF-LF
402
2
1
R2156
22K
5%
1/16W
MF-LF
402
2
7 mA (A01)
R2171
22
1 2
5%
1/16W
MF-LF
402
R2173
22
1 2
5%
1/16W
MF-LF
402
2
OUT 36C6
13B6 42D8 74B3
42C8 74B3
IN 21A4 40D4
OUT 41B7 74A3
OUT 41A5 41C8 74A3
IN 41A5 41B7 74A3
OUT 41A5 41C7 74A3
OUT 26B4 74A3
1
R2170
22
1 2
R2190
1K
1%
1/16W
MF-LF
402
2
R2154
100K
5%
1/16W
MF-LF
402
1
5%
1/16W
MF-LF
402
R2172
22
1 2
5%
1/16W
MF-LF
402
MCP_VID
MCP_VID
MCP_VID
1
R2157
22K
5%
1/16W
MF-LF
402
2
HDA_SDOUT
HDA_BIT_CLK
HDA_RST_L
HDA_SYNC
OUT 51C7 74A3
OUT 51C7 74B3
OUT 51B7 74A3
OUT 51C7 74A3
=PP3V3_S0_MCP
BOOT_MODE_SAFE
1
R2180
10K
5%
1/16W
MF-LF
402
2
OUT 23B5
BOOT_MODE_USER
1
R2181
10K
5%
1/16W
MF-LF
402
2
USER mode: Normal
SAFE mode: For ROMSIP
recovery
Connects to SMC for
automatic recovery.
Preliminary
8C5 18C1 19D1
21C3
21C3 52C7
21B3 28A5 29A5 39B8
21B3 40D4
21B3
8B5 21D8 24A8
21A4
21A4
=PP3V3_S3_MCP_GPIO
AP_PWR_EN
21B3 31D5 34C7
21C3 61A8
21C3 61A8
21C3 61A8
8D3
8C5 22B3 24B8
APPLE INC.
I/F HDA_SDOUT
LPC
PCI
SPI0
SPI1
SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L
R1961 and R2160 selects SPI0 ROM by
default, LPC+ debug card pulls
LPC_FRAME# high for SPI1 ROM override.
NOTE: MCP79 does not support FWH, only
LPC ROMs. So Apple designs will
not use LPC for BootROM override.
BUF_SIO_CLK Frequency
Frequency
42 MHz 0
25 MHz
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
24 MHz
14.31818 MHz
Frequency
BIOS Boot Select
NOTE: MCP79 rev A01 does not support
SPI1 option. Rev B01 will.
31 MHz
1 MHz
DRAWING NUMBER
NONE
SPI_DO
0
1
1
HDA_SYNC
SPI Frequency Select
NOTE: Straps not provided on this page.
0
0
1
1
LPC_FRAME#
1
0
MCP HDA & MISC
0
1
0
1
SPI_CLK
SYNC_MASTER=T18_MLB SYNC_DATE=06/26/2008
0
1
0
1
SHT OF
21
REV.
051-7537 A
109
D
C
B
A

D
C
B
A
8 7 6 5 4 3 2 1
OMIT
U1400
MCP79-TOPO-B
BGA
(11 OF 11)
AH26 GND161 GND253 AV40
AH33 GND162 GND254 BA1
AH34 GND163 GND255 BA4
AH37 GND164 GND256 AW31
AH38 GND165 GND257 AY6
AJ39 GND166 GND258 L35
AJ8 GND167 GND259 BC33
AK10 GND168 GND260 BC37
AK33 GND169 GND261 BC41
AK34 GND170 GND262 AY14
AK37 GND171 GND263 BC5
AK4 GND172 GND264 C2
AK40 GND173 GND265 D10
AL36 GND174 GND266 D14
AL40 GND175 GND267 D15
AL5 GND176 GND268 D18
AM10 GND177 GND269 D19
AM16 GND178 GND270 D22
AM18 GND179 GND271 D23
AM20 GND180 GND272 D26
AM22 GND181 GND273 D30
AM24 GND182 GND274 D37
AM26 GND183 GND275 D6
AM30 GND184 GND276 E13
AM34 GND185 GND277 E17
AM35 GND186 GND278 E21
AM37 GND187 GND279 E25
AM38 GND188 GND280 E29
AM5 GND189 GND281 E33
AM6 GND190 GND282 F12
AM7 GND191 GND283 F16
AM9 GND192 GND284 F32
AP26 GND193 GND285 F8
AN28 GND194 GND286 G10
AN30 GND195 GND287 G12
AN39 GND196 GND288 G14
AN4 GND197 GND289 G16
Y7 GND198 GND290 BC12
AP10 GND199 GND291 G22
AU26 GND200 GND292 G24
AP14 GND201 GND293 AW20
AU14 GND202 GND294 G34
AP28 GND203 GND295 G4
AP32 GND204 GND296 G43
AP34 GND205 GND297 G6
AP36 GND206 GND298 G8
AP37 GND207 GND299 H11
AP4 GND208 GND300 H15
AP40 GND209 GND301 AW35
AP7 GND210 GND302 H23
AW23 GND211 GND303 AN8
AR28 GND212 GND304 G40
AR32 GND213 GND305 J12
AR40 GND214 GND306 J8
AT10 GND215 GND307 K10
AR12 GND216 GND308 K12
AT13 GND217 GND309 K18
AT29 GND218 GND310 K26
AT33 GND219 GND311 K37
AT6 GND220 GND312 K4
AT7 GND221 GND313 K40
AT9 GND222 GND314 K8
AY21 GND223 GND315 AU1
AY22 GND224 GND316 L40
L12 GND225 GND317 L43
AU12 GND226 GND318 L5
AU28 GND227 GND319 M10
AP33 GND228 GND320 M34
AU32 GND229 GND321 M35
AR30 GND230 GND322 M37
AU36 GND231 GND323 Y28
AU38 GND232 GND324 Y33
AU4 GND233 GND325 Y34
G28 GND234 GND326 Y35
F20 GND235 GND327 Y37
AV28 GND236 GND328 Y38
AV32 GND237 GND329 AB17
AV36 GND238 GND330 AB16
AV4 GND239 GND331 AN26
AV7 GND240 GND332 AD7
AW11 GND241 GND333 M11
G20 GND242 GND334 AA4
AR43 GND243 GND335 AB19
AW43 GND244 GND336 AY13
AY10 GND245 GND337 P11
AV12 GND246 GND338 Y6
AY30 GND247 GND339 T11
AY33 GND248 GND340 V11
AY34 GND249 GND341 Y11
AY37 GND250 GND342 AH16
AY38 GND251 GND343 T22
AY41 GND252
GND
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
23065 mA (A01, 1.2V)
16996 mA (A01, 1.0V)
10 uA (G3)
80 uA (S0)
AA25 +VDD_CORE1
AC23 +VDD_CORE2
U25 +VDD_CORE3
AH12 +VDD_CORE4
AG10 +VDD_CORE5
AG5 +VDD_CORE6
Y21 +VDD_CORE7
Y23 +VDD_CORE8
AA16 +VDD_CORE9
AA26 +VDD_CORE10
AA27 +VDD_CORE11
AA28 +VDD_CORE12
AC16 +VDD_CORE13
AC17 +VDD_CORE14
AC18 +VDD_CORE15
AC19 +VDD_CORE16
AC20 +VDD_CORE17
AC21 +VDD_CORE18
AA17 +VDD_CORE19
AC24 +VDD_CORE20
AC25 +VDD_CORE21
AC26 +VDD_CORE22
AC27 +VDD_CORE23
AC28 +VDD_CORE24
AD21 +VDD_CORE25
AD23 +VDD_CORE26
W27 +VDD_CORE27
V25 +VDD_CORE28
AA18 +VDD_CORE29
AE19 +VDD_CORE30
AE21 +VDD_CORE31
AE23 +VDD_CORE32
AE25 +VDD_CORE33
AE26 +VDD_CORE34
AE27 +VDD_CORE35
AE28 +VDD_CORE36
AF10 +VDD_CORE37
AF11 +VDD_CORE38
AA19 +VDD_CORE39
AF2 +VDD_CORE40
AF21 +VDD_CORE41
AF23 +VDD_CORE42
AF25 +VDD_CORE43
AF3 +VDD_CORE44
AF4 +VDD_CORE45
AF7 +VDD_CORE46
AH23 +VDD_CORE47
AF9 +VDD_CORE48
AA20 +VDD_CORE49
AG11 +VDD_CORE50
AG12 +VDD_CORE51
AG21 +VDD_CORE52
AG23 +VDD_CORE53
AG25 +VDD_CORE54
AG3 +VDD_CORE55
AG4 +VDD_CORE56
AA21 +VDD_CORE57
AG6 +VDD_CORE58
AG7 +VDD_CORE59
AG8 +VDD_CORE60
AG9 +VDD_CORE61
AH1 +VDD_CORE62
AH10 +VDD_CORE63
AH11 +VDD_CORE64
W26 +VDD_CORE65
AH2 +VDD_CORE66
AA23 +VDD_CORE67
W28 +VDD_CORE68
AH25 +VDD_CORE69
AH21 +VDD_CORE70
AH3 +VDD_CORE71
AH4 +VDD_CORE72
AH5 +VDD_CORE73
AH6 +VDD_CORE74
AH7 +VDD_CORE75
AH9 +VDD_CORE76
AA24 +VDD_CORE77
W21 +VDD_CORE78
W23 +VDD_CORE79
W25 +VDD_CORE80
AF12 +VDD_CORE81
A20 +VBAT
OMIT
U1400
61B1 44D7 24D8 8C8 =PPVCORE_S0_MCP
MCP79-TOPO-B
BGA
(10 OF 11)
=PP1V05_S0_MCP_FSB
8D7 9C2 14A2 14B7 24C8
26D4 21C8 7C3 PP3V3_G3_RTC
POWER
+VTT_CPU1 R32
+VTT_CPU2 AC32
+VTT_CPU3 E40
+VTT_CPU4 J36
+VTT_CPU5 N32
+VTT_CPU6 T32
+VTT_CPU7 U32
+VTT_CPU8 V32
+VTT_CPU9 W32
+VTT_CPU10 P31
+VTT_CPU11 AF32
+VTT_CPU12 AE32
+VTT_CPU13 AH32
+VTT_CPU14 AJ32
+VTT_CPU15 AK31
+VTT_CPU16 AK32
+VTT_CPU17 AD32
+VTT_CPU18 AL31
+VTT_CPU19 AB32
+VTT_CPU20 B41
+VTT_CPU21 B42
+VTT_CPU22 C40
+VTT_CPU23 C41
+VTT_CPU24 C42
+VTT_CPU25 D39
+VTT_CPU26 D40
+VTT_CPU27 D41
+VTT_CPU28 E38
+VTT_CPU29 E39
+VTT_CPU30 F37
+VTT_CPU31 F38
+VTT_CPU32 F39
+VTT_CPU33 G36
+VTT_CPU34 G37
+VTT_CPU35 G38
+VTT_CPU36 H35
+VTT_CPU37 H37
+VTT_CPU38 J34
+VTT_CPU39 J35
+VTT_CPU40 K33
+VTT_CPU41 K34
+VTT_CPU42 K35
+VTT_CPU43 L32
+VTT_CPU44 L33
+VTT_CPU45 L34
+VTT_CPU46 M31
+VTT_CPU47 M32
+VTT_CPU48 M33
+VTT_CPU49 N31
+VTT_CPU50 P32
+VTT_CPU51 Y32
+VTT_CPU52 AA32
+VTT_CPUCLK AG32
+3.3V_1 AD10
+3.3V_2 AE8
+3.3V_3 AB10
+3.3V_4 AD9
+3.3V_5 Y10
+3.3V_6 AB11
+3.3V_7 AA8
+3.3V_8 Y9
+3.3V_DUAL1 G18
+3.3V_DUAL2 H19
+3.3V_DUAL3 J20
+3.3V_DUAL4 K20
+3.3V_DUAL_USB1 G26
+3.3V_DUAL_USB2 H27
+3.3V_DUAL_USB3 J28
+3.3V_DUAL_USB4 K28
8 7 6 5 4 3 2 1
+VDD_AUXC1 T21
+VDD_AUXC2 U21
+VDD_AUXC3 V21
1139 mA
43 mA
=PP3V3_S0_MCP
16 mA
250 mA
1182 mA (A01)
8C5 21C2 24B8
450 mA (A01)
Preliminary
=PP3V3_S5_MCP
=PP1V05_S5_MCP_VDD_AUXC
8A3 24B8
266 mA (A01)
8B3 24C8
105 mA (A01)
SYNC_MASTER=T18_MLB
APPLE INC.
MCP Power & Ground
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
SHT OF
22
SYNC_DATE=04/04/2008
REV.
051-7537 A
109
D
C
B
A

D
C
B
A
8 7 6 5 4 3 2 1
19C4 13B6 OUT PM_LATRIGGER_L
31C7 17B6 7D5
21B7 13C3 6C5
21B7 13C3 6C5
OUT
OUT
OUT
3.3V Interface Pull-ups
PCIE_WAKE_L
JTAG_MCP_TDI
JTAG_MCP_TMS
26A1 21B7 OUT PM_SYSRST_DEBOUNCE_L
21C7 OUT TP_MCP_LID_L
MCP_LID_L
MAKE_BASE=TRUE
39C5 21C7 OUT SMC_WAKE_SCI_L
39B8 21C7 OUT SMC_RUNTIME_SCI_L
39C8 21B7 OUT PM_PWRBTN_L
39B8 21C7 OUT PM_BATLOW_L
These internal pull-ups are missing in Revs A01 & A01P.
R2400 1
2
MCP_A01&MCP_A01P&MCP_A01Q
R2401 10K 1
2
5% 1/16W
MCP_A01&MCP_A01P&MCP_A01Q
R2402 10K 1
2
MF-LF 402
5% 1/16W MF-LF 402
MCP_A01&MCP_A01P&MCP_A01Q
10K
5% 1/16W MF-LF 402
MCP_A01&MCP_A01P&MCP_A01Q
R2404 10K 1
2
5% 1/16W
R2405 1
2
MF-LF 402
MCP_A01&MCP_A01P&MCP_A01Q
MCP_A01&MCP_A01P&MCP_A01Q
R2403 10K 1
2
5% 1/16W MF-LF 402
10K
5% 1/16W MF-LF 402
R2413 1
2
MCP_A01&MCP_A01P&MCP_A01Q
R2410 1
2
MCP_A01&MCP_A01P&MCP_A01Q
R2411 10K 1
2
5% 1/16W
MCP_A01&MCP_A01P&MCP_A01Q
R2412 10K 1
2
MF-LF 402
5% 1/16W
10K
MF-LF 402
5% 1/16W MF-LF 402
MCP_A01&MCP_A01P&MCP_A01Q
10K
5% 1/16W MF-LF 402
MCP_SAFE_MODE SIGNAL TO SUPPORT ROM FAILURE OVERRIDE
21C3 MCP_SPKR
RADAR 5925345
R2430
1
0
5%
1/16W
MF-LF
402
2
41B4 8A3 =PP3V3_S5_MCP_A01
SMC_MCP_SAFE_MODE
Preliminary
8 7 6 5 4 3 2 1
IN 39B5
SYNC_MASTER=T18_MLB
APPLE INC.
MCP79 A01 Silicon Support
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
SHT OF
24
SYNC_DATE=03/08/2008
REV.
051-7537 A
109
D
C
B
A

D
C
B
A
61B1 44D7 22D5
14B7 14A2 9C2 8D7 =PP1V05_S0_MCP_FSB
22D3
1182 mA (A01)
8 7 6 5 4 3 2 1
MCP Core Power
8C8 =PPVCORE_S0_MCP
23065 mA (A01, 1.2V)
16996 mA (A01, 1.0V)
(No IG vs. EG data)
MCP PCIE (DVDD) Power
MCP 1.05V AUX Power
MCP FSB (VTT) Power
MCP Memory Power
16C7 16C3 8B7 =PP1V8R1V5_S0_MCP_MEM
4771 mA (A01, DDR3)
MCP 3.3V Power
MCP 3.3V AUX/USB Power
266 mA (A01)
MCP 3.3V/1.5V HDA Power
7 mA (A01)
C2500
4.7UF
20%
4V
X5R
402
1
2
NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF)
Apple: 4x 4.7uF 0402, 4x 1uF 0402, 6x 0.1uF 0402 (23.4 uF)
C2502
4.7UF
20%
4V
X5R
402
1
2
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)
Apple: 7x 2.2uF 0402 (15.4 uF)
NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF)
Apple: 4x 2.2uF 0402 (8.8 uF)
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)
C2504
1UF
10%
10V
2
X5R
402-1
MCP SATA (DVDD) Power
8B7 8A8 =PP1V05_S0_MCP_PEX_DVDD 8B7 8A8 =PP1V05_S0_MCP_SATA_DVDD
57 mA (A01)
43 mA (A01)
C2515
4.7UF
20%
4V
X5R
402
1
2
MCP 1.05V RMGT Power
22A3 8B3 =PP1V05_S5_MCP_VDD_AUXC
18D3 8B1 =PP1V05_ENET_MCP_RMGT
105 mA (A01) 131 mA (A01)
22B3 21C2 8C5 =PP3V3_S0_MCP
C2540
4.7UF
20%
4V
X5R
402
1
2
1
1
C2530
2.2UF
20%
6.3V
2
CERM
402-LF
C2516
1UF
10%
10V
X5R
402-1
C2531
2.2UF
20%
6.3V
2
CERM
402-LF
C2532
2.2UF
20%
6.3V
2
CERM
402-LF
450 mA (A01) 19 mA (A01)
22B3 8A3 =PP3V3_S5_MCP
21D8 21D3 8B5 =PP3V3R1V5_S0_MCP_HDA
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) MCP 3.3V Ethernet Power
Apple: 1x 2.2uF 0402 (2.2 uF)
24A6 18D3 18C7 8B1 =PP3V3_ENET_MCP_RMGT
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
1
2
0.1uF
20%
10V
2
CERM
402
C2550
1
2.2UF
20%
6.3V
2
CERM
402-LF
1
1
2.2UF
20%
6.3V
2
CERM
402-LF
C2501
4.7UF
20%
4V
X5R
402
1
2
C2525
2.2UF
20%
6.3V
2
CERM
402-LF
1 C2541
0.1UF
20%
10V
2
CERM
402
C2560
C2562
1
1
1
C2517
1UF
10%
10V
2
X5R
402-1
C2526
0.1uF
20%
10V
2
CERM
402
1
0.1UF
20%
10V
2
CERM
402
1 C2551
2.2UF
20%
6.3V
2
CERM
402-LF
C2542
1
C2552
1
2.2UF
20%
6.3V
2
CERM
402-LF
C2503
4.7UF
20%
4V
X5R
402
1
2
1 C2518
0.1uF
20%
10V
2
CERM
402
1 C2543
0.1UF
20%
10V
2
CERM
402
1
1
C2533
2.2UF
20%
6.3V
2
CERM
402-LF
1 C2519
0.1uF
20%
10V
2
CERM
402
1 C2544
0.1UF
20%
10V
2
CERM
402
1 C2553
2.2UF
20%
6.3V
2
CERM
402-LF
1
C2505
1UF
10%
10V
2
X5R
402-1
1 C2534
2.2UF
20%
6.3V
2
CERM
402-LF
1 C2545
0.1UF
20%
10V
2
CERM
402
5 mA (A01)
5 mA (A01)
C2595
4.7UF
20%
4V
X5R
402
1
8B1 =PP1V05_ENET_MCP_PLL_MAC
L2595
30-OHM-1.7A
1 2
PP1V05_ENET_MCP_PLL_MAC
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
18C6
0402
VOLTAGE=1.05V
1 C2596
0.1UF
2
20%
10V
2
CERM
402
1
1
C2506
1UF
10%
10V
2
X5R
402-1
C2535
2.2UF
20%
6.3V
2
CERM
402-LF
1 C2546
0.1UF
20%
10V
2
CERM
402
8B5 =PP3V3_S0_MCP_PLL_UF
1
83 mA (A01)
1
C2507
1UF
10%
10V
2
X5R
402-1
C2520
4.7UF
20%
4V
X5R
402
1
2
C2528
4.7uF
20%
4V
X5R
402
1
2
C2536
2.2UF
20%
6.3V
2
CERM
402-LF
1 C2547
0.1UF
20%
10V
2
CERM
402
1
0.1uF
20%
10V
2
CERM
402
1
1 C2508
0.1UF
20%
10V
2
CERM
402
C2521
C2529
0.1uF
20%
10V
2
CERM
402
1 C2548
0.1UF
20%
10V
2
CERM
402
L2555
30-OHM-1.7A
1 2
0402
24B6 18D3 18C7 8B1 =PP3V3_ENET_MCP_RMGT
1 C2509
0.1UF
20%
10V
2
CERM
402
1 C2549
0.1UF
20%
10V
2
CERM
402
MCP79 Ethernet VRef
R2591
1.47K
1%
1/16W
MF-LF
402
1
2
1.47K
1/16W
1%
R2590
MF-LF
402
1
2
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)
PP3V3_S0_MCP_PLL_USB
20C3
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
19 mA (A01)
VOLTAGE=3.3V
C2555
1
2.2UF
20%
6.3V
2
CERM
402-LF
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)
1
C2564
2.2UF
20%
6.3V
2
CERM
402-LF
MCP_MII_VREF
1 C2591
0.1UF
20%
10V
2
CERM
402
8 7 6 5 4 3 2 1
1 C2510
0.1UF
20%
10V
2
CERM
402
OUT 18D3
1 C2511
0.1UF
20%
10V
2
CERM
402
1 C2512
0.1UF
20%
10V
2
CERM
402
1 C2513
0.1UF
20%
10V
2
CERM
402
8B7 =PP1V05_S0_MCP_AVDD_UF
333 mA (A01)
8B7 =PP1V05_S0_MCP_PLL_UF
562 mA (A01)
L2570
30-OHM-5A
1 2
0603
L2575
30-OHM-5A
1 2
0603
L2580
30-OHM-1.7A
1 2
C2580
4.7UF
20%
4V
X5R
402
1
0402
2
L2582
30-OHM-1.7A
1 2
C2582
4.7UF
20%
4V
X5R
402
1
0402
2
L2584
30-OHM-1.7A
1 2
C2584
4.7UF
20%
4V
X5R
402
1
0402
2
L2586
30-OHM-1.7A
1 2
C2586
4.7UF
20%
4V
X5R
402
1
0402
2
L2588
30-OHM-1.7A
1 2
C2588
4.7UF
20%
4V
X5R
402
1
0402
2
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF)
Apple: 5x 2.2uF 0402 (11 uF)
PP1V05_S0_MCP_PEX_AVDD
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
1
C2570
2.2UF
20%
6.3V
2
CERM
402-LF
1
1
C2571
2.2UF
20%
6.3V
2
CERM
402-LF
1
C2572
2.2UF
20%
6.3V
2
CERM
402-LF
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)
Apple: 2x 2.2uF 0402 (4.4 uF)
PP1V05_S0_MCP_SATA_AVDD
8A8
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
127 mA (A01)
VOLTAGE=1.05V
C2575
2.2UF
20%
6.3V
2
CERM
402-LF
1
0.1UF
20%
10V
2
CERM
402
1
1
C2581
C2583
0.1UF
20%
10V
2
CERM
402
1
C2585
0.1UF
20%
10V
2
CERM
402
1
C2587
0.1UF
20%
10V
2
CERM
402
C2589
0.1UF
20%
10V
2
CERM
402
1
C2576
2.2UF
20%
6.3V
2
CERM
402-LF
PP1V05_S0_MCP_PLL_FSB
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
PP1V05_S0_MCP_PLL_PEX
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
PP1V05_S0_MCP_PLL_SATA
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
PP1V05_S0_MCP_PLL_CORE
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
1
C2590
0.1UF
20%
10V
2
CERM
402
1
14A6
270 mA (A01)
17A6
84 mA (A01)
20B6
84 mA (A01)
16C6
87 mA (A01)
Preliminary
PP1V05_S0_MCP_PLL_NV
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
APPLE INC.
C2573
2.2UF
20%
6.3V
2
CERM
402-LF
SYNC_MASTER=T18_MLB
2.2UF
20%
6.3V
2
CERM
402-LF
21C7
37 mA (A01)
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
1
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
C2574
MCP Standard Decoupling
DRAWING NUMBER
NONE
051-7537
SHT OF
25
8A8
206 mA (A01)
SYNC_DATE=04/04/2008
REV.
109
A
D
C
B
A

D
C
B
A
8 7 6 5 4 3 2 1
WF: Checklist says 0-ohm resistor placeholder for ferrite bead.
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)
NO STUFF
L2650
30-OHM-1.7A
NV: 1x 4.7uF 0603, 2x 0.1uF 0402 (4.9 uF)
Apple: 2x 2.2uF 0402 (4.4 uF)
190 mA (A01, 1.8V)
206 mA (A01) 1 2
206 mA (A01)
0402
NO STUFF
1 C2650
2.2UF
20%
6.3V
2
CERM
402-LF
1
R2651
0
5%
1/16W
MF-LF
2 402
1 C2610
2 6.3V
18B6 8A7 =PP3V3R1V8_S0_MCP_IFP_VDD
8C5 =PP3V3_S0_MCP_DAC_UF
PP3V3_S0_MCP_DAC
18C3
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
2.2UF
20%
CERM
402-LF
VOLTAGE=3.3V
95 mA (A01)
16 mA (A01)
HDCP ROM
WF: Open question on which packge option(s) nVidia can support.
8B5 =PP3V3_S0_HDCPROM
25A7 HDCPROM_WP
C2690 1
0.1UF
20%
10V
CERM 2
402
18A6 8B7 =PP1V05_S0_MCP_HDMI_VDD
NOSTUFF
8
VCC
U2695
1 A0 SDA
2 A1 SCL
3 A2
WP
GND
NOSTUFF
4
VCC
U2690
AT24C01B
SOT23
3 SDA
5 WP
SCL 1
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
AT24C08
SOIC
4
GND
2
5
6
7
C2615 1
4.7UF
20%
4V
X5R 2
402
C2620 1
73B3 18A6 MCP_HDMI_RSET
73B3 18A6 MCP_HDMI_VPROBE
NO STUFF
0.1UF
20%
10V
CERM
2
402
8C5 =PP3V3_S0_MCP_VPLL_UF
25A8
1
C2616
0.1UF
2 10V
20%
CERM
402
R2620
1K
1
1%
1/16W
MF-LF
402
2
=I2C_HDCPROM_SDA
=I2C_HDCPROM_SCL
HDCPROM_WP
WF: Checklist says 0-ohm resistor placeholder for ferrite bead.
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: ???
16 mA (A01)
C2640 1
L2640
30-OHM-1.7A
PP3V3_S0_MCP_VPLL
18A6
1 2
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
0402
VOLTAGE=3.3V
1 C2641
4.7UF
0.1uF
20%
6.3V
CERM
603
2 2
20%
10V
CERM
402
R2690 1
10K
5%
1/16W
MF-LF
402
2
BI
42C6
IN 42C6
C2630 1
73A3 18A3 MCP_IFPAB_RSET
73A3 18A3 MCP_IFPAB_VPROBE
NO STUFF
0.1UF
20%
10V
CERM
2
402
NO STUFF
1
R2630
1K
1%
1/16W
MF-LF
402
2
Preliminary
SYNC FROM T18
REMOVE MCP 27MHZ CRYSTAL CRICUIT SINCE NOT SUPPORTING TV-OUT
REMOVE DAC TERMINATIONS R2665,C2665 AND R2670 TO R2672
NOSTUFF PP3V3_S0_MCP_DAC RAIL COMPONENTS (L2650 AND C2650)
CHANGE C2651 TO R2651 TO GND PP3V3_S0_MCP_DAC
8 7 6 5 4 3 2 1
APPLE INC.
MCP Graphics Support
SYNC_MASTER=T18_MLB SYNC_DATE=12/12/2007
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
SHT OF
26
REV.
051-7537 A
109
D
C
B
A

D
C
B
A
8D1 =PP3V42_G3H_RTC_D
64A4 39D8
60C7
21B3
8 7 6 5 4 3 2 1
IN
IN
IN
1 C2870
1UF
10%
10V
2
X5R
402
3
EN
21B7
IN
21B7 OUT
21B7
IN
21B7 OUT
1
VIN
U2801
MIC5232-2.8YD5
TSOT-23-5
GND
2
VOUT
NC
NO STUFF
1
R2811
10M
5%
1/16W
MF-LF
402
2
MCP S0 PWRGD & CPU_VLD
8A3 =PP3V3_S5_MCPPWRGD
ALL_SYS_PWRGD
VR_PWRGOOD_DELAY
MCP_CPUVDD_EN
2
A
5 TC7SZ08AFEAPE
SOT665
U2850Y
4 S0_AND_IMVP_PGOOD
1
B
MCPSEQ_SMC represents MCP79 ’MLB’ power sequencing connections,
but results in MCP79 ROMSIP sequence happening after CPU powers up.
MCPSEQ_MIX is cross between MLB and internal power sequencing, which
results in earlier ROMSIP and MCP FSB I/O interface initialization.
SMC 99ms delay from ALL_SYS_PWRGD to IMVP_VR_ON plus IMVP6 delay for
VR_PWRGOOD_DELAY should guarantee CPU_VLD does not go high before
CPUVDD_EN (which is 40-100ms after PS_PWRGD assertion).
RTC Crystal
MCP 25MHz Crystal
NO STUFF
1
R2816
1M
5%
1/16W
MF-LF
402
2
CRITICAL
NOTE: If CPU_VLD deasserts during S0 MCP79 will take system to S5 immediately.
3
5
4
RTC_CLK32K_XTALOUT
RTC_CLK32K_XTALIN
MCP_CLK25M_XTALOUT
MCP_CLK25M_XTALIN
MCPSEQ_SMC
1 C2850
0.1UF
20%
10V
2
CERM
402
1 C2871
0.47UF
10%
10V
2
X5R
402
MCPSEQ_MIX
R2851
0
1
5%
1/16W
MF-LF
402
R2810
5%
1/16W
MF-LF
402
2
Y2810
32.768K
0
7X1.5X1.4-SM
R2815
1 4
CRITICAL
Y2815
25.0000M
SM-3.2X2.5MM
2
1
3
1
MCPSEQ_SMC
R2853
0
MCPSEQ_SMC
R2850
0
PLACEMENT_NOTE=Place close to U1400 5%
1/16W
MF-LF
402
1
1
1
5%
1/16W
MF-LF
402
MCPSEQ_MIX
R2852
0
5%
1/16W
MF-LF
402
2
2
2
RTC_CLK32K_XTALOUT_R
1
0
5%
1/16W
MF-LF
402
2
MCP_CLK25M_XTALOUT_R
4
2
NC
NC
C2810
12pF
1 2
5%
50V
CERM
402
C2811
12pF
1 2
5%
50V
CERM
402
C2815
12pF
1 2
5%
50V
CERM
402
C2816
12pF
1 2
5%
50V
CERM
402
OUT 21B7
OUT 21B7
RTC Power Sources
R2819
100
402
2
1
MF-LF
PP3V3_G3_SUPERCAP
1 C2800
0.08F
2%
2 3.3V
XHHG
SM
C2819
10%
1UF
6.3V
CERM
402
1
2
PP3V3_G3_RTC 7C3 21C8 22A5
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
PLACEMENT_NOTE=PLACE C2819 CLOSE TO MCP79
PLACE C2819 CLOSE TO MCP79
PLACE C2800 AT COOLEST SPOT ON MLB
SYNC FROM T18
CHANGE RESET BUTTOM TO RESET PADS
REMOVE UNUSED PCIE RESET SIGNALS
REMOVE R2824 AND NET PCI_CLK33M_SLOT_A
CHANGE RTC COIN CELL TO LDO & SUPERCAP
ALIAS MEM_VTT_EN TO =DDRVTT_EN
CHANGE Y2810 AND U2850 TO SMALLER PARTS
74C3 19B3 IN LPC_RESET_L
PLACEMENT_NOTE=Place close to U1400
1
33
5%
2
DEBUG_RESET_L
OUT 41D5
1/16W
MF-LF
402
R2883
33
1 2 SMC_LRESET_L
OUT 39C8
PLACEMENT_NOTE=Place close to U1400 5%
1/16W
MF-LF
402
8 7 6 5 4 3 2 1
17B3
19C4
IN
74C3 19B3
74A3 21B3
IN
IN
IN
39B8
13B3 10C6
PCIE_RESET_L
MEM_VTT_EN_R
LPC_CLK33M_SMC_R
IN
IN
Platform Reset Connections
LPC Reset (Unbuffered)
R2881
PCIE Reset (Unbuffered)
R2870
33
1 2
5%
1/16W
MF-LF
402
R2891
0
1
2
5%
1/16W
MF-LF
402
R2872
0
1
2
R2825
PLACEMENT_NOTE=Place close to U1400
1
33
2
5%
1/16W
MF-LF
402
Reset Button
R2826
33
1
2
PLACEMENT_NOTE=Place close to U1400 5%
1/16W
MF-LF
402
R2829
PM_CLK32K_SUSCLK_R 1
22
2
PM_CLK32K_SUSCLK
5%
1/16W
MF-LF
402
PLACEMENT_NOTE=Place close to U1400 5%
1/16W
MF-LF
402
R2892
0
1
5%
1/16W
MF-LF
402
2
R2871
0
1 2
APPLE INC.
SCALE
NONE
OUT 70C8
OUT 31A6
OUT 27A5
OUT 32B3
OUT 59C8 65A3
OUT 39C8 74C3
OUT 41D3 74C3
OUT 39C5 74A3
XDP_DBRESET_L
XDP
R2898
0
1
2
R2899
33
1
2
10K pull-up to 3.3V S0 inside MCP
PM_SYSRST_DEBOUNCE_L
OUT 21B7 23C5
5%
1/16W
MF-LF
402
1
R2890
0
5%
1/16W
MF-LF
402
2
NO STUFF
SILK_PART=SYS RST
5%
1/16W
MF-LF
402
NO STUFF
1 C2899
1UF
10%
10V
2
X5R
402
5%
1/16W
MF-LF
402
MINI_RESET_L
FC_RESET_L
MEM_VTT_EN =DDRVTT_EN
MAKE_BASE=TRUE
Preliminary
MCP_PS_PWRGD
MCP_CPU_VLD
PM_SYSRST_L
BKLT_PLT_RST_L
PCA9557D_RESET_L
LPC_CLK33M_SMC
LPC_CLK33M_LPCPLUS
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SB Misc
SYNC_MASTER=RAYMOND SYNC_DATE=04/05/2008
DRAWING NUMBER
051-7537
SHT OF
28
REV.
109
A
D
C
B
A

D
C
B
A
8 7 6 5 4 3 2 1
Page Notes
Power aliases required by this page:
- =PP3V3_S3_VREFMRGN
- =PP3V3_S5_VREFMRGN
- =PPVTT_S3_DDR_BUF
Signal aliases required by this page:
- =I2C_VREFDACS_SCL
- =I2C_VREFDACS_SDA
- =I2C_PCA9557D_SCL
- =I2C_PCA9557D_SDA
BOM options provided by this page:
VREFMRGN
NO_VREFMRGN
=PP3V3_S3_VREFMRGN
8D3
42A3
IN
42A3 BI
42B3
IN
42B3 BI
ADDR=0x98(WR)/0x99(RD)
ADDR=0x30(WR)/0x31(RD)
=I2C_PCA9557D_SCL
=I2C_PCA9557D_SDA
VREFMRGN
C2900
2.2UF
20%
6.3V
CERM
402-LF
MEM A VREF DQ
DAC channel A B A B C
Min DAC code 0x00 0x00 0x00 0x00 0x00
Max DAC code 0x87 0x87 0x87 0x87 0x55
Max sink I -3.75 mA -3.75 mA -3.75 mA -3.75 mA -0.91 mA
Max source I 5 mA 5 mA 5 mA 5 mA 0.52 mA
Nominal Vref 0.75 V 0.75 V 0.75 V 0.75 V 0.70 V
Min Vref 0.375 V 0.375 V 0.375 V 0.375 V 0.091 V
Max Vref 1.250 V 1.250 V 1.250 V 1.250 V 1.044 V
Vref Stepping 6.5 mV 6.5 mV 6.5 mV 6.5 mV 11.2 mV
(per DAC LSB)
20%
2
10V
CERM
402
6 SCL
7 SDA
9 A0
10 A1
Required zero ohm resistors when no VREF margining circuit stuffed
GND
3
VCC
VOUTB 2
VOUTC 4
VOUTD 5
3 A0
PCA9557
QFN
P0 6
P1 7
NC
4 A1
P2 9
5 A2
P3 10
P4 11
P5 12
1 SCL
2 SDA
P6 13
P7 14
NC
NC
THRM RESET* 15
PAD GND
MEM A VREF CA
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
116S0004 1 RES,MTL FILM,0,5%,0402,SM,LF
1
0.1UF
20%
2
10V
CERM
402
=I2C_VREFDACS_SCL
=I2C_VREFDACS_SDA
1
VREFMRGN
C2901
VREFMRGN
C2902
0.1UF
17
VREFMRGN
8 U2900
VDD
MSOP VOUTA 1
DAC5574
16
U2901
8
VREFMRGN
VREFMRGN_DQ_SODIMM
VREFMRGN_CA_SODIMM
VREFMRGN_CPUFSB
R2903 CRITICAL NO_VREFMRGN
116S0004 1 RES,MTL FILM,0,5%,0402,SM,LF R2905 CRITICAL NO_VREFMRGN
116S0004 1 RES,MTL FILM,0,5%,0402,SM,LF R2909 CRITICAL NO_VREFMRGN
116S0004 1 RES,MTL FILM,0,5%,0402,SM,LF R2911 CRITICAL NO_VREFMRGN
NC
MEM B VREF DQ
VREFMRGN_CPUFSB_EN
27B3
VREFMRGN_CA_SODIMMA_EN
27C3
VREFMRGN_DQ_SODIMMA_EN
27D3
VREFMRGN_CA_SODIMMB_EN
27B3
VREFMRGN_DQ_SODIMMB_EN
27C3
PCA9557D_RESET_L
IN
26C1
MEM B VREF CA CPU FSB VREF
B1
A2
V+
MAX4253
UCSP
VREFMRGN
A1
8 7 6 5 4 3 2 1
1
1
20%
10V
2 CERM
402
1
VREFMRGN
C2903
0.1UF
20%
10V
2 CERM
402
VREFMRGN
C2904
0.1UF
VREFMRGN
C2905
0.1UF
20%
10V
2 CERM
402
A3
V-
B4
B1
C2
V+
MAX4253
UCSP
VREFMRGN
C1
C3
V-
B4
B1
A2
V+
MAX4253
UCSP
VREFMRGN
A1
A3
V-
B4
B1
C2
V+
MAX4253
UCSP
VREFMRGN
C1
C3
V-
B4
V-
B4
SO-DIMM A and SO-DIMM B Vref settings should be margined separately
(i.e. not simultaneously) due to current limitation of TPS51116 regulator.
U2903
C4
B1
A2
V+
MAX4253
UCSP
VREFMRGN
A1
NC
A3
V-
B4
A4
B1
C2
V+
MAX4253
UCSP
VREFMRGN
C1
C3
=PPVTT_S3_DDR_BUF
59D7 8C4
U2902
A4
U2902
C4
U2903
A4
U2904
U2904
C4
10mA max load
VREFMRGN_DQ_SODIMMA_BUF
27A5 VREFMRGN_DQ_SODIMMA_EN
R2901
100K
VREFMRGN
5%
1/16W
MF-LF
402
R2902
100K
1 2
VREFMRGN_DQ_SODIMMB_BUF
27A5 VREFMRGN_DQ_SODIMMB_EN
1 2
5%
1/16W
MF-LF
402
VREFMRGN_CA_SODIMMA_BUF
27A5 VREFMRGN_CA_SODIMMA_EN
R2907
1 2
VREFMRGN
100K VREFMRGN
5%
1/16W
MF-LF
402
VREFMRGN_CA_SODIMMB_BUF
27A5 VREFMRGN_CA_SODIMMB_EN
R2908
100K
1 2
5%
1/16W
MF-LF
402
VREFMRGN_CPUFSB_BUF
27A5 VREFMRGN_CPUFSB_EN
R2913
100K
2
5%
1/16W
MF-LF
402
1
VREFMRGN
VREFMRGN
R2903
R2904
1
1
100
1%
1/16W
MF-LF
402
2
R2905
R2906
1
100
1%
1/16W
MF-LF
402
2
R2909
R2910
1
1
200
1 2
1%
1/16W
MF-LF
402
200
1 2
1%
1/16W
MF-LF
402
200
1 2
1%
1/16W
MF-LF
402
100
1%
1/16W
MF-LF
402
200
1%
1/16W
MF-LF
402
2
R2911
1 2
R2912
100
1%
1/16W
MF-LF
402
R2914
100
1%
1/16W
MF-LF
402
2
2
VREFMRGN
VREFMRGN
VREFMRGN
VREFMRGN
VREFMRGN
VREFMRGN
VREFMRGN
VREFMRGN
VREFMRGN
PP0V75_S3_MEM_VREFDQ_A
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
Place close to J3100.1
PP0V75_S3_MEM_VREFDQ_B
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
Place close to J3200.1
PP0V75_S3_MEM_VREFCA_A
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
Place close to J3100.126
PP0V75_S3_MEM_VREFCA_B
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
Place close to J3200.126
Preliminary
CPU_GTLREF
Place close to U1000.AD26
SYNC_MASTER=BEN
APPLE INC.
28D5
29D5
28B3
29B3
SCALE
OUT 10B4 71B3
FSB/DDR3 Vref Margining
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
DRAWING NUMBER
NONE
SYNC_DATE=03/31/2008
051-7537
SHT OF
29 109
REV.
A
D
C
B
A

D
C
B
A
- =PP1V5_S0_MEM_A
- =PP1V5_S3_MEM_A
- =PP0V75_S0_MEM_VTT_A
Signal aliases required by this page:
- =I2C_SODIMMA_SCL
BOM options provided by this page:
(NONE)
8 7 6 5 4 3 2 1
Page Notes
Power aliases required by this page:
- =PPSPD_S0_MEM_A (2.5 - 3.3V)
- =I2C_SODIMMA_SDA
8B5 =PPSPD_S0_MEM_A
1 C3140
2.2UF
20%
6.3V
2
CERM
402-LF
72D3 15A5
72D3 15C5
72D3 15C5
72D3 15B5
72D3 15B5
72D3 15B5
72D3 15B5
72D3 15B5
72D3 15B5
72D3 15B5
72D3 15C5
72D3 15C5
72D3 15C5
72D3 15C5
72D3 15C5
72D3 15B5
72D3 15C7
72D3 15C7
72C3 15D5
72C3 15D5
72D3 15C7
72D3 15C7
72D3 15C7
72D3 15C7
72C3 15B7
72D3 15C7
72D3 15C7
72D3 15D7
72D3 15D7
72C3 15D5
72C3 15D5
72D3 15D7
72D3 15D7
72D3 15D7
72D3 15D7
72C3 15B7
72D3 15D7
72D3 15D7
1
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
BI
BI
R3140
10K
5%
1/16W
MF-LF
402
2
MEM_A_CKE
MEM_A_BA
MEM_A_A
MEM_A_A
MEM_A_A
MEM_A_A
MEM_A_A
MEM_A_A
MEM_A_CLK_P
MEM_A_CLK_N
MEM_A_A
MEM_A_BA
MEM_A_WE_L
MEM_A_CAS_L
MEM_A_A
MEM_A_CS_L
MEM_A_DQ
MEM_A_DQ
MEM_A_DQS_N
MEM_A_DQS_P
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DM
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQS_N
MEM_A_DQS_P
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DM
MEM_A_DQ
MEM_A_DQ
MEM_A_SA
R3141
10K
1
MEM_A_SA
5%
1/16W
MF-LF
402
2
8D3 =PP1V5_S3_MEM_A
73
75
77
NC
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
NC
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
KEY
CKE0
CKE1
VDD
NC
BA2
J3100
F-RT-THB
VDD
A15
A14
VDD
VDD
A12/BC*
A11
A9
A7
VDD
VDD
A8
A6
A5
A4
VDD
VDD
A3
A2
A1
A0
VDD
VDD
CK0
CK1
CK0*
CK1*
VDD
VDD
A10/AP
BA1
BA0
RAS*
VDD
VDD
WE*
S0*
CAS*
ODT0
VDD
VDD
A13
ODT1
S1*
NC
VDD
VDD
TEST
VREFCA
VSS
VSS
DQ32
DQ36
DQ33
DQ37
VSS
VSS
DQS4*
DM4
DQS4
VSS
VSS
DQ38
DQ34
DQ39
DQ35
VSS
VSS
DQ44
DQ40
DQ45
DQ41
VSS
VSS
DQS5*
DM5
DQS5
VSS
VSS
DQ42
DQ46
DQ43
DQ47
VSS
VSS
DQ48
DQ52
DQ49
DQ53
VSS
VSS
DQS6*
DM6
DQS6
VSS
VSS
DQ54
DQ50
DQ55
DQ51
VSS
VSS
DQ60
DQ56
DQ61
DQ57
VSS
VSS
DQS7*
DM7
DQS7
VSS
VSS
DQ58
DQ62
DQ59
DQ63
VSS
VSS
SA0
EVENT*
VDDSPD
SDA
SA1
SCL
VTT
VTT
DDR3-SODIMM-DUAL-M97-3
(SYMBOL 2 OF 2)
516-0201
SPD ADDR=0xA0(WR)/0xA1(RD)
1 C3100
10UF
20%
6.3V
2
X5R
603
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
NC
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
1 C3101
10UF
20%
6.3V
2
X5R
603
MEM_A_CKE
MEM_A_A
MEM_A_A
MEM_A_A
MEM_A_A
MEM_A_A
MEM_A_A
MEM_A_A
MEM_A_A
1
0.1UF
20%
6.3V
2 X6S-CERM
0204-1
MEM_A_CLK_P
MEM_A_CLK_N
MEM_A_BA
MEM_A_RAS_L
MEM_A_CS_L
MEM_A_ODT
MEM_A_ODT
MEM_A_DQ
MEM_A_DQ
MEM_A_DM
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
DDR3 DECOUPLING AND GROUND RETURN CAPS (CONNECTOR SIDE)
C3110
MEM_A_DQS_N
MEM_A_DQS_P
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DM
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQS_N
MEM_A_DQS_P
MEM_A_DQ
MEM_A_DQ
MEM_EVENT_L
=I2C_SODIMMA_SDA
=I2C_SODIMMA_SCL
IN 15A5 72D3
IN 9D2
IN 15C5 72D3
IN 15C5 72D3
IN 15B5 72D3
IN 15B5 72D3
IN 15B5 72D3
IN 15B5 72D3
IN 15B5 72D3
IN 15B5 72D3
IN 15B5 72D3
IN 15C5 72D3
IN 15C5 72D3
IN 15B5 72D3
IN 15A5 72D3
IN 15A5 72D3
BI
BI
IN 15A7 72C3
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN 15B7 72C3
BI
BI
BI
BI
BI
BI
BI
BI
OUT 21A4 21B3 29A5 39B8
BI
IN
C3111
1
0.1UF
20%
6.3V
2 X6S-CERM
0204-1
15C7 72D3
15C7 72D3
15C7 72D3
15C7 72D3
15C7 72D3
15C7 72D3
15D5 72C3
15D5 72C3
15C7 72D3
15C7 72D3
15D7 72D3
15D7 72D3
15D7 72D3
15D7 72D3
15D7 72D3
15D7 72D3
15D5 72C3
15D5 72C3
15D7 72D3
15D7 72D3
42D6
42D6
1
C3150
2.2UF
20%
6.3V
2 CERM
402-LF
1
0.1UF
20%
6.3V
2 X6S-CERM
0204-1
27D1 PP0V75_S3_MEM_VREFDQ_A
C3112
72D3 15B7
72D3 15B7
72C3 15A7
72D3 15B7
72D3 15B7
72D3 15B7
72D3 15B7
72C3 15D5
72C3 15D5
72D3 15B7
72D3 15B7
72D3 15C7
72D3 15C7
72C3 15D5
72C3 15D5
72D3 15C7
72D3 15C7
72D3 15B7
72D3 15B7
72C3 15A7
72D3 15C7
72D3 15B7
1
2.2UF
20%
6.3V
2
CERM
402-LF
1
2
BI
BI
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
BI
BI
C3135
C3151
2.2UF
20%
6.3V
CERM
402-LF
VREFDQ
VSS
VSS
DQ4
DQ0
DQ1
CRITICAL
DQ5
VSS
VSS
DM0
VSS
DQS0*
J3100 DQS0
F-RT-THB
VSS
DQ2
DQ6
DQ3
DQ7
VSS
VSS
DQ8
DQ12
DQ9
DQ13
VSS
VSS
DQS1*
DM1
DQS1
RESET*
VSS
VSS
DQ10
DQ14
DQ11
DQ15
VSS
VSS
DQ16
DQ20
DQ17
DQ21
VSS
VSS
DQS2*
DM2
DQS2
VSS
VSS
DQ22
DQ18
DQ23
DQ19
VSS
VSS
DQ28
DQ24
DQ29
DQ25
VSS
VSS
DQS3*
DM3
DQS3
VSS
VSS
DQ26
DQ30
DQ27
DQ31
VSS
VSS
8 7 6 5 4 3 2 1
C3113
1
0.1UF
20%
6.3V
2 X6S-CERM
0204-1
1 C3130
2.2UF
20%
6.3V
2 CERM
402-LF
1
0.1UF
20%
6.3V
2 X6S-CERM
0204-1
1
1 C3136
0.1UF
20%
10V
2
CERM
402
C3114
C3131
0.1UF
20%
10V
2 CERM
402
MEM_A_DQ
MEM_A_DQ
MEM_A_DM
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQS_N
MEM_A_DQS_P
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQS_N
MEM_A_DQS_P
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DM
MEM_A_DQ
MEM_A_DQ
=PP0V75_S0_MEM_VTT_A
C3115
1
0.1UF
20%
6.3V
2 X6S-CERM
0204-1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
PP0V75_S3_MEM_VREFCA_A
C3116
1
0.1UF
20%
6.3V
2 X6S-CERM
0204-1
DDR3-SODIMM-DUAL-M97-3
(SYMBOL 1 OF 2)
KEY
516-0201
C3117
1
0.1UF
20%
6.3V
2 X6S-CERM
0204-1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
MEM_A_DQ
MEM_A_DQ
MEM_A_DQS_N
MEM_A_DQS_P
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DM
MEM_RESET_L
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQS_N
MEM_A_DQS_P
MEM_A_DQ
MEM_A_DQ
Preliminary
8C7
27C1
MEM_A_DM
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
BI
BI
BI
BI
IN
BI
BI
BI
BI
BI
BI
BI
BI
15B7 72D3
15B7 72D3
15D5 72C3
15D5 72C3
15B7 72D3
15B7 72D3
15B7 72D3
15B7 72D3
15A7 72C3
29C2 30C3
15B7 72D3
15B7 72D3
15C7 72D3
15C7 72D3
15A7 72C3
15C7 72D3
15C7 72D3
15B7 72D3
15B7 72D3
15D5 72C3
15D5 72C3
15B7 72D3
15C7 72D3
APPLE INC.
"Factory" (top) slot
SYNC_MASTER=BEN
DDR3 SO-DIMM Connector A
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
051-7537
SHT OF
31 109
SYNC_DATE=06/30/2008
REV.
A
D
C
B
A

D
C
B
A
- =PPSPD_S0_MEM_B (2.5 - 3.3V)
8 7 6 5 4 3 2 1
Power aliases required by this page:
- =PP1V5_S0_MEM_B
- =PP1V5_S3_MEM_B
Page Notes
- =PP0V75_S0_MEM_VTT_B
Signal aliases required by this page:
- =I2C_SODIMMB_SCL
- =I2C_SODIMMB_SDA
BOM options provided by this page:
(NONE)
8B5 =PPSPD_S0_MEM_B
1
R3240
10K
5%
1/16W
MF-LF
402
2
1
C3240
2.2UF
20%
6.3V
2
CERM
402-LF
72B3 15A1
72B3 15C1
72B3 15C1
72B3 15B1
72B3 15B1
72B3 15B1
72B3 15B1
72B3 15B1
72B3 15B1
72B3 15B1
72B3 15C1
72B3 15C1
72B3 15C1
72B3 15C1
72B3 15C1
72B3 15B1
72B3 15C3
72B3 15C3
72A3 15D1
72A3 15D1
72B3 15C3
72B3 15C3
72B3 15C3
72B3 15C3
72B3 15B3
72B3 15C3
72B3 15C3
72B3 15D3
72B3 15D3
72A3 15D1
72A3 15D1
72B3 15D3
72B3 15D3
72B3 15D3
72B3 15D3
72A3 15B3
72B3 15D3
72B3 15D3
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
BI
BI
MEM_B_CKE
MEM_B_BA
MEM_B_A
MEM_B_A
MEM_B_A
MEM_B_A
MEM_B_A
MEM_B_A
MEM_B_CLK_P
MEM_B_CLK_N
MEM_B_A
MEM_B_BA
MEM_B_WE_L
MEM_B_CAS_L
MEM_B_A
MEM_B_CS_L
MEM_B_DQ
MEM_B_DQ
MEM_B_DQS_N
MEM_B_DQS_P
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DM
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQS_N
MEM_B_DQS_P
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DM
MEM_B_DQ
MEM_B_DQ
R3241
10K
1
MEM_B_SA
MEM_B_SA
5%
1/16W
MF-LF
402
2
8D3 =PP1V5_S3_MEM_B
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
KEY
CKE0
CKE1
VDD
VDD
NC
BA2 J3200
A15
A14
VDD F-RT-BGA3 VDD
A12/BC*
A11
A9
A7
VDD
VDD
A8
A6
A5
A4
VDD
VDD
A3
A2
A1
A0
VDD
VDD
CK0
CK1
CK0*
CK1*
VDD
VDD
A10/AP
BA1
BA0
RAS*
VDD
VDD
WE*
S0*
CAS*
ODT0
VDD
VDD
A13
ODT1
S1*
NC
VDD
VDD
TEST
VREFCA
VSS
VSS
DQ32
DQ36
DQ33
DQ37
VSS
VSS
DQS4*
DM4
DQS4
VSS
VSS
DQ38
DQ34
DQ39
DQ35
VSS
VSS
DQ44
DQ40
DQ45
DQ41
VSS
VSS
DQS5*
DM5
DQS5
VSS
VSS
DQ42
DQ46
DQ43
DQ47
VSS
VSS
DQ48
DQ52
DQ49
DQ53
VSS
VSS
DQS6*
DM6
DQS6
VSS
VSS
DQ54
DQ50
DQ55
DQ51
VSS
VSS
DQ60
DQ56
DQ61
DQ57
VSS
VSS
DQS7*
DM7
DQS7
VSS
VSS
DQ58
DQ62
DQ59
DQ63
VSS
VSS
SA0
EVENT*
VDDSPD
SDA
SA1
SCL
VTT
VTT
DDR3-SODIMM
(2 OF 2)
205
207
MTG PINS
MTG PIN MTG PIN
MTG PIN MTG PIN
206
208
209
211
MTG PIN
MTG PIN
MTG PIN
MTG PIN
210
212
516S0706
SPD ADDR=0xA2(WR)/0xA3(RD)
1
C3200
10UF
20%
6.3V
2
X5R
603
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
1
C3201
10UF
20%
6.3V
2
X5R
603
MEM_B_CKE
MEM_B_A
MEM_B_A
MEM_B_A
MEM_B_A
MEM_B_A
MEM_B_A
MEM_B_A
MEM_B_A
1
0.1UF
20%
6.3V
2 X6S-CERM
0204-1
MEM_B_CLK_P
MEM_B_CLK_N
MEM_B_BA
MEM_B_RAS_L
MEM_B_CS_L
MEM_B_ODT
MEM_B_ODT
MEM_B_DQ
MEM_B_DQ
MEM_B_DM
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
DDR3 DECOUPLING AND GROUND RETURN CAPS (CONNECTOR SIDE)
C3210
MEM_B_DQS_N
MEM_B_DQS_P
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DM
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQS_N
MEM_B_DQS_P
MEM_B_DQ
MEM_B_DQ
MEM_EVENT_L
=I2C_SODIMMB_SDA
=I2C_SODIMMB_SCL
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
BI
BI
BI
BI
BI
BI
BI
BI
1
0.1UF
20%
6.3V
2 X6S-CERM
0204-1
OUT 21A4 21B3 28A5 39B8
BI
IN
C3211
15A1 72B3
15D1 72A3
15D3 72B3
15D3 72B3
42D6
42D6
1
C3250
2.2UF
20%
6.3V
2 CERM
402-LF
C3212
1
0.1UF
20%
6.3V
2 X6S-CERM
0204-1
27C1 PP0V75_S3_MEM_VREFDQ_B
9D2
15C1 72B3
15C1 72B3
15B1 72B3
15B1 72B3
15B1 72B3
15B1 72B3
15B1 72B3
15B1 72B3
15B1 72B3
15C1 72B3
15C1 72B3
15B1 72B3
15A1 72B3
15A1 72B3
15C3 72B3
15C3 72B3
15A3 72B3
15C3 72B3
15C3 72B3
15C3 72B3
15C3 72B3
15D1 72A3
15D1 72A3
15C3 72B3
15C3 72B3
15D3 72B3
15D3 72B3
15B3 72A3
15D3 72B3
15D3 72B3
15D3 72B3
15D3 72B3
15D1 72A3
1
2
BI
BI
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
BI
BI
VREFDQ
VSS
VSS
DQ4
DQ0
DQ1
CRITICAL
DQ5
VSS
VSS
DM0
DQS0*
J3200 DQS0
VSS
F-RT-BGA3
VSS
DQ2
DQ6
DQ3
DQ7
VSS
VSS
DQ8
DQ12
DQ9
DQ13
VSS
VSS
DQS1*
DM1
DQS1
RESET*
VSS
VSS
DQ10
DQ14
DQ11
DQ15
VSS
VSS
DQ16
DQ20
DQ17
DQ21
VSS
VSS
DQS2*
DM2
DQS2
VSS
VSS
DQ22
DQ18
DQ23
DQ19
VSS
VSS
DQ28
DQ24
DQ29
DQ25
VSS
VSS
DQS3*
DM3
DQS3
VSS
VSS
DQ26
DQ30
DQ27
DQ31
VSS
VSS
8 7 6 5 4 3 2 1
1
72B3 15B3
72B3 15B3
72B3 15A3
72B3 15B3
72B3 15B3
72B3 15B3
72B3 15B3
72A3 15D1
72A3 15D1
72B3 15B3
72B3 15B3
72B3 15B3
72B3 15B3
72A3 15D1
72A3 15D1
72B3 15C3
72B3 15B3
72B3 15C3
72B3 15C3
72B3 15A3
72B3 15C3
72B3 15C3
C3251
2.2UF
20%
6.3V
CERM
402-LF
C3213
0.1UF
20%
6.3V
2 X6S-CERM
0204-1
1
1 C3235
2.2UF
20%
6.3V
2
CERM
402-LF
C3230
2.2UF
20%
6.3V
2 CERM
402-LF
1 C3214
0.1UF
20%
6.3V
2 X6S-CERM
0204-1
1
0.1UF
20%
10V
2
CERM
402
C3231
0.1UF
20%
10V
2 CERM
402
MEM_B_DQ
MEM_B_DQ
MEM_B_DM
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQS_N
MEM_B_DQS_P
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQS_N
MEM_B_DQS_P
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DM
MEM_B_DQ
MEM_B_DQ
1
C3236
=PP0V75_S0_MEM_VTT_B
C3215
1
0.1UF
20%
6.3V
2 X6S-CERM
0204-1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
C3216
1
0.1UF
20%
6.3V
2 X6S-CERM
0204-1
DDR3-SODIMM
(1 OF 2)
KEY
516S0706
C3217
1
0.1UF
20%
6.3V
2 X6S-CERM
0204-1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
8B7 =PP1V5_S0_MEM_MCP
1
C3222
0.1UF
20%
6.3V
2 X6S-CERM
0204-1
MEM_B_DQ
MEM_B_DQ
MEM_B_DQS_N
MEM_B_DQS_P
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DM
MEM_RESET_L
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DM
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQ
MEM_B_DQS_N
MEM_B_DQS_P
MEM_B_DQ
MEM_B_DQ
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
BI
BI
BI
BI
IN
BI
BI
BI
BI
BI
BI
BI
BI
DDR3 GROUND RETURN CAPS (MCP SIDE)
Preliminary
PP0V75_S3_MEM_VREFCA_B
8C7
27C1
1
C3223
0.1UF
20%
6.3V
2 X6S-CERM
0204-1
1
15B3 72B3
15B3 72B3
15D1 72A3
15D1 72A3
15B3 72B3
15B3 72B3
15B3 72B3
15B3 72B3
15A3 72B3
28C2 30C3
15B3 72B3
15B3 72B3
15B3 72B3
15B3 72B3
15A3 72B3
15B3 72B3
15C3 72B3
15C3 72B3
15C3 72B3
15D1 72A3
15D1 72A3
15C3 72B3
15C3 72B3
C3224
0.1UF
20%
6.3V
2 X6S-CERM
0204-1
1
C3225
0.1UF
20%
6.3V
2 X6S-CERM
0204-1
SYNC_MASTER=BEN
APPLE INC.
C3226
1
0.1UF
20%
6.3V
2 X6S-CERM
0204-1
"Expansion" (bottom) slot
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
1
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
C3227
0.1UF
20%
6.3V
2 X6S-CERM
0204-1
DRAWING NUMBER
NONE
C3228
1
0.1UF
20%
6.3V
2 X6S-CERM
0204-1
DDR3 SO-DIMM Connector B
051-7537
SHT OF
32 109
C3229
1
0.1UF
20%
6.3V
2 X6S-CERM
0204-1
SYNC_DATE=05/09/2008
REV.
A
D
C
B
A

D
C
B
A
8 7 6 5 4 3 2 1
8D3 =PP1V5_S3_MEMRESET
8A3 =PP3V3_S5_MEMRESET
16C3 IN
DDR3 RESET Support
MCP79 cannot control this signal directly since it must be high in sleep and MCP MEM rails are not powered in sleep.
MCP_MEM_RESET_L
MEMRESET_HW
R3300
10K
5%
1/16W
MF-LF
402
1
2
MEMRESET_HW
R3301
20K
5%
1/16W
MF-LF
402
1
2
3.3V input must be stable before
before 1.5V starts to rise to
avoid glitch on MEM_RESET_L.
MEM_RESET_RC_L
MEMRESET_HW
1 C3300
0.1UF
20%
10V
2 CERM
402
5
MEMRESET_HW
1
R3305
20K
5%
1/16W
MF-LF
402
2
MEMRESET_HW
3
Q3305
MMDT3904-X-G
SOT-363-LF
4
8 7 6 5 4 3 2 1
MEM_RESET
2
1
R3310
1K
5%
1/16W
MF-LF
402
2
MEMRESET_HW
6
Q3305
MMDT3904-X-G
SOT-363-LF
1
MEMRESET_MCP
1
R3309
0
5%
1/16W
MF-LF
402
2
Preliminary
MEM_RESET_L
OUT 28C2 29C2
SYNC_MASTER=T18_MLB
APPLE INC.
DDR3 Support
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
051-7537
SYNC_DATE=04/04/2008
SHT OF
33 109
REV.
A
D
C
B
A

D
C
B
A
CRITICAL
518S0610
J3401
20347-325E-12
F-RT-SM
31
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
32
8 7 6 5 4 3 2 1
NC
NC
17C6 9C6
OUT PCIE_MINI_PRSNT_L
17C6 OUT
PCIE_MINI_D2R_P
PCIE_MINI_D2R_N
7D5 PCIE_MINI_R2D_P
7D5 PCIE_MINI_R2D_N
PCIE_CLK100M_MINI_CONN_P
PCIE_CLK100M_MINI_CONN_N
7C5 MINI_CLKREQ_Q_L
OUT
OUT
7D5 17B6 73D3
7D5 17B6 73D3
PCIE_WAKE_L OUT 7D5 17B6 23C5
73D3
73D3
73D3 7D5
73D3 7D5
MINI_CLKREQ_L
3 D Q3401
SSM6N15FEAPE
SOT563
S G 5
4
6 D Q3401
SSM6N15FEAPE
SOT563
S G 2
1
7D5 PP5V_S3_BTCAMERA_F
I2C_ALS_SDA BI
I2C_ALS_SCL IN
74C3 7D5 USB_CAMERA_CONN_P
74C3 7D5 USB_CAMERA_CONN_N
CONN_USB2_BT_P
CONN_USB2_BT_N
TC7SZ08AFEAPE 5
SOT665
7C5 MINI_RESET_CONN_L
4
Y
U3401
3
A
B
2
1
1 2 0.1uF
10% 16V X5R 402
C3430
42D1
42D1
=PP3V3_S3_WLAN
90-OHM-100MA
DLP11S
SYM_VER-1
90-OHM
DLP0NS
SYM_VER-1
90-OHM
DLP0NS
SYM_VER-1
2 0.1uF
16V X5R 402
IN
IN
PLACEMENT_NOTE=Place close to J3401.
10%
C3431
1
PLACEMENT_NOTE=Place close to J3401.
CRITICAL
4 3
1
L3401
PLACEMENT_NOTE=Place close to J3401.
4
CRITICAL
L3402
U3402
5
74LVC1G17DRL
SOT-553
WLAN_SMIT_BUF
4
2
3
1 2
4
MINI_RESET_L
AP_PWR_EN
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V
PLACEMENT_NOTE=Place close to J3401.
CRITICAL
L3403
3
1 2
PLACEMENT_NOTE=Place close to J3401.
8D3
26C1
3
NC
21A3 21B3 34C7
PCIE_MINI_R2D_C_P
PCIE_MINI_R2D_C_N
ALS
CAMERA
1
NC
C3453
1UF
AIRPORT
PCIE_CLK100M_MINI_P
PCIE_CLK100M_MINI_N
USB_CAMERA_P
USB_CAMERA_N
IN 17C3
73D3
IN 17C3
73D3
BLUETOOTH
2
1
10%
6.3V
CERM
2
402
USB_BT_P
USB_BT_N
PP5V_WLAN_F
1
R3453
33K
5%
1/16W
MF-LF
402
2
WLAN_SMIT_RC
1
R3454
62K
5%
1/16W
MF-LF
402
2
L3404
FERR-120-OHM-1.5A
1000 mA peak
750 mA nominal max
0402-LF
IN
IN
17B3 7D5 7C3 PP5V_WLAN
73D3
MIN_LINE_WIDTH=1 mm
17B3 73D3 MIN_NECK_WIDTH=0.5 mm
VOLTAGE=5V
2 1
C3422 1 C3421 1
0.1uF
0.1uF
20%
10V
CERM
402
2
20%
10V
CERM
2
402
275 mA peak
206 mA nominal max
OUT 20D3 74C3
OUT 20D3 74C3
31C3
BI
BI
C3452
1
0.1uF
20%
10V
CERM 2
402
20C3 74B3
20C3 74B3
PLACEMENT_NOTE=Place close to J3401.
FERR-120-OHM-1.5A
0402-LF
5V S3 WLAN FET
8 7 6 5 4 3 2 1
L3405
2 1
MOSFET
CHANNEL
RDS(ON)
LOADING
PLACEMENT_NOTE=Place close to Q3450.
PLACEMENT_NOTE=Place close to Q3450.
=PP5V_S3_BTCAMERA
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V
PP5V_WLAN_F
31A5
MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.5 mm
VOLTAGE=5V
1 C3420
10UF
20%
10V
2
X5R
805
FDC606P
P-TYPE
26 mOhm @4.5V
0.8 A (EDP)
6
5
2
1
FDC606P_G
D
C3450
0.1UF
1 2
10%
16V
X5R
402
Q3450
SOT-6
G
3
S
4
C3451
1
0.033UF
10%
16V
X5R
2
402
P5VWLAN_SS
Preliminary
8C3
R3450
100K
1
2
5%
1/16W
MF-LF
402
APPLE INC.
1
R3451
10K
5%
1/16W
MF-LF
402
2
SYNC_MASTER=YITE
=PP5V_S3_WLAN
MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.5 mm
VOLTAGE=5V
PM_WLAN_EN_L
SCALE
NONE
IN 34C6
Right Clutch Connector
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
DRAWING NUMBER
051-7537
8C3
SHT OF
34
SYNC_DATE=04/22/2008
REV.
A
109
D
C
B
A

D
C
B
A
8 7 6 5 4 3 2 1
73D3 9B5
73D3 9B5
IN
IN
PCIE_FC_R2D_C_P
PCIE_FC_R2D_C_N
9C5 OUT FC_CLKREQ_L
73D3 9B5 IN PCIE_CLK100M_FC_P
PLACEMENT_NOTE=Place close to J3501. 73C3 9B5 IN
C3573 VENICE
PCIE_CLK100M_FC_N
1 2
0.1uF
73D3 PCIE_FC_R2D_P
1 2 0.1uF 10% 16V X5R 402
73D3 PCIE_FC_R2D_N
10% 16V X5R 402
C3572 VENICE
73D3 9B5 OUT PCIE_FC_D2R_P
PLACEMENT_NOTE=Place close to J3501.
73D3 9B5 OUT PCIE_FC_D2R_N
8 7 6 5 4 3 2 1
CRITICAL
J3501
503219-0221
M-ST-SM
24
VENICE 23
1
3
5
7
9
11
13
15
17
19
21
25
26
NC
NC
NC
NC
Venice Connector
2
4
6
8
10
12
14
16
18
20
22
=PP3V3_FC_CON
=PP1V5_FC_CON
FC_PRSNT_L
FC_RESET_L
Preliminary
8B5
8B7
OUT 9C5
OUT 26C1
SYNC_MASTER=YITE
APPLE INC.
VENICE CONNECTOR
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
SYNC_DATE=03/13/2008
SHT OF
35 109
REV.
051-7537 A
D
C
B
A

D
C
B
A
8 7 6 5 4 3 2 1
75D3 18D3
Configuration Settings:
IN
5%
1/16W
402
MF-LF
PLACE R3796 CLOSE TO U1400, PIN D24
ENET_RESET_L IS NOT ASSERTED WHEN WOL IS ACTIVE.
HENCE, RC (C3725 AND R3725) ARE NOT STUFFED.
PHYAD = 01 (PHY Address 00001)
AN[1:0] = 11 (Full auto-negotiation)
RXDLY = 0 (RXCLK transitions with data)
TXDLY = 0 (No TXCLK Delay)
(43mA typ - 1000base-T)
(19mA typ - Energy Detect)
WF: Marvell numbers, update for Realtek
ENET_CLK125M_TXCLK
75C3 18C3
IN
8B1 =PP3V3_ENET_PHY
R3796
1 0 2
Alias to =PP3V3_ENET_PHY for internal switcher.
Alias to GND for external 1.05V supply.
IN
75C3 18D3 IN
R3724
ENET_RESET_L 1
0
2
RTL8211_PHYRST_L
5%
1/16W
MF-LF
1
402
0.1UF
20%
2
NO STUFF
10V
CERM
402
C3725
R3730
2.49K
1%
1/16W
MF-LF
402
1
2
1
2
CRITICAL
L3705
FERR-120-OHM-1.5A
0402-LF
PP3V3_ENET_PHYAVDD
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
9D2
75D3 ENET_CLK125M_TXCLK_R
75C3 18D3
75C3 18D3
75C3 18D3
75C3 18C3
75D3 18C3
75D3 18C3
75D3 34A3
IN
IN
IN
IN
IN
BI
IN
=RTL8211_ENSWREG
ENET_TXD
ENET_TXD
ENET_TXD
ENET_TXD
ENET_TX_CTRL
ENET_MDC
ENET_MDIO
RTL8211_RSET
TP_RTL8211_CLK125
1 C3700
0.1UF
10%
16V
2
X5R
402
1 C3705
0.1UF
10%
16V
2
X5R
402
RTL8211_CLK25M_CKXTAL1
TP_RTL8211_CKXTAL2
R3720
10K
5%
1/16W
MF-LF
402
1
2
C3701
1
0.1UF
10%
16V
2
X5R
402
1 C3706
0.1UF
10%
16V
2
X5R
402
1 C3702
0.1UF
10%
16V
2
X5R
402
NO STUFF
1
R3725
4.7K
5%
1/16W
MF-LF
402
2
39 ENSWREG
22
6
41
TXC
AVDD33
23
TXD[0]
24
TXD[1]
25
TXD[2]
26
TXD[3]
27
TXCTL
30
MDC
31
MDIO
29
46
32
PHYRSTB*
RSET
CLK125
42
CKXTAL1
43
CKXTAL2
15
21
37
DVDD33
C3714
0.1UF
10%
16V
X5R
402
1
2
44
45
VDDREG
MANAGEMENT
OMIT
CRITICAL
U3700
RGMII/MII
GND
FB12
RTL8211CLGR
TQFP
DVDD12
AVDD12
REGOUT
RXC
RXCTL
MDI+[1]
4
RESET MEDIA DEPENDENT
MDI-[1]
MDI+[2]
5
8
MDI-[2]
9
REFERENCE
MDI+[3]
11
MDI-[3]
12
CLOCK
LED
7
20
33
47
Reserved for EMI
per RealTek request.
8 7 6 5 4 3 2 1
3
28
36
10
40
C3710
0.1UF
10%
16V
X5R
402
1
2
C3715
0.1UF
10%
16V
X5R
402
1
2
R3750
4.7K
5%
1/16W
MF-LF
402
1
2
48
19
RXD[0]
14
RXD[1]/TXDLY
16
RXD[2]/AN0
17
RXD[3]/AN1
18
13
MDI+[0]
1
MDI-[0]
2
LED0/PHYAD0
34
LED1/PHYAD1
35
LED2/RXDLY
38
C3711
0.1UF
10%
16V
X5R
402
1
2
C3716
0.1UF
10%
16V
X5R
402
1
PP1V05_ENET_PHYAVDD
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
2
1
R3751
4.7K
5%
1/16W
MF-LF
402
2
NO STUFF
C3790
10PF
5%
50V
CERM
402
1
2
75D3 ENET_CLK125M_RXCLK_R
ENET_RXD_R
ENET_RXD_R
ENET_RXD_R
ENET_RXD_R
ENET_RXCTL_R
ENET_MDI_P
ENET_MDI_N
ENET_MDI_P
ENET_MDI_N
ENET_MDI_P
ENET_MDI_N
ENET_MDI_P
ENET_MDI_N
RTL8211_PHYAD0
RTL8211_PHYAD1
RTL8211_RXDLY
(221mA typ - 1000base-T)
( 7mA typ - Energy Detect)
1 WF: Marvell numbers, update for Realtek
CRITICAL
L3715
FERR-120-OHM-1.5A
0402-LF
R3755
4.7K
5%
1/16W
MF-LF
402
1
2
BI
BI
BI
BI
BI
BI
BI
BI
R3752
4.7K
5%
1/16W
MF-LF
402
1
2
35B7 75C3
35B7 75C3
35C7 75C3
35C7 75C3
35B7 75C3
35C7 75C3
35C7 75C3
35C7 75C3
2
R3756
4.7K
5%
1/16W
MF-LF
402
1
2
=PP1V05_ENET_PHY
1
=PP3V3_ENET_PHY_VDDREG
If internal switcher is used, must place 1x 22uF &
1x 0.1uF caps within 5mm of U3700 pins 44 & 45.
NOTE: VDDREG rise time must be >1ms to avoid damage to switcher.
=RTL8211_REGOUT
If internal switcher is used, must place inductor within 5mm
of U3700, and 1x 22uF & 1x 0.1uF caps within 5mm of inductor.
If internal switcher is not used, VDDREG and REGOUT can float.
R3790 22 1 2
R3791 22 1 2
R3792 22 1 2
R3793 22 1 2
R3794 22 1 2
R3795 22 1 2
Preliminary
75D3
75D3
75D3
75D3
75D3
R3757
4.7K
5%
1/16W
MF-LF
402
2
8B1
5% 1/16W
5%
5%
5%
5%
5%
9D2
9D2
1/16W
1/16W
1/16W
1/16W
1/16W
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
402
402
402
402
402
402
SYNC_MASTER=SUMA
APPLE INC.
ENET_CLK125M_RXCLK
ENET_RXD
ENET_RXD
ENET_RXD
ENET_RXD
ENET_RX_CTRL
SCALE
NONE
OUT 18D6 75D3
OUT 18D6 75D3
OUT 18D6 75D3
OUT 18D6 75D3
OUT 18D6 75D3
OUT 18D6 75D3
Ethernet PHY (RTL8211CL)
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
DRAWING NUMBER
051-7537
SYNC_DATE=05/23/2008
SHT OF
37 109
REV.
A
D
C
B
A

D
C
B
A
8 7 6 5 4 3 2 1
31D5 21B3 21A3
40B2 39D5 21C7
68D8 64D5 41A5 39C5 21C3 7C3
IN
IN
IN
WLAN Enable Generation
"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))
NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.
AP_PWR_EN
SMC_ADAPTER_EN
PM_SLP_S3_L
Q3805
SSM6N15FEAPE
SOT563
2 G
Q3805
SSM6N15FEAPE
SOT563
5 G
D 6
S 1
D 3
S 4
PM_WLAN_EN_L OUT 31C1
Pull-up is with power FET.
AC_OR_S0_L
6 D
Q3801
S G 2
1
SSM6N15FEAPE
SOT563
IN
IN
MOBILE:
Non-ARB:
5 G
5 G
D 3
S 4
IN MCP_CLK25M_BUF0_R 1
22
5%
1/16W
MF-LF
402
2 RTL8211_CLK25M_CKXTAL1
OUT 33B6 75D3
PLACEMENT_NOTE=Place close to U1400
8 7 6 5 4 3 2 1
D 3
S 4
Recommend aliasing PM_SLP_RMGT_L and
=P3V3ENET_EN. Nets separated on
ARB for alternate power options.
Recommend aliasing PM_SLP_RMGT_L and
=P1V05ENET_EN. Nets separated on
ARB for alternate power options.
RTL8211 25MHz Clock
3.3V ENET FET
@ 2.5V Vgs:
Rds(on) = 90mOhm max
I(max) = 1.7A (85C)
NOTE: MCP79 can provide 25MHz clock, but clock runs whenever RMGT rails are powered.
Designs must ensure PHY is powered whenever RMGT rails are, or use separate crystal.
75D3 18C3
9D2
8A3 =PP3V3_S5_P3V3ENETFET
9D2
=P3V3ENET_EN
8A3 =PP3V3_S5_P1V05ENETFET
=P1V05ENET_EN
1
R3842
69.8K
1%
1/16W
MF-LF
402
2
R3895
1
R3800
10K
5%
1/16W
MF-LF
402
2
Q3801
SSM6N15FEAPE
SOT563
Q3841
SSM6N15FEAPE
SOT563
P3V3ENET_EN_L
R3810
100K
1
2
5%
1/16W
MF-LF
402
8B3 =PP1V05_ENET_P1V05ENETFET
P1V05ENET_EN_L
R3840
100K
1 2
5%
1/16W
MF-LF
402
1 C3811
0.033UF
10%
16V
2 X5R
402
2 G
D 6
S 1
CRITICAL
Q3810
NTR4101P
SOT-23-HF
G
S
G
1.05V ENET FET
P1V05ENET_SS
R3841
10K
1
2
1%
1/16W
MF-LF
402
1 C3840
0.1UF
20%
10V
CERM 2
402
Q3841
SSM6N15FEAPE
SOT563
P3V3ENET_SS
P1V05ENET_EN_L_RC
1
2
1
D
S
D
3
C3810
0.01UF
2 1
3
2
10%
16V
CERM
402
1.8V Vgs
CRITICAL
Q3840
SI2312BDS
SOT23
1 C3841
0.01UF
10%
16V
2
CERM
402
=PP3V3_ENET_FET
=PP1V05_ENET_FET
Preliminary
8B2
8B2
APPLE INC.
Ethernet & AirPort Support
SYNC_MASTER=SUMA SYNC_DATE=07/01/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
SHT OF
38
REV.
051-7537 A
109
D
C
B
A

D
C
B
A
8 7 6 5 4 3 2 1
- COPY THIS PAGE FROM K36 CSA.39
75C3 33B3 BI
75C3 33B3
75C3 33B3
75C3 33B3
75C3 33B3
75C3 33B3
75C3 33B3
75C3 33B3
BI
BI
BI
BI
BI
BI
BI
ENET_MDI_P
ENET_MDI_N
ENET_MDI_P
ENET_MDI_N
ENET_MDI_N
ENET_MDI_P
ENET_MDI_N
ENET_MDI_P
ENET_CONN_CTAP
1
2
3
4
5
6
1
2
3
4
5
6
CRITICAL
T3901
TX
TX
SM
TLA-6T213HF
RX
CRITICAL
T3902
SM
RX
1 C3900
0.1UF
10%
16V
2 X5R
402
TLA-6T213HF
PLACE ONE CAP EACH NEAR PINS 3 AND 4 OF T3901 AND T3902
12
11
10
9
8
7
12
11
9
8
7
1 C3901
0.1UF
10%
16V
2 X5R
402
ENET_CENTER_TAP
1% 1/16W
1 C3902
0.1UF
10%
16V
2 X5R
402
1R3903
MF-LF
1%
ENET_CENTER_TAP 2
1/16W 402
1R3902
1R3901
1R3900
75
75
2
MF-LF 402
10 ENET_CENTER_TAP 2 75
1% 1/16W MF-LF 402
75
ENET_CENTER_TAP 2
1% 1/16W MF-LF 402
1 C3903
0.1UF
10%
16V
2 X5R
402
75C3
75C3
ENET_MDI_TRAN_P
ENET_MDI_TRAN_N
ETHERNET CONNECTOR
8 7 6 5 4 3 2 1
75C3
75C3
ENET_MDI_TRAN_P
ENET_MDI_TRAN_N
75C3
75C3
75C3
75C3
ENET_MDI_TRAN_N
ENET_MDI_TRAN_P
ENET_MDI_TRAN_N
CRITICAL
1 C3910
1000PF
10%
2KV
2 CERM
1206
ENET_MDI_TRAN_P
ENET_BOB_SMITH_CAP
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM
J3900
RJ45-M97-2
F-RT-TH
9
10
1
2
3
4
5
6
7
8
11
12
CRITICAL
514-0596
Preliminary
SYNC_MASTER=SUMA
APPLE INC.
ETHERNET CONNECTOR
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
051-7537
SHT OF
39
SYNC_DATE=04/04/2008
REV.
109
A
D
C
B
A

D
C
B
A
8 7 6 5 4 3 2 1
CRITICAL
J4501
20374020E31
F-ST-SM
21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
22
518S0654
NC
NC
NC
NC
NC
NC
ODD Power Control
CRITICAL
Q4590
FDC606P_G
SOT-6
NOTE: 3.3V must be S0 if 5V is S3 or S5 to
1 C4595
ensure the drive is unpowered in S3/S5.
0.068UF
10%
10V
2 CERM
C4596
402
0.01UF
1 2
10%
16V
D
CERM
402
G S
D
G S
21B3 IN
SATA ODD Port
FL4520
PLACEMENT_NOTE=PLACE C4520 CLOSE TO MCP79
90-OHM-100MA
DLP11S
PLACEMENT_NOTE=PLACE C4521 NEXT TO C4520
SYM_VER-1
CRITICAL
3 4
1 2 C4521
IN
0.01UF 10% 16V CERM 402
2
1
1 2 C4520
IN 20D6 73A3
J4500
CRITICAL 55560-0168
0.01UF 10% 16V CERM 402
M-ST-SM-LF
2 1
PLACEMENT_NOTE=Place FL4520 close to J4500
4 3
6 5
8 7
10 9
12 11
PLACEMENT_NOTE=PLACE C4526 CLOSE TO J4500
FL4525
90-OHM-100MA
33K
14 13
PLACEMENT_NOTE=PLACE C4525 NEXT TO C4526
DLP11S
SYM_VER-1
1/16W
16 15
C4526 1 2
4
CRITICAL
MF-LF
3
OUT 20D6 73A3
0.01UF 10% 16V CERM 402
516S0617
C4525 1 2
1 2
OUT 20D6 73A3
OUT
0.01UF 10% 16V CERM 402
PLACEMENT_NOTE=Place FL4525 close to J4500
Indicates disc presence
SATA HDD Port
SYM_VER-1
C4510 1 2
IN 20D6 73A3
0.01UF 10% 16V CERM 402
C4511 1 2
IN 20D6 73A3
10% 16V CERM 402
5%
R4590
402
1
7C3 7B7 PP5V_SW_ODD
8D5 =PP5V_S0_ODD
MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.4mm
VOLTAGE=5V
R4596
100K
5%
1/16W
MF-LF
36B7 8C5 =PP3V3_S0_ODD
402
R4595
100K
ODD_PWR_EN_LS5V_L
1 2 ODD_PWR_SS
R4597
5%
100K
1/16W
5%
6
MF-LF
1/16W
Q4596
402
MF-LF
402 SSM6N15FEAPE
SOT563
ODD_PWR_EN
2
1
3
Q4596
SSM6N15FEAPE
SOT563
5
4
ODD_PWR_EN_L
73A3 SATA_ODD_R2D_UF_P
SATA_ODD_R2D_C_P
20D6 73A3
73A3 SATA_ODD_R2D_UF_N
SATA_ODD_R2D_C_N
73A3 7B7 SATA_ODD_R2D_P
36D5 8C5 =PP3V3_S0_ODD
73A3 7C5 7B7 SATA_ODD_R2D_N
73A3 7B7 SATA_ODD_D2R_C_N
73A3 7B7 SATA_ODD_D2R_C_P
73A3 SATA_ODD_D2R_UF_N
SATA_ODD_D2R_N
2
73A3 SATA_ODD_D2R_UF_P
SATA_ODD_D2R_P
39B8 7B7 SMC_ODD_DETECT
1 C4501
1 C4502
0.1UF
0.1UF
20%
20% PLACEMENT_NOTE=PLACE C4501 CLOSE TO J4501
2
10V
2
10V
CERM
CERM PLACEMENT_NOTE=PLACE C4502 CLOSE TO J4501
402 CRITICAL
402
Preliminary
L4500
FERR-70-OHM-4A
7C5 7C3 PP5V_S0_HDD_FLT
1
2
=PP5V_S0_HDD 8D5
0603
PLACEMENT_NOTE=PLACE L4500 CLOSE TO J4501 FL4501
PLACEMENT_NOTE=Place C4510 close to MCP79
90-OHM-100MA
PLACEMENT_NOTE=Place C4511 next to C4510
DLP11S
CRITICAL
3 4
73A3 SATA_HDD_R2D_UF_P
SATA_HDD_R2D_C_P
73A3 7C5 SATA_HDD_R2D_P
2
1
73A3 SATA_HDD_R2D_UF_N
SATA_HDD_R2D_C_N
73A3 7C5 SATA_HDD_R2D_N
73A3 7C5 SATA_HDD_D2R_C_N
73A3 7C5 SATA_HDD_D2R_C_P
PLACEMENT_NOTE=Place FL4501 close to J4501
C4515
0.01UF
C4516
0.01UF
1
1
2
73A3 SATA_HDD_D2R_UF_N
10% 16V CERM 402
2
73A3 SATA_HDD_D2R_UF_P
10% 16V CERM 402
PLACEMENT_NOTE=Place C4515 next to C4516
PLACEMENT_NOTE=Place C4516 close to J4501
FL4502
0.01UF
90-OHM-100MA
DLP11S
SYM_VER-1
CRITICAL
4
3
1 2
PLACEMENT_NOTE=PLACE FL4502 CLOSE TO J4501
8 7 6 5 4 3 2 1
SATA_HDD_D2R_N
SATA_HDD_D2R_P
OUT 20D6 73A3
OUT 20D6 73A3
4
S
G
3
D
1 2 5 6
APPLE INC.
SATA Connectors
SYNC_MASTER=CHANGZHANG SYNC_DATE=04/14/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
SHT OF
45
REV.
051-7537 A
109
D
C
B
A

D
C
B
A
IN
OUT
BI
BI
8 7 6 5 4 3 2 1
20C2 OUT
We can remove C4690 later if the output cap of the 5V_S5 regulator is close enough.
41C3 40B2 39C5 39B8
41C5 40B2 39C5 39B8
USB/SMC Debug Mux
8D1 =PP3V42_G3H_SMCUSBMUX
74C3 20D3
74C3 20D3
SMC_RX_L
SMC_TX_L
USB_EXTA_P
USB_EXTA_N
SMC_DEBUG_YES
1 C4650
0.1UF
20%
10V
CERM 2
402
SMC_DEBUG_NO
R4651
0
1 2
5%
1/16W
MF-LF
402
VCC
5 SMC_DEBUG_YES
M+
Y+ 1
4 M-
Y- 2
U4650
PI3USB102ZLE
7 D+
TQFN
6 D-
CRITICAL
8
OE*
64C6
GND
IN
STUFF R4691 IF USING TPS2060(ACTIVE LOW ENABLE)
STUFF R4690 IF USING TPS2064(ACTIVE HIGH ENABLE)
9
3
SMC_DEBUG_NO
R4652
0
1
2
8C3 =PP5V_S3_EXTUSB
5%
1/16W
MF-LF
402
USB_EXTA_OC_L
20C2 OUT USB_EXTB_OC_L
=USB_PWR_EN
SEL 10
NOSTUFF
1
C4690
10UF
20%
6.3V
X5R
2
603
Port Power Switch
R4690
0
1
5%
1/16W
MF-LF
402
1
R4650
10K
5%
1/16W
MF-LF
2
402
2
0.1UF
20%
10V
2
CERM
402
SEL=0 Choose SMC
SEL=1 Choose USB
1
C4691
USB_DEBUGPRT_EN_L
USB_PWR_EN_R
TPS2064DGN
2
IN
7
OUT1
MSOP
8
OC1*
3
EN1 OUT2
6
5
OC2*
4
EN2
1 NOSTUFF
R4691
0
5%
1/16W
MF-LF
2
402
CRITICAL
U4690
GND TPAD
1 9
CAN NOSTUFF C4696 AND C4616 AFTER CHARACTERIZATION
IN 39B8
C4695
X5R
603
1
10UF
20%
6.3V
2
PP5V_S3_RTUSB_A_ILIM
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.5 mm
VOLTAGE=5V
PP5V_S3_RTUSB_B_ILIM
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.5 mm
VOLTAGE=5V
1
CRITICAL
C4696
100UF
20%
2 6.3V
POLY-TANT
CASE-B2-SM
C4617
10UF
20%
6.3V
X5R
603
1
2
1
CRITICAL
C4616
100UF
20%
2 6.3V
POLY-TANT
CASE-B2-SM
74C3 USB_EXTA_MUXED_N
USB PORT A (FRONT PORT)
PLACEMENT_NOTE=NEAR J4600
CRITICAL
L4605
FERR-220-OHM-2.5A
8 7 6 5 4 3 2 1
C4605
1
0.01uF
20%
16V
CERM
2
402
1
0603
PLACEMENT_NOTE=NEAR J4600
CRITICAL
4
L4600
90-OHM
DLP0NS
SYM_VER-1
74C3 USB_EXTA_MUXED_P
1
2 74C3 CONN_USB_EXTA_P
74B3 20C3 BI USB_EXTB_N
74B3 20C3 BI USB_EXTB_P
2
3
90-OHM
DLP0NS
SYM_VER-1
6 VBUS
1 GND
NC
IO
NC
IO
PLACEMENT_NOTE=NEAR J4610
CRITICAL
CRITICAL
We can add protection to 5V if we want, but leaving NC for now
L4615
FERR-220-OHM-2.5A
1 2 PP5V_S3_RTUSB_B_F
Place L4600 and L4605 at connector pin
0603
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.5 mm
1 C4615
0.01uF
20%
VOLTAGE=5V
2
16V
CERM
402
CRITICAL
PLACEMENT_NOTE=NEAR J4610
CRITICAL
4
1
PP5V_S3_RTUSB_A_F
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.5 mm
VOLTAGE=5V
74C3 CONN_USB_EXTA_N
L4610
3
2
D4600
RCLAMP0502N
SLP1210N6
6 VBUS
1 GND
2 5 3
NC
IO
NC
IO
USB PORT B (BACK PORT)
4
74B3 CONN_USB_EXTB_N
74B3 CONN_USB_EXTB_P
2 5 3 4
D4610
RCLAMP0502N
SLP1210N6
CRITICAL
CRITICAL
J4600
USB
F-RT-TH-M97-3
5
6
1
2
3
4
7
8
514-0606
J4610
USB
F-RT-TH-M97-3
5
Preliminary
6
1
2
3
4
7
8
514-0606
APPLE INC.
External USB Connectors
SYNC_MASTER=YUAN.MA
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
SHT OF
46
SYNC_DATE=01/18/2008
REV.
051-7537 A
109
D
C
B
A

D
C
B
A
8 7 6 5 4 3 2 1
74B3 20D3
74B3 20D3
BI
BI
38B4 8C3 =PP5V_S3_IR
DIFFERENTIAL_PAIR=USB2_IR
DIFFERENTIAL_PAIR=USB2_IR
USB_IR_P
USB_IR_N
1 C4801
0.1UF
10%
16V
2
X7R-CERM
402
IR_VREF_FILTER
1 C4803
1UF
10%
10V
2 X5R
402-1
CRITICAL
14 P1_0/D+
15 P1_1/D-
18 P1_2/VREG
20 P1_3/SSEL
23 P1_4/SCLK
24 P1_5/SMOSI
25 P1_6/MISO
26 P1_7
21 P3_0
22 P3_1
27
28
29
NC
30
31
J4800
FF18-6A-R11AD-B-3H
F-RT-SM
1
2
3
4
5
6
16
VDD
U4800
CY7C63833
CRITICAL
OMIT
P/N 338S0375
THRM_PAD VSS
33
QFN
C4805
1
0.1UF
10%
16V
2 X7R-CERM
402
13
P0_0 7
P0_1 6
P0_2/INT0 5
P0_3/INT1 4
P0_4/INT2 3
P0_5/TIO0 2
P0_6/TIO1 1
P0_7 32
P2_0 9
P2_1 8
10
11
12
NC
17
CYPRESS ’ENCORE II’ USB CONTROLLER
7A7 PP3V42_G3H_LIDSWITCH_R
19
C4806
1
0.1UF
10%
16V
2 X7R-CERM
402
R4800
100
IR_RX_OUT_RC 1
2 IR_RX_OUT
5%
1/16W
MF-LF
402
8 7 6 5 4 3 2 1
IN 7A7 38A4
PLACE R4805 NEAR J4800
PLACE R4806 NEAR J4800
R4805 PLACE R4807 NEAR J4800
PLACE R4808 NEAR J4800
10
1 2
=PP3V42_G3H_LIDSWITCH 8D1
1/16W 402
5%
MF-LF R4806
10
1 2
=PP5V_S3_IR 8C3 38D7
1/16W 402
5% R4807
MF-LF 100
1 2 R4808
SMC_LID 39B5 40C2 47A5
1/16W
402 4.7
5%
1 2 SYS_LED_ANODE 40A6
MF-LF
1/16W
402
5%
MF-LF
IR_RX_OUT 7A7 38C4
C4807
1
0.001UF
10%
50V
2 CERM
402
1 C4804
0.001UF
10%
50V
2 CERM
402
Preliminary
518S0692
7A7
7A7
7A7
PP5V_S3_IR_R
SMC_LID_R
SYS_LED_ANODE_R
C4808
1
0.001UF
10%
50V
2 CERM
402
PLACE C4805 NEAR J4800
PLACE C4806 NEAR J4800
PLACE C4807 NEAR J4800
PLACE C4808 NEAR J4800
SYNC_MASTER=YUAN.MA
APPLE INC.
Front Flex Support
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
SHT OF
48
SYNC_DATE=05/28/2008
REV.
051-7537 A
109
D
C
B
A

D
C
B
A
8 7 6 5 4 3 2 1
NOTE: Unused pins have "SMC_Pxx" names. Unused
pins designed as outputs can be left floating,
those designated as inputs require pull-ups.
(DEBUG_SW_1)
(DEBUG_SW_2)
64A4 26A8
23C5 21B7
40D5 OUT
40C5 OUT
64B1
74C3 41D5 19B3
74C3 41D5 19B3
74C3 41D3 19B3
74C3 41D3 19B3
74C3 41D5 19C3
41D3 19B7
41C5 40B2 39C5 37A8
41C3 40B2 39C5 37A8
29A5 28A5 21B3 21A4
56C2 40B2
IN
IN
21B7 OUT
60C7 OUT
OUT
40D5 OUT
26D1
74C3 26C1
BI
BI
BI
BI
IN
IN
IN
BI
40D5 OUT
48A6 OUT
OUT
IN
42D6 BI
23B5 21C7
46B5 OUT
40D5 OUT
40D5 OUT
40D5 OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
SMC_PB3:
NC
NC
NC
NC
NC
NC
NC
(OC)
NC
NC
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
NC
23C5 21C7 OUT SMC_RUNTIME_SCI_L
36B7 7B7 IN SMC_ODD_DETECT
40C5 SMC_PB3 (See below)
40A2 IN SMC_EXCARD_CP
NC
40B5 IN SMC_EXCARD_OC_L
40B2 IN SMC_GFX_OVERTEMP_L
46C5
40B2
40B2
40B2
49B4
49B4
49B4
40C5
40D5
40D5
40D5
40C5
SMC_EXCARD_PWR_EN
SMC_RSTGATE_L
ALL_SYS_PWRGD
RSMRST_PWRGD
PM_RSMRST_L
IMVP_VR_ON
PM_PWRBTN_L
ESTARLDO_EN
40D5 SMC_P24
40D5 SMC_P26
LPC_AD
LPC_AD
LPC_AD
LPC_AD
LPC_FRAME_L
SMC_LRESET_L
LPC_CLK33M_SMC
LPC_SERIRQ
42B5 BI
40D5 SMC_P41
SMB_MGMT_DATA
49B7 OUT SMS_ONOFF_L
SMC_GFX_THROTTLE_L
SMC_SYS_KBDLED
SMC_TX_L
SMC_RX_L
SMB_0_S0_CLK
26B3 OUT
40C2 SMC_PA0
40C2 SMC_PA1
PM_SYSRST_L
37A6 OUT USB_DEBUGPRT_EN_L
BI MEM_EVENT_L
40A2 SMC_PA5
BI SYS_ONEWIRE
OUT PM_BATLOW_L
SMC_FAN_0_CTL
SMC_FAN_1_CTL
SMC_FAN_2_CTL
SMC_FAN_3_CTL
SMC_FAN_0_TACH
SMC_FAN_1_TACH
SMC_FAN_2_TACH
SMC_FAN_3_TACH
SMS_X_AXIS
SMS_Y_AXIS
SMS_Z_AXIS
SMC_ANALOG_ID
SMC_NB_CORE_ISENSE
SMC_NB_DDR_ISENSE
ALS_LEFT
ALS_RIGHT
SMC_IG_THROTTLE_L for MG systems.
Otherwise, TP/NC okay (was ISENSE_CAL_EN)
M10 PD0
N9 PD1
K10 PD2
L8 PD3
M9 PD4
N8 PD5
K9 PD6
L7 PD7
U4900
B12 P10
HS82117
P60 L13
A13 P11
LGA-HF
P61 K12
A12 P12
(1 OF 3)
P62 K11
B13 P13
OMIT
P63 J12
D11 P14
P64 K13
C13 P15
P65 J10
C12 P16 P66 J11
D10 P17
P67 H12
D13 P20
E11 P21
D12 P22
F11 P23
E13 P24
E12 P25
F13 P26
E10 P27
A9 P30
D9 P31
C8 P32
B7 P33
A8 P34
D8 P35
D7 P36
D6 P37
D4 P40
A5 P41
B4 P42
A1 P43
C2 P44
B2 P45
C1 P46
C3 P47
G2 P50
F3 P51
E4 P52
N3 PA0
N1 PA1
M3 PA2
M2 PA3
N2 PA4
L1 PA5
K3 PA6
L2 PA7
B8 PB0
C9 PB1
B9 PB2
A10 PB3
C10 PB4
B10 PB5
C11 PB6
A11 PB7
G11 PC0
G13 PC1
F12 PC2
H13 PC3
G10 PC4
G12 PC5
H11 PC6
J13 PC7
U4900
HS82117
LGA-HF
(2 OF 3)
OMIT
P70 N10
P71 M11
P72 L10
P73 N11
P74 N12
P75 M13
P76 N13
P77 L12
P80 A7
P81 B6
P82 C7
P83 D5
P84 A6
P85 B5
P86 C6
P90 J4
P91 G3
P92 H2
P93 G1
P94 H4
P95 G4
P96 F4
P97 F1
PE0 K1
PE1 J3
PE2 K2
PE3 J1
PE4 K4
PF0 K5
PF1 N5
PF2 M6
PF3 L5
PF4 M5
PF5 N4
PF6 L4
PF7 M4
PG0 M8
PG1 N7
PG2 K8
PG3 K7
PG4 K6
PG5 N6
PG6 M7
PG7 L6
PH0 E2
PH1 F2
PH2 J2
PH3 A4
PH4 B3
PH5 C4
NC
NC
(OC)
(OC)
NC
NC
NC
NC
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
NC
NC
SMC_PM_G2_EN
NC
NC
NC
SMC_ADAPTER_EN
SMC_PROCHOT_3_3_L
SMC_BIL_BUTTON_L
SMC_CPU_ISENSE
SMC_CPU_VSENSE
SMC_GPU_ISENSE
SMC_GPU_VSENSE
SMC_DCIN_ISENSE
SMC_PBUS_VSENSE
SMC_BATT_ISENSE
SMC_NB_MISC_ISENSE
SMC_WAKE_SCI_L
PM_CLKRUN_L
LPC_PWRDWN_L
SMC_TX_L
SMC_RX_L
SMB_MGMT_CLK
SMC_ONOFF_L
SMC_BC_ACOK
SMC_BS_ALRT_L
PM_SLP_S3_L
PM_SLP_S4_L
PM_SLP_S5_L
PM_CLK32K_SUSCLK
SMB_0_S0_DATA
SMC_CASE_OPEN
SMC_TCK
SMC_TDI
SMC_TDO
SMC_TMS
SMC_SYS_LED
SMC_LID
NC
NC
SMC_MCP_SAFE_MODE
=SMC_SMS_INT
SMB_BSA_DATA
SMB_BSA_CLK
SMB_A_S3_DATA
SMB_A_S3_CLK
SMB_B_S0_DATA
SMB_B_S0_CLK
SMC_PROCHOT
SMC_THRMTRIP
SMC_PH2
ALS_GAIN
OUT 7C3 64D8
OUT 21C7 34B7 40B2
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT 21C7 23C5
OUT 19B7 41D5
IN 19C3 41D3
OUT 37A8 39B8 40B2 41C5
IN
BI
IN
IN
IN
IN
IN
IN
IN
BI
IN
IN
IN
OUT 40B2 41C5
IN
OUT 40A8
IN
OUT 23B4
IN
BI
BI
BI
BI
BI
BI
40D1
56B1
44B1
43D6
40B2
40D5
44B1
43B4
44A4
40B2
OUT 40C2
OUT 40C2
OUT 40C5
37A8 39B8 40B2 41C3
42B5
40A3 40C2 40C7 47C3
40B2 40D5 56C1
7A7 40B2 56A8
7C3 21C3 34B7 41A5 64D5 68D8
7C3 21C3 40A2 64C8
40A2
26B1 74A3
42D6
40B2
40B2 41C3
40B2 41D3
40B2 41D5
38B4 40C2 47A5
40B5
42C6
42C6
42D3
42D3
42C3
42C3
40B6 7C3 PP3V3_S5_AVREF_SMC
49D7 40D8 40C7 40C1 8D1 =PP3V3_S5_SMC
NOTE: P94 and P95 are shorted, P95 could be spare.
NOTE: SMS Interrupt can be active high or low, rename net accordingly.
If SMS interrupt is not used, pull up to SMC rail.
8 7 6 5 4 3 2 1
C4902
22UF
20%
6.3V
CERM
805
1
2
C4903
1
0.1UF
20%
10V
2
CERM
402
R4999
4.7
1 2
5%
1/16W
MF-LF
402
C4920
0.1UF
20%
10V
CERM
402
1
PP3V3_S5_SMC_AVCC
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V
2
PLACEMENT_NOTE=Place R4999 close to U4900 pins N14,N15
PLACEMENT_NOTE=Place C4920 close to U4900 pins N14,N15
41C3 40D6
1
0.1UF
20%
10V
2
CERM
402
IN
C4904
SMC_RESET_L
40A6 SMC_XTAL
40A6 SMC_EXTAL
C4905
1
0.1UF
20%
10V
2
CERM
402
C4906
1
0.1UF
20%
10V
2
CERM
402
D3
M12
AVCC
RES*
A3 XTAL
A2 EXTAL
D2
L3
B1
VSS
F10
M1
H10
VCC
U4900
HS82117
LGA-HF
E1
(3 OF 3)
OMIT
B11
C5
VCL AVREF
NC
NMI
ETRST
AVSS
XW4900
2
L11
MD1 D1
MD2 H1
SM
1
PLACEMENT_NOTE=Place C4907 close to U4900 pin F1
SMC_VCL
E5
E3
H3
L9
C4907
0.47UF
10%
6.3V
CERM-X5R
402
1
2
NC
1
SMC_KBC_MDE
R4902
10K
5%
1/16W
MF-LF
2
402
GND_SMC_AVSS
Preliminary
40B2
APPLE INC.
R4909
10K
5%
1/16W
MF-LF
402
1
2
1
R4998
10K
5%
1/16W
MF-LF
2
402
SYNC_MASTER=T18_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
1
R4901
10K
5%
1/16W
MF-LF
2
402
NO STUFF
1
R4903
0
5%
1/16W
MF-LF
2
402
DRAWING NUMBER
NONE
SMC_MD1
SMC_NMI
40B6 43B5 43C6 43D6 44A1
SMC_TRST_L
SMC
IN
IN
IN
44A4 44B2 44B5 44C5 44D5
SHT OF
49
41C5
41C3
41C5
SYNC_DATE=06/26/2008
REV.
051-7537 A
109
D
C
B
A

D
C
B
A
SILK_PART=SMC_RST
8 7 6 5 4 3 2 1
49D7 40C7 40C1 39D4 8D1 =PP3V3_S5_SMC
IN
SMC Reset "Button" / Brownout Detect
2 G
IN
D 6
S 1
CD
NC
GND
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
PART NUMBER
39B5
SMC_MANUAL_RST_L
NOSTUFF
1
R5001
0
5%
1/10W
MF-LF
603
2
8D1 =PPVIN_S5_SMCVREF
OUT
IN
GND
OUT
System (Sleep) LED Circuit
1
R5031
523
1%
1/16W
MF-LF
402
2
1
R5032
1.47K
1%
1/16W
MF-LF
402
2
1 C5000
0.1uF
20%
10V
2
CERM
402
1 C5001
0.01UF
10%
16V
CERM
2
402
1
R5030
20
1%
1/16W
MF-LF
2
402
Q5032
SSM6N15FEAPE
SOT563
NC
02
SMC AVREF Supply
1
1 C5020
0.47UF
10%
6.3V
2
CERM-X5R
402
5
4
CRITICAL
VR5020
REF3333
SOT23-3
3
1
CRITICAL
U5000
NCP303LSN
SOT23-5-HF
1
2
2
1 C5025
10uF
20%
6.3V
2
X5R
603
353S1381 353S1278 ALL Intersil ISL60002-33
8C3 =PP5V_S3_SYSLED
SMC_SYS_LED
49D7 40D8 40C1 39D4 8D1 =PP3V3_S5_SMC
47B1 SMC_TPAD_RST_L
47C3 40C2 40A3 39C5 SMC_ONOFF_L
SYS_LED_ILIM
SYS_LED_L_VDIV
SYS_LED_L
3
2
3
5
3
TABLE_ALT_HEAD
TABLE_ALT_ITEM
SOD
1
2
U5001
SN74LVC1G02
SOT553-5
4 SMC_TPAD_RST
1 C5026
0.01UF
10%
16V
2
CERM
402
2SA2154MFV-YAE
Q5030
1
R5000
1K
5%
1/16W
MF-LF
402
2
Q5032
SSM6N15FEAPE
PP3V3_S5_AVREF_SMC
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
GND_SMC_AVSS
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
SYS_LED_ANODE
SMC_RESET_L
OUT 39C3 41C3
SOT563
5 G
OUT 38B4
D 3
S 4
7C3 39D4
39C3 SMC_XTAL
39C3 SMC_EXTAL
39A8 SMC_FAN_1_CTL
39A8 SMC_FAN_2_CTL
56C1 40B2 39C5 SMC_BC_ACOK
MAKE_BASE=TRUE
39C2 43B5 43C6 43D6 44A1 44A4 44B2 44B5 44C5 44D5
39A8 SMC_FAN_3_CTL
39B8 SMC_GFX_THROTTLE_L
39C8 ESTARLDO_EN
R5095
0
39B8 1
2
OUT
SMC_EXCARD_OC_L
EXCARD_OC_L
IN 20C2
39B5 OUT
=SMC_SMS_INT
SMS_INT_L
IN 49C7
MAKE_BASE=TRUE
SMC Crystal Circuit
CRITICAL
1
Y5010
20.00MHZ
5X3.2-SM
2
NC_SMC_FAN_1_CTL
MAKE_BASE=TRUE
NC_SMC_FAN_2_CTL
MAKE_BASE=TRUE
NC_SMC_FAN_3_CTL
MAKE_BASE=TRUE
SMC_IG_THROTTLE_L
MAKE_BASE=TRUE
NC_ESTARLDO_EN
MAKE_BASE=TRUE
=CHGR_ACOK
39C8 SMC_P24
TP_SMC_P24
MAKE_BASE=TRUE
39C8 SMC_P26
SMC_BMON_MUX_SEL
MAKE_BASE=TRUE
39C8 SMC_P41
TP_SMC_P41
MAKE_BASE=TRUE
39A8 SMC_NB_CORE_ISENSE
SMC_MCP_CORE_ISENSE
MAKE_BASE=TRUE
39A8 SMC_NB_DDR_ISENSE
SMC_MCP_DDR_ISENSE
MAKE_BASE=TRUE
39A8 ALS_LEFT
SMC_CPU_FSB_ISENSE
MAKE_BASE=TRUE
39C5 SMC_GPU_VSENSE
SMC_MCP_VSENSE
MAKE_BASE=TRUE
39D8 SMC_EXCARD_PWR_EN
TP_SMC_EXCARD_PWR_EN
MAKE_BASE=TRUE
39D8 SMC_RSTGATE_L
TP_SMC_RSTGATE_L
MAKE_BASE=TRUE
39B8 SMC_PB3 NC_SMC_PB3
MAKE_BASE=TRUE
39A5 ALS_GAIN
NC_ALS_GAIN
MAKE_BASE=TRUE
39A8 SMC_ANALOG_ID
NC_SMC_ANALOG_ID
MAKE_BASE=TRUE
39A8 ALS_RIGHT
NC_ALS_RIGHT
MAKE_BASE=TRUE
C5010
15pF
1 2
5%
50V
CERM
402
C5011
15pF
1
2
5%
50V
CERM
402
BI
71B3 14B7 10C6 OUT
OUT 39C5 40C2 40C7 47C3
8 7 6 5 4 3 2 1
5%
1/16W
MF-LF
402
SILK_PART=PWR_BTN
TO CPU
Debug Power "Button"
SMC_ONOFF_L
NOSTUFF
1
R5015
0
5%
1/10W
MF-LF
603
2
71B3 60C8 14B6 10C5
NOSTUFF
3.3K
CPU_PROCHOT_L 1
2 CPU_PROCHOT_L_R
PM_THRMTRIP_L
6 D
S G 2
1
3 D
1
R5016
PLACE R5015,R5001 ON BOTTOM SIDE
0 PLACE R5016 ON TOP SIDE
5%
1/10W
MF-LF
603
2
SILK_PART=PWR_BTN
R5062
5%
1/16W
MF-LF
402
S G 5
4
Q5059
SSM6N15FEAPE
SOT563
Q5059
SSM6N15FEAPE
SOT563
SMC FSB to 3.3V Level Shifting
8D7 =PP1V05_S0_SMC_LS
SMC_PROCHOT
SMC_THRMTRIP
39B8 SMC_PA0
39B8 SMC_PA1
47A5 39B5 38B4 SMC_LID
2
IN 39A5
IN 39A5
47C3 40C7 40A3 39C5 SMC_ONOFF_L
39A5 SMC_PH2
41C5 39C5 39B8 37A8 SMC_TX_L
41C3 39C5 39B8 37A8 SMC_RX_L
56C2 39B8 SYS_ONEWIRE
56A8 39C5 7A7 SMC_BS_ALRT_L
41D5 39B5 SMC_TMS
41C5 39B5 SMC_TDO
41D3 39B5 SMC_TDI
41C3 39B5 SMC_TCK
56C1 40D5 39C5 SMC_BC_ACOK
39A8 SMC_GFX_OVERTEMP_L
39A8 SMC_FAN_1_TACH
39A8 SMC_FAN_2_TACH
39A8 SMC_FAN_3_TACH
39C5 SMC_GPU_ISENSE
39D5 34B7 21C7 SMC_ADAPTER_EN
39B5 SMC_CASE_OPEN
39B8 SMC_EXCARD_CP
39C5 PM_SLP_S5_L
64C8 39C5 21C3 7C3 PM_SLP_S4_L
40A1 8B5 =PP3V3_S0_SMC
Preliminary
21A4 21B3
57B5
44A5
44D5
44C5
44B5
43D6
39C5 SMC_NB_MISC_ISENSE
39B8 SMC_PA5
1
R5061
3.3K
MF-LF
402
2
6
1
5%
1/16W
CPU_PROCHOT_BUF
Q5060
BC847BV-X-F
SOT563-HF
APPLE INC.
R5091
R5092
R5070 10K
R5071 100K
R5072 10K
R5073 10K
R5074 100K
R5075
R5076
R5077
2.0K
100K
10K
R5078
R5079 10K
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
1
1
1
1
1
1
1
1
10K 1
DRAWING NUMBER
NONE
2
2
2
2
2
ONEWIRE_PU
2
2
2
2
1 2
R5080 10K 1 2
R5085 10K
R5086 10K
R5088
R5090
R5089
5
100K
100K
R5087 470K
R5050 10K
R5051
R5052
R5053
R5054
R5055
10K
10K
10K
10K
10K
10K
100K
10K
SYNC_MASTER=YUAN.MA
1
R5060
470
5%
1/16W
MF-LF
402
2
3
Q5060
BC847BV-X-F
SOT563-HF
4
1
SMC_PROCHOT_3_3_L
49D7 40D8 40C7 39D4 8D1 =PP3V3_S5_SMC
1
1
1
1
1
1
1
1
1
2
2
2
2
1 2
1
1
2
2
2
1 2
2
2
2
2
2
5% 1/16W
TO SMC
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
5% 1/16W MF-LF
5%
1/16W MF-LF
5% 1/16W MF-LF
5% 1/16W MF-LF
5% 1/16W MF-LF
5% 1/16W
MF-LF
SHT OF
50 109
OUT 39C5
402
402
402
402
402
402
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
5%
1/16W MF-LF 402
5% 1/16W MF-LF
5%
MF-LF
5% 1/16W MF-LF
5%
5%
5%
5%
1/16W
1/16W
1/16W
402
402
402
1/16W MF-LF 402
1/16W
MF-LF 402
5% 1/16W MF-LF 402
5%
5%
SMC Support
1/16W
1/16W
MF-LF
MF-LF
MF-LF
MF-LF
402
402
402
5% 1/16W MF-LF 402
40D2 8B5 =PP3V3_S0_SMC
051-7537
MF-LF 402
402
SYNC_DATE=05/28/2008
REV.
A
D
C
B
A

D
C
B
A
74A3 41A5 21B3
IN
8 7 6 5 4 3 2 1
Alternate SPI ROM Support
SPI_CLK_R
SEL HIGH OUTPUTS TO D (ON BOARD ROM)
SEL LOW OUTPUTS TO M (FRANKCARD ROM)
50C6 41C5
50C3 41C5
50C3 41B5
R5191 1
OUT
OUT
IN
MUX SEL CONTROLLED BY FRANKCARD SWITCH ONCE CS1 IS SUPPORTED IN MCP
10K
5%
1/16W
MF-LF
402 2
50C6 41B5 8A3
74A3 41A5 21B3
SPI_CLK_MUX
IN
74A3 41A5 21B3
SPI_MOSI_MUX
SPI_MISO_MUX
41D5 41C3 41B7 8D1 =PP3V3_S5_LPCPLUS
=PP3V3_S5_ROM
41D3 41C5
74A3 21B3
OUT
IN
R5190 1
10K
5%
1/16W
MF-LF
402 2
SPI_MOSI_R
SPIROM_USE_MLB
41D5 41C7 41C3 8D1
LPCPLUS
9
VCC
1
2
Y+
M+
5
Y- U5110 M- 4
PI3USB102ZLE
TQFN
D+
7
D-
CRITICAL
6
10 SEL OE* 8
=PP3V3_S5_LPCPLUS
GND
3
BI
BI
IN
74A3 41B5 OUT
IN
39C5 19B7 OUT
40B2 39B5 OUT
IN
OUT
IN
39C1 OUT
IN
OUT 41D3 74A3
OUT 41D5 74A3
OUT 41A8 50C6
OUT 41A8 50C3
IN 41D5 74A3
VCC
Y+
M+
Pull-up on debug card
Y-
M-
OUT 41D3
D+
IN 41A8 50C3
D-
SEL OE*
OUT 50C6
GND
R51441 1
0.1UF
20%
LPCPLUS
10V
2 CERM
402
SPI_ALT_MISO
SPI_MISO
1
5
MCP_CS1_NO
SPI_CS0_R_L
2
4
0
SPI_ALT_CS_L_MUX1
2
U5120
R5127SPI_ALT_CS_L
1/16W 402
PI3USB102ZLE
5%
TQFN
MF-LF
7
SPI_MISO_MUX
6 SPI_MLB_CS_L_MUX
MCP_CS1_NO
CRITICAL
0
10
8
1 2 R5126 SPI_MLB_CS_L
1/16W 402
5% MCP_CS1_NO
MF-LF
=PP3V3_S5_ROM 8A3 41C7 50C6
20K
5%
MCP_CS1_YES&LPCPLUS_NOT
1/16W
MF-LF
R5146
402 2
0
1 2
5%
1/16W
MF-LF
402
SPI MUX BYPASS
LPCPLUS_NOT
R5156
0
1 2
5%
1/16W
MF-LF
402
LPCPLUS_NOT
R5158
0
1 2
5%
1/16W
MF-LF
402
9
3
1
LPCPLUS
C5114
0.1UF
20%
10V
2 CERM
402
LPCPLUS
C5124
PLACEMENT_NOTE=PLACE NEXT TO U1400
LPCPLUS_NOT
R5157
0
1 2
5%
1/16W
MF-LF
402
SPI_ALT_CLK
SPI_ALT_MOSI
SPI_CLK_MUX
SPI_MOSI_MUX
SPI_CLK_R
SPI_MOSI_R
SPI_MISO
41C7 41C3 41B7 8D1
74C3 39C8 19B3
74C3 39C8 19B3
74A3 41C5
74C3 39C8 19C3
39C1
40B2 39C5 39B8 37A8
8D5
IN 21B3 41C8 74A3
IN 21B3 41C7 74A3
OUT 21B3 41B7 74A3
LPC+SPI Connector
=PP3V3_S5_LPCPLUS
=PP5V_S0_LPCPLUS
LPC_AD
LPC_AD
SPI_ALT_MOSI
SPI_ALT_MISO
LPC_FRAME_L
PM_CLKRUN_L
SMC_TMS
DEBUG_RESET_L
SMC_TDO
SMC_TRST_L
SMC_MD1
SMC_TX_L
CRITICAL
LPCPLUS
J5100
55909-0374
M-ST-SM
31 32
1
3
516S0573
IN
IN 26B1 74C3
BI
BI
OUT 41C5 41C7
IN 41C5 74A3
IN 41B5
BI
IN 19C3 39C5
OUT 39B5 40B2
OUT 39B5 40B2
OUT 39C3 40D6
OUT 39C1
OUT 37A8 39B8 39C5 40B2
8 7 6 5 4 3 2 1
10
11 12
13
14
15 16
17 18
19
2
20
21 22
23
25
24
26
27 28
29
4
5 6
7
9
8
30
33 34
OUT 18B7
MCP SPI Override Options
MCP79 REV A01 REQUIRES EXTERNAL MUX, REV B01 STILL DOES NOT SUPPORT INTERNAL MUX
41D3 41C7
SPIROM_USE_MLB
68D8 64D5 39C5 34B7 21C3 7C3
MCP_CS1_YES
R5147
0
1 2
5%
1/16W
MF-LF
402
LPC_CLK33M_LPCPLUS
LPC_AD
LPC_AD
SPIROM_USE_MLB
SPI_ALT_CLK
SPI_ALT_CS_L
LPC_SERIRQ
LPC_PWRDWN_L
SMC_TDI
SMC_TCK
SMC_RESET_L
SMC_NMI
SMC_RX_L
LPCPLUS_GPIO
From Frank Card
To Frank Card
19B7 39C8
MCP_CS1_NO
R5142
PLACEMENT_NOTE=PLACE NEXT TO U5120
D 3
S 4
MCP79 Internal SPI MUX Support
2 G
NOT SUPPORTED IN REV A01 OR B01 MCP79 SILICON
SPI Frequency Clamp
ENSURES MCP79 SPI_DO OR SPI_CLK INPUT IS LOW WHEN STRAP IS LATCHED.NOT NEEDED FOR B01 OR LATER.
SLP_S3# nVidia recommendation, SSM6N15FEAPE
SOT563
not compatible with button-mashing.
MCP_A01&MCP_A01Q
R5160
5 G
PM_SLP_S3_L
0
1 2 MCP_SPI_FORCE_L
5%
1/16W
MF-LF
402
19B3 39C8 74C3
19B3 39C8 74C3
1
0
2
5% PLACEMENT_NOTE=Place near J5100
1/16W
MF-LF
402
=PP3V3_S5_MCP_A01
MCP_A01&MCP_A01Q
R5163 1
Q5160
100K
5%
1/16W
MF-LF
402
2
MCP_A01&MCP_A01Q
8C5 =PP3V3_S0_LPCPLUS
41D5 41C7 41B7 8D1 =PP3V3_S5_LPCPLUS
Q5160
R5140 1
100K
5%
1/16W
MF-LF
402
2
MCP_A01&MCP_A01Q
SSM6N15FEAPE
MCP_SPI_FORCE
SOT563
D 6
S 1
MCP_CS1_YES
2
S
G
1
D
Q5140
SSM3J16FV
Keep very short
3
SOD-VESM-HF
MCP_FORCE_SPI_DO_L
LPC_FRAME_PU
MCP_CS1_YES
74A3 SPI_CS1_R_L_USE_MLB
MAKE_BASE=TRUE
Preliminary
23C4 8A3
R5141 1
470
5%
1/16W
MF-LF
402
2
NO STUFF
R5161
0
1 2
5%
1/16W
MF-LF
402
MCP_A01&MCP_A01Q
R5162
0
1 2
5%
1/16W
MF-LF
402
APPLE INC.
LPC_FRAME_R_L
SPI_MOSI
SPI_CLK
SCALE
NONE
OUT 19C5
=SPI_CS1_R_L_USE_MLB
OUT 50C4 74A3
OUT 50C5 74A3
BI 21C7
LPC+SPI Debug Connector
SYNC_MASTER=CHANGZHANG SYNC_DATE=05/09/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
DRAWING NUMBER
051-7537
SHT OF
51 109
REV.
A
D
C
B
A

D
C
B
A
8 7 6 5 4 3 2 1
MCP79
U1400
(MASTER)
21C3 13B6 SMBUS_MCP_0_CLK
74B3 MAKE_BASE=TRUE
21C3 13B6 SMBUS_MCP_0_DATA
74B3 MAKE_BASE=TRUE
MCP79
U1400
(MASTER?)
74B3 21C3 SMBUS_MCP_1_CLK
MAKE_BASE=TRUE
74B3 21C3 SMBUS_MCP_1_DATA
MAKE_BASE=TRUE
MCP79 SMBUS "0" CONNECTIONS
8C5 =PP3V3_S0_SMBUS_MCP_0
R5200
4.7K
5%
402
1
1/16W
MF-LF
2
R5201
4.7K
5%
1/16W
MF-LF
402
2
SO-DIMM "A"
J3100
(Write: 0xA0 Read: 0xA1)
SO-DIMM "B"
J3200
(Write: 0xA2 Read: 0xA3)
MCP79 SMBUS "1" CONNECTIONS
8B5 =PP3V3_S0_SMBUS_MCP_1
8A3 =PP3V3_S5_SMBUS_MCP_1
R5230
1
2.0K
5%
1/16W
MF-LF
402
2
1
R5231
2 402
2.0K
5%
1/16W
MF-LF
NOSTUFF
1
R5232
10K
5%
1/16W
MF-LF
402
2
1
NOSTUFF
1
R5233
10K
5%
1/16W
2 402
MF-LF
=I2C_SODIMMB_SCL
HDCP ROM
U2690 OR U2695
(Write: 0xA0-0xAE,
Read: 0xA1-0xAF)
(All 8 addresses used)
=I2C_HDCPROM_SCL
=I2C_HDCPROM_SDA
Mikey
U6860
(WRITE: 0X72 READ: 0X73)
=I2C_MIKEY_SCL
=I2C_MIKEY_SDA
Battery
SMC
U4900
(MASTER)
SMC
U4900
(MASTER)
SMC "Battery A" SMBus Connections
Battery Manager - (Write: 0x16 Read: 0x17)
Battery LED Driver - (Write: 0x36 Read: 0x37)
Battery Temp - (Write: 0x90 Read: 0x91)
SMC
U4900
(MASTER)
SMC "0" SMBus Connections
8C5 =PP3V3_S0_SMBUS_SMC_0_S0
1
R5250
4.7K
5%
1/16W
MF-LF
402
2
R5280
1K
EMC1403-5: U5535
(Write: 0x98 Read: 0x99)
Battery Charger
ISL6258A - U7000
(Write: 0x12 Read: 0x13)
The bus formerly known as "Battery B"
Vref DACs
U2900
(Write: 0x98 Read: 0x99)
Margin Control
U2901
(Write: 0x30 Read: 0x31)
U5930
(Write: 0x70 Read: 0x71)
8 7 6 5 4 3 2 1
5%
1/16W
MF-LF
402
2
MCP Temp
BATTERY & BIL
J6950 & J6955
(See Table)
SMC "Management" SMBus Connections
R5290
1
4.7K
5%
1/16W
MF-LF
402
2
1
1
R5251
4.7K
5%
1/16W
MF-LF
402
2
R5281
1K
1
5%
1/16W
MF-LF
402
2
1
R5291
4.7K
5%
1/16W
MF-LF
2
402
SMS
SMC
U4900
(MASTER)
=I2C_SODIMMA_SCL
28A5
39B8 SMB_0_S0_CLK
76D3 SMBUS_SMC_0_S0_SCL
MAKE_BASE=TRUE
=I2C_MCPTHMSNS_SCL
45B3
39A5 SMB_A_S3_CLK
=I2C_SODIMMA_SDA 28A5 39B5 SMB_0_S0_DATA
76D3 SMBUS_SMC_0_S0_SDA
MAKE_BASE=TRUE
=I2C_MCPTHMSNS_SDA
45B3
39A5 SMB_A_S3_DATA
=I2C_SODIMMB_SDA
29A5
29A5
25A6
25A6
52C7
52C7
39A5 SMB_BSA_CLK
39A5 SMB_BSA_DATA
39C5 SMB_MGMT_CLK
39C8 SMB_MGMT_DATA
8D1 =PP3V42_G3H_SMBUS_SMC_BSA
76D3 7A7 SMBUS_SMC_BSA_SCL
MAKE_BASE=TRUE
=SMBUS_BATT_SCL
56A3 56A6
76D3 SMBUS_SMC_BSA_SDA
MAKE_BASE=TRUE
=SMBUS_BATT_SDA
56A3 56A6
8D3 =PP3V3_S3_SMBUS_SMC_MGMT
76D3
76D3
SMBUS_SMC_MGMT_SCL
MAKE_BASE=TRUE
SMBUS_SMC_MGMT_SDA
MAKE_BASE=TRUE
=SMBUS_CHGR_SCL
=SMBUS_CHGR_SDA
=I2C_VREFDACS_SCL
=I2C_VREFDACS_SDA
=I2C_PCA9557D_SCL
=I2C_PCA9557D_SDA
=I2C_SMS_SCL
=I2C_SMS_SDA
SMC
U4900
(MASTER)
39A5 SMB_B_S0_CLK
39A5 SMB_B_S0_DATA
SMC "A" SMBus Connections
NOTE: SMC RMT bus remains powered and may be active in S3 state
8D3 =PP3V3_S3_SMBUS_SMC_A_S3
76D3 7D5 7B5
76D3 7C5 7B5
SMBUS_SMC_A_S3_SCL
MAKE_BASE=TRUE
SMBUS_SMC_A_S3_SDA
MAKE_BASE=TRUE
R5270
1K
5%
1/16W
MF-LF
402
2
SMC "B" SMBus Connections
8C5 =PP3V3_S0_SMBUS_SMC_B_S0
SMBUS_SMC_B_S0_SCL
MAKE_BASE=TRUE
SMBUS_SMC_B_S0_SDA
MAKE_BASE=TRUE
Preliminary
27C7
27C7
27A8
27A8
49C6
49C6
57C6
57C6
76D3
76D3
R5260
4.7K
5%
1/16W
MF-LF
402
2
APPLE INC.
1
1
1
R5271
1K
5%
1/16W
MF-LF
402
2
1
R5261
4.7K
5%
1/16W
MF-LF
402
2
SYNC_MASTER=BEN
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
TRACKPAD
J5800
(Write: 0x90 Read: 0x91)
=I2C_TPAD_SCL
=I2C_TPAD_SDA
ALS
J3401
(Write: 0x52 Read: 0x53)
I2C_ALS_SCL
I2C_ALS_SDA
CPU Temp
EMC1403-5: U5515
(Write: 0x98 Read: 0x99)
=I2C_CPUTHMSNS_SCL
=I2C_CPUTHMSNS_SDA
M97 SMBUS CONNECTIONS
DRAWING NUMBER
NONE
051-7537
SHT OF
52
SYNC_DATE=04/21/2008
REV.
109
48C1
48C1
31B6
31B6
45D3
45D3
A
D
C
B
A

D
C
B
A
8 7 6 5 4 3 2 1
8D7 =PPVCORE_S0_CPU_VSENSE
64C1
1
R5315
100K
1%
1/16W
MF-LF
402
2
IN
Enables PBUS VSense
divider when high.
CPU Voltage Sense / Filter
XW5309
SM
PLACEMENT_NOTE=Place near U1000 center
8C7 =PPVCORE_S0_MCP_VSENSE
8C1 =PPBUS_G3HRS5
MCP Voltage Sense / Filter
XW5359
SM
1 2
PLACEMENT_NOTE=Place near U1400 center
1
CPUVSENSE_IN
R5309
4.53K
1 2 SMC_CPU_VSENSE
PBUS VOLTAGE SENSE ENABLE & FILTER
=PBUSVSENS_EN
PBUSVSENS_EN_L_DIV
2
NTUD3127CXXG
SOT-963
N-CHANNEL
G
G
D
S
D
S
P-CHANNEL
Place RC close to SMC
R5359
4.53K
MCPVSENSE_IN 1
2 SMC_MCP_VSENSE
2
1
5
4
Q5315
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
Place RC close to SMC
6
3
1
2
X5R
6.3V
0.22UF
20%
402
1
C5309
GND_SMC_AVSS
C5359
0.22UF
20%
6.3V
2
X5R
402
GND_SMC_AVSS
PBUSVSENS_EN_L
R5316
1
100K
1%
1/16W
MF-LF
402
2
OUT 39C5
39C2 40B6 43B5 43C6 44A1 44A4 44B2 44B5 44C5 44D5
OUT 40D4
39C2 40B6 43B5 43D6 44A1 44A4 44B2 44B5 44C5 44D5
R5385
27.4K
1/16W
1
PPBUS_G3HRS5_VSENSE
MIN_LINE_WIDTH=0.20 mm
MIN_NECK_WIDTH=0.20 mm
VOLTAGE=18.5V
1%
MF-LF
402
2
R5386
2
1
5.49K
1%
1/16W
MF-LF
402
RTHEVENIN = 4573 OHMS
SMC_PBUS_VSENSE
1 C5385
0.22UF
20%
6.3V
2 X5R
402
GND_SMC_AVSS
Place RC close to SMC
OUT 39C5
39C2 40B6 43C6 43D6 44A1 44A4 44B2 44B5 44C5 44D5
Preliminary
8 7 6 5 4 3 2 1
SYNC_MASTER=YUNWU
APPLE INC.
VOLTAGE SENSING
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
051-7537
SHT OF
53
SYNC_DATE=02/04/2008
REV.
109
A
D
C
B
A

D
C
B
A
8C1
IN
IN
8 7 6 5 4 3 2 1
MCP VCore Current Sense
R5490
0.001
1%
1W
MF
1206
8C8
1
IN =PPVCORE_S0_MCP_REG_R
3
8B8
=PP1V5_S0_FET_R
61C4
77D3
2
4
OUT
OUT
C5415
1
0.1uF
20%
10V
2 CERM
402
8C8 22D5
24D8 61B1
4 IN+
MCP MEM VDD Current Sense
R5491
0.002
1%
1/4W
MF
1206
1 2 =PP1V5_S0
3 4
4 IN+
BMON CURRENT SENSE
4 IN+
V+
GND
V+
GND
REF 1
V+
GND
REF 1
CPU 1.05V AND CPU VCORE HIGH SIDE CURRENT SENSE
REF 1
Place RC close to SMC
Place RC close to SMC
ENG_BMON
1 C5418
0.1uF
20%
10V
2 CERM
402
V+
REGULATOR SIDE
ENG_BMON
U5403
INA213
5
OUT
IN- SC70 OUT 6
IN
4 IN+
REF 1
LOAD SIDE
GND
NOTE: MONITORING CURRENT FROM
BATTERY TO PBUS (BATTERY DISCHARGE)
ACROSS R7008
57B5 IN
B1
SEL
1
GND
VCC
0
B0
A
VER 1
PROD_BMON
R5431
0
5%
1/16W
MF-LF
402
IN
1
R5423
100K
5%
MF-LF
402
2
OUT
PLACE R5491 AND C5390 CLOSE TO SMC
ENG_BMON
77D3 57B3 CHGR_CSO_R_P
77D3 57B3 CHGR_CSO_R_N
BMON_INA_OUT
CHGR_BMON
U5413
NC7SB3157P6XG
1 SC70 6
2
5
3
4
ENG_BMON
SMC_BMON_MUX_SEL
40D4
BMON_AMUX_OUT
1/16W
ENG_BMON
1 C5459
0.1uF
20%
10V
2 CERM
402
R5401
4.53K
1 2 SMC_BATT_ISENSE
39C5
1%
1/16W
MF-LF
1 C5490
402
0.22UF
20%
6.3V
2 X5R
402
GND_SMC_AVSS 39C2 40B6 43B5 43C6 43D6 44A1 44B2 44B5 44C5
44D5
INA213 has gain of 50V/V
PLACE U5403 AND C5418 NEAR R7008
1
3
U5400
INA213
5 IN- SC70 OUT 6
C5416
0.1uF
20%
10V
2 CERM
402
R5492
1 C5417
=PPCPUVCORE_VTT_ISNS_R 1
3
0.01
0.5%
1W
MF
0612
2
4
=PPCPUVCORE_VTT_ISNS OUT
0.1uF
20%
10V
2 CERM
402
8C2
77D3 ISNS_CPUVTT_N
77D3 ISNS_CPUVTT_P
8D1 =PP3V42_G3H_BMON_ISNS
8B5 =PP5VR3V3_S0_MCPCOREISNS
=PPVCORE_S0_MCP
ISNS_PVCORES0MCP_N
77D3 ISNS_PVCORES0MCP_P
8B5 =PP3V3_S0_MCPDDRISNS
77D3 ISNS_P1V5S0MCP_N
77D3 ISNS_P1V5S0MCP_P
3
2
8B8
8B5 =PP3V3_S0_CPUVTTISNS
2
3
U5401
INA210
5 IN- SC70 OUT 6
2
3
U5402
INA213
5 IN- SC70 OUT 6
2
MCPCORE_IOUT
MCPDDR_IOUT
CPUVTT_IOUT
MCP VCore Current Sense Filter
R5416
4.53K
1
1%
1/16W
MF-LF
402
2
1
C5472
0.22UF
20%
6.3V
2
X5R
402
OUT 40D4
MCP MEM VDD Current Sense Filter
R5417
4.53K
1 2
1%
1/16W
MF-LF
402
R5418
1
4.53K
1 2
1%
1/16W
MF-LF
402
SMC_MCP_CORE_ISENSE
GND_SMC_AVSS
SMC_MCP_DDR_ISENSE
C5435
0.22UF
20%
6.3V
2 X5R
402
GND_SMC_AVSS
1 C5436
2 6.3V
0.22UF
20%
X5R
402
GND_SMC_AVSS
Place RC close to SMC
39C2 40B6 43B5 43C6 43D6 44A1 44A4 44B2 44B5 44C5
OUT 40D4
39C2 40B6 43B5 43C6 43D6 44A1 44A4 44B2 44B5 44D5
SMC_CPU_FSB_ISENSE OUT 40D4
PLACE U5413, R5423, R5431, C5459 NEAR SMC (U4900)
For engineering, stuff U5313 and unstuff R5330
For production, stuff R5330 and unstuff U5313
39C2 40B6 43B5 43C6 43D6 44A1 44A4 44B2 44C5 44D5
CPU VCore Load Side Current Sense / Filter
8 7 6 5 4 3 2 1
IN
Place RC close to SMC
R5471
6.19K
60C7
1
2
IN
IMVP6_IMON
SMC_CPU_ISENSE
OUT 39C5
1%
1/16W
MF-LF
402
R5480
17.4K
1%
1/16W
MF-LF
402
2
1
C5470
0.22UF
20%
6.3V
2
X5R
402
DC-IN (AMON) CURRENT SENSE
Preliminary
CHGR_AMON
R5481
4.53K
1 2
SMC_DCIN_ISENSE
1%
1/16W
MF-LF
402
1
GND_SMC_AVSS
C5487
1
0.22UF
20%
6.3V
2 X5R
402
GND_SMC_AVSS
SYNC_MASTER=YUNWU
APPLE INC.
39C2 40B6 43B5 43C6 43D6 44A1 44A4 44B5 44C5 44D5
OUT 39C5
39C2 40B6 43B5 43C6 43D6 44A4 44B2 44B5 44C5 44D5
Current Sensing
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
051-7537
SHT OF
54
SYNC_DATE=04/07/2008
REV.
109
A
D
C
B
A

D
C
B
A
8 7 6 5 4 3 2 1
DETECT FIN-STACK TEMPERATURE
CRITICAL
J5590
78171-0002
M-RT-SM
3
REPLACED 518S0521 WITH 518S0519
1
2
4
Q5501
BC846BMXXH
3
SOT732-3
2
8B5 =PP3V3_S0_CPUTHMSNS
DETECT HEAT-PIPE TEMPERATURE
77D3 10C6 BI
CPU T-Diode Thermal Sensor
SIGNAL_MODOL=EMPTY
C5521 1
DETECT CPU DIE TEMPERATURE
0.0022uF
10%
50V
CERM 2
402
77D3 10C6 BI CPU_THERMD_N
1
8B5 =PP3V3_S0_MCPTHMSNS
77D3 21C3 BI
8 7 6 5 4 3 2 1
DN1
DN1
INTERNAL DIODE IN U5515 DETECTS CPU PROXIMITY TEMPERATURE
VDD
VDD
ALERT* 8
ALERT*
PLACEMENT NOTE: PLACE U5515 NEAR CPU
MCP T-Diode Thermal Sensor
SIGNAL_MODOL=EMPTY
C5522 1
DETECT MCP DIE TEMPERATURE
0.0022uF
10%
50V
CERM 2
402
77D3 21C3 BI MCP_THMDIODE_N
1
R5515
47 2
5%
1/16W
MF-LF
402
77D3 CPUTHMSNS_D2_P
SIGNAL_MODOL=EMPTY
1 C5520
0.0022uF
10%
50V
CERM
2
402
77D3 CPUTHMSNS_D2_N
R5535
47
1
5%
1/16W
MF-LF
402
MCP_THMDIODE_P
77D3 7C7 MCPTHMSNS_D2_P
77D3 7C7
CPU_THERMD_P
SIGNAL_MODOL=EMPTY
1
MCPTHMSNS_D2_N
2
PP3V3_S0_CPUTHMSNS_R
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V
PP3V3_S0_MCPTHMSNS_R
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V
C5540
0.0022uF
10%
50V
CERM
2
402
1
EMC1403-1-AIZL
2
DP1
TSSOP
THERM* 7
3
U5515
4 DP2
SMDATA 9
5 CRITICAL
DN2
SMCLK
GND
10
6
R5516
10K
5%
1/16W
MF-LF
402
2
INTERNAL DIODE IN U5535 DETECTS MCP PROXIMITY TEMPERATURE
6
1
U5535
EMC1403-1-AIZL
2
TSSOP
DP1
THERM* 7
3
4
DP2
SMDATA
9
5 CRITICAL
DN2
SMCLK
GND
10
8
1 C5515
0.1uF
20%
10V
2
CERM
402
CPUTHMSNS_THERM_L
CPUTHMSNS_ALERT_L
=I2C_CPUTHMSNS_SDA
=I2C_CPUTHMSNS_SCL
1 C5535
0.1uF
20%
10V
2
CERM
402
MCPTHMSNS_THERM_L
MCPTHMSNS_ALERT_L
=I2C_MCPTHMSNS_SDA
=I2C_MCPTHMSNS_SCL
PLACEMENT NOTE: PLACE U5535 NEAR MCP
Preliminary
1
R5536
1
10K
5%
1/16W
MF-LF
402
2
1
R5517
10K
5%
1/16W
MF-LF
402
2
BI
BI
BI
BI
42C1
42C1
1
R5537
10K
5%
1/16W
MF-LF
2
402
42D3
42D3
APPLE INC.
Thermal Sensors
SYNC_MASTER=YUNWU SYNC_DATE=03/20/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
SHT OF
55
REV.
051-7537 A
109
D
C
B
A

D
C
B
A
8 7 6 5 4 3 2 1
8D5
8C5
39A8
39A8
=PP5V_S0_FAN_RT
=PP3V3_S0_FAN_RT
5%
1/16W
MF-LF
402 2
SMC_FAN_0_TACH 147K2
7D7 FAN_RT_TACH
5%
1/16W
MF-LF
402
R5661
100K
1
1/16W
MF-LF
402
5%
2
SMC_FAN_0_CTL
8 7 6 5 4 3 2 1
R5665
1
2
G
S
D
3
R5660
Q5660
47K
1
SSM3K15FV
SOD-VESM-HF
7D7 FAN_RT_PWM
78171-0004
M-RT-SM
NC 5
NC
CRITICAL
J5601
1
2
3
4
5V DC
TACH
MOTOR CONTROL
GND
518S0521
Preliminary
6
SYNC_MASTER=CHANGZHANG
APPLE INC.
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
Fan
DRAWING NUMBER
NONE
SYNC_DATE=01/18/2008
051-7537
SHT OF
56 109
REV.
A
D
C
B
A

D
C
B
A
47B6
47D7
TO MLB CONNECTOR
8 7 6 5 4 3 2 1
PSOC USB CONTROLLER
U5701 CHIP DECOUPLING
USB INTERFACES TO MLB
SPI HOST TO Z2
P2_3
P2_1
P4_7
P4_5
P4_3
P4_1
P3_7
P3_5
P3_3
P3_1
P5_7
P5_5
P5_3
P5_1
P2_5
P2_7
P0_1
P0_3
P0_5
P0_7
VSS
VDD
P0_6
P0_4
P0_2
P0_0
P2_6
P2_4
P1_7
P1_5
P1_3
P1_1
VSS
D+
D-
VDD
P7_7
P7_0
P1_0
P1_2
P1_4
P1_6
ISSP SCLK/I2C SCL
TRACKPAD PICK BUTTONS
KEYBOARD SCANNER
PLACE C5701, C5702 & C5703
PLACE C5704, C5705 & C5706
CLOSE TO U5701 VDD PIN 22 CLOSE TO U5701 VDD PIN 49
1
C5701
4.7UF
20%
6.3V
2 X5R
603
48C1 7B5 PICKB_L
47A5 BUTTON_DISABLE
48C3 7B5 Z2_HOST_INTN
47B4 WS_LEFT_SHIFT_KEY
47B4 WS_LEFT_OPTION_KEY
1 C5702
100PF
5%
50V
2 CERM
402
74B3 1
R5702
24
1 C5703
0.1UF
10%
16V
2 X7R-CERM
402
15
56
16
55
17
54
18
53
19
52
20
51
21
50
22 49
23
48
24
47
25
46
26
45
27
44
28
43
2
5%
1/16W
MF-LF
402
DIFFERENTIAL_PAIR=USB2_TPAD
C5704
1
100PF
5%
50V
2 CERM
402
1 C5705
0.1UF
10%
16V
2 X7R-CERM
402
P2_2
P2_0
P4_6
P4_4
P4_2
P4_0
P3_6
P3_4
P3_2
P3_0
P5_6
P5_4
P5_2
P5_0
THRML
PAD
47B4 WS_CONTROL_KEY
1
42 WS_KBD17 7A5 47C2
48C1 7B5 Z2_KEY_ACT_L
2
41 WS_KBD16N 47C3
48C3 7B5 Z2_BOOT_CFG1
TP_P4_5
48C3 7C5 Z2_DEBUG3
48C1 7B5 Z2_RESET
3
4
5
6
CRITICAL
U5701
CY8C24794
MLF
40
39
38
37
WS_KBD15_C 47C3
WS_KBD14 7A5 47C2
WS_KBD13 7A5 47C2
WS_KBD12 7A5 47C2
48C1 7B5 PSOC_MISO
7
(SYM-VER2)
36 WS_KBD11 7A5 47C2
48C1 7B5 PSOC_F_CS_L
8
APN 337S2983
35 WS_KBD10 7A5 47D2
48C1 7B5 PSOC_MOSI
48C1 7B5 PSOC_SCLK
9
10
OMIT
34
33
WS_KBD9
WS_KBD8
7A5 47D2
7A5 47D2
48C3 7C5 Z2_MISO
11
32 WS_KBD7 7B5 47D2
48C3 7C5 Z2_CS_L
12
31 WS_KBD1 7B5 47D2
48C3 7C5 Z2_MOSI
13
30 WS_KBD2 7B5 47D2
48C3 7C5 Z2_SCLK
14
29 WS_KBD3 7B5 47D2
74B3 20D3
74B3 20D3
47C6 ISSP_SCLK_P1_1
USB_TPAD_P
USB_TPAD_N
TP_PSOC_SCL
TP_PSOC_SDA
TP_PSOC_P1_3
74B3 1
PP3V3_S3_PSOC MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
DIFFERENTIAL_PAIR=USB2_TPAD
R5701
24
5%
1/16W
MF-LF
402
2
USB_TPAD_R_P
USB_TPAD_R_N
PP3V3_S3_PSOC
WS_KBD23
WS_KBD22
WS_KBD21
WS_KBD20
WS_KBD19
WS_KBD18
PP3V3_S3_PSOC
47A8 47B6
57
ISSP_SDATA_P1_0 47C6
ISSP SDATA/I2C SDA
Z2_CLKIN
TP_P7_7
R5704
5%
1/16W
MF-LF
1 C5706 402
4.7UF
20%
6.3V
2 X5R
603
WS_KBD4 7B5 47D2
WS_KBD5 7B5 47D2
WS_KBD6 7B5 47D2
47A8 47D7
7B5 48C3
TMP102
3V3 LDO
PSOC
IC
18V BOOSTER
1.5 =PP3V3_S3_TPAD
1 2
8C3 47B5 47C5 47D2
PIN NAME
V+
VDD
VOUT
VDD
VIN
CURRENT
10UA
80UA
60MA MAX
60MA MAX
8MA (TYP)
14MA (MAX)
4MA (MAX)
PSOC PROGRAMMING CONNECTOR
TEST POINTS ARE FOR ON BOARD PROGRAMMING
47D2 47B5 47A6 8C3 =PP3V3_S3_TPAD
47D2 47C5 47B5 47A6 8C3
47B8 ISSP_SCLK_P1_1
47C6 ISSP_SDATA_P1_0
IN
R_SNS
2.55 KOHM
10 OHM
0.2 OHM
1.5 OHM
4.7 OHM
2
A
CRITICAL
5 TC7SZ08AFEAPE
SOT665
4
U5726 Y
1
B
2
A
CRITICAL
5 TC7SZ08AFEAPE
SOT665
4
1
U5727 Y
B
D 3
1 G S 2
V_SNS
0.0255 V
0.204 V
0.6 V
0.012 V
0.012 V
0.021 V
0.0188 V
NC
NC
ISOLATION CIRCUIT
=PP3V3_S3_TPAD
47C2 WS_LEFT_SHIFT_KBD
47B3 7A5
47D2 47C5 47B5 47A6 8C3
47C5 47C2 47B5 47B3 8D1
=PP3V3_S3_TPAD
WS_LEFT_OPTION_KBD
47C2 47B3 7A5
47D2 47C5 47B5 47A6 8C3
47C2 47B5 47B3 8D1
47C5 47C2 47B5 47B3 8D1
=PP3V3_S3_TPAD
WS_CONTROL_KBD
47C2 47B3 7A5
40C7 40C2 40A3 39C5
OUT
IN
NC
NC
CRITICAL
1
A
5
SN74LVC1G10
SC70
3
B U5703
6
C
Y
4
8 7 6 5 4 3 2 1
POWER
0.255E-6 W
16.32E-6 W
36E-3 W
0.72E-3 W
96E-6 W
294E-6 W
75.2E-6 W
APN 518S0430
TPAD BUTTONS DISABLE
40C2 39B5 38B4
2
A
CRITICAL
5 TC7SZ08AFEAPE
SOT665
4
U5725 Y
1
B
Q5701
SSM3K15FV
SOD-VESM-HF
3
=PP3V42_G3H_TPAD
BUTTON_DISABLE
47D8
SMC_LID
C5725
0.1UF
=PP3V42_G3H_TPAD 2 1
3
=PP3V42_G3H_TPAD
3
TPAD_DEBUG
CRITICAL
J5702
FH19C-4S-0.5SH25
F-RT-SM1
5
20%
10V
CERM
402
1
2
3
4
6
C5726
0.1UF
2 1
20%
10V
CERM
402
C5727
0.1UF
2 1
20%
10V
CERM
402
ISSP CLOCK
ISSP DATA
WS_LEFT_SHIFT_KEY
47D8
WS_LEFT_OPTION_KEY 47D8
WS_CONTROL_KEY
47C8
PLACE THESE COMPONENTS CLOSE TO J5800
THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB
THE TPAD BUTTONS WILL BE DISABLE
WHEN THE LID IS CLOSED
LID OPEN => SMC_LID_LC ~ 3.42V
LID CLOSE => SMC_LID_LC < 0.50V
SMC_ONOFF_L
WS_KBD15_C
WS_KBD16N
R5714
470
1 2
1%
1/16W
MF-LF
402
R5715
10K
1 2
1%
1/16W
MF-LF
402
1
C5710
0.1UF
20%
10V
2
CERM
402
PLACEMENT_NOTE=NEAR J5713
1
KEYBOARD CONNECTOR
SMC_MANUAL_RESET LOGIC
1
R5769
33K
5%
1/16W
MF-LF
402
2
R5710
1K
5%
1/16W
MF-LF
402
47C2 47B5 7A5 WS_LEFT_SHIFT_KBD
47C2 47B5 7A5 WS_LEFT_OPTION_KBD
47C2 47B5 7A5 WS_CONTROL_KBD
2
47C5 47B5 47B3
47B5 47B3 7A5
47B5 47B3 7A5
47B5 47B3 7A5
47C5 47C2 47B5 8D1 =PP3V42_G3H_TPAD
1
R5770
33K
5%
1/16W
MF-LF
2
402
47C6 7B5 WS_KBD1
47C6 7B5 WS_KBD2
47C6 7B5 WS_KBD3
47C6 7B5 WS_KBD4
47C6 7B5 WS_KBD5
47C6 7B5 WS_KBD6
47C6 7B5 WS_KBD7
47C6 7A5 WS_KBD8
47C6 7A5 WS_KBD9
47C6 7A5 WS_KBD10
47C6 7A5 WS_KBD11
47C6 7A5 WS_KBD12
47C6 7A5 WS_KBD13
47C6 7A5 WS_KBD14
7A5 WS_KBD15_CAP
7A5 WS_KBD16_NUM
47C6 7A5 WS_KBD17
47D7 7A5 WS_KBD18
47D7 7A5 WS_KBD19
47D7 7A5 WS_KBD20
47D7 7A5 WS_KBD21
47D7 7A5 WS_KBD22
47D7 7A5 WS_KBD23
7A5 WS_KBD_ONOFF_L
8D1 =PP3V42_G3H_TPAD
WS_LEFT_SHIFT_KBD
WS_LEFT_OPTION_KBD
WS_CONTROL_KBD
R5771
33K
1
8C3
47A6
47B5
47C5
5%
1/16W
MF-LF
402
2
=PP3V3_S3_TPAD
Preliminary
47C6
47C6
2
APPLE INC.
CRITICAL
APN 518S0637
APN 311S0406
J5713
32
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
31
F-RT-SM
FF14-30A-R11B-B-3H
SYNC_MASTER=YUAN.MA
C5758
1
0.1UF
10%
16V
2 X7R-CERM
402
WELLSPRING 1
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
SMC_TPAD_RST_L
DRAWING NUMBER
NONE
051-7537
40C7
SYNC_DATE=04/22/2008
SHT OF
57
REV.
109
A
D
C
B
A

D
C
B
A
8C3
=PP5V_S3_TPAD
1 C5800
0.1UF
20%
10V
2 CERM
402
PLACEMENT_NOTE=NEAR J5800
8 7 6 5 4 3 2 1
PLACEMENT_NOTE=NEAR J5800
L5800
0.01H-0.3A-80V
SM-HF
SYM_VER-1
To detect Keyboard backlight, SMC will
tristate SMC_SYS_KBDLED:
LOW = keyboard backlight present
HIGH= keyboard backlight not present
BOM OPTION: KBDLED_YES
TURNED ON FOR BEST MLB CONFIG
R5853 ALWAYS PRESENT
1
2
NO STUFF
CRITICAL
R5800
1
0
5%
1/10W
MF-LF
603
4
3
2
R5801
0
1 2
5%
1/10W
MF-LF
603
VOLTAGE=3V3
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
PP5V_S3_TPAD_F
TPAD_GND_F
VOLTAGE=0V
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
PP5V_S3_TPAD_F
48C7 48B6
48B6 48D6
7C5 48B4 48C3 48C4
IN
39B8
R5805
0
2
5%
1/16W
MF-LF
402
1
1 C5816
0.1UF
10%
16V
2 X7R-CERM
402
=PP3V3_S0_TPAD
8B5
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
BOOSTER +18.5VDC FOR SENSORS
1 C5817
2.2UF
10%
16V
2 X5R
603
APN 152S0504
2
1 L
VIN
U5805
TPS61045
FB 4
3 DO
QFN
CTRL 5
PGND
THRML
PAD GND
1
9
CRITICAL
L5801
3.3UH-870MA
VLF3010AT-SM-HF
1%
1/16W
MF-LF
402
10%
16V
2 X5R
603
CRITICAL
7
R5873
C5853
2.2UF
APN 353S1401
PP5V_S3_TPAD_F
48D6 48C7
1 2 PP5V_S3_VR
SMC_SYS_KBDLED
SMC_KDBLED_PRESENT_L
48A4
R5853
1
470K
5%
1/16W
MF-LF
402
2
INPUT_SW
0.50MM
0.20MM
R5854
PP5V_S3_BOOSTER
1
4.7K
5%
1/16W
MF-LF
402
2
10
6
SW
8
3V3 LDO FOR IPD
4 2
KEYBOARD BACKLIGHT DRIVNG AND DETECTION
8D5 =PP5V_S0_KBDLED
C5850
1UF
10%
10V
X5R
402-1
1
2
NO STUFF
1
R5852
10K
5%
1/16W
MF-LF
402
2
BOOST_SW
6 CTRL
GND
BOOSTER DESIGN CONSIDERATION:
- POWER CONSUMPTION
- DROOP LINE REGULATION
- RIPPLE TO MEET ERS
- 100-300 KHZ CLEAN SPECTRUM
- STARTUP TIME LESS THAN 2MS
- R5812,R5813,C5818 MODIFIED
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
SWITCH_NODE=TRUE
1
R5811
100K
1%
1/16W
MF-LF
402
2
CRITICAL
APN 353S1364
VIN
THRML
PAD
SW 3
LED 5
CAP 4
R5836
0.2
1 2
B0520WSXG
APN 371S0313
KBD BACKLIGHT CONNECTOR
IPD FLEX CONNECTOR
J5815 pin 1 is grounded
8 7 6 5 4 3 2 1
D5802
SOD-323
1%
1/6W
MF
402-HF
1 CE
VDD
VR5802
MM3243DRRE
MLF
GND
VOUT 3 PP3V3_S3_LDO_R
2
1
BOOST_FB
Z2_BOOST_EN 7C5 48C3
CRITICAL
U5850
LT3491
DFN
7
CRITICAL
L5850
10UH-0.58A-0.35OHM
1
1098AS-SM
1
R5855
10
2
1%
1/16W
MF-LF
402
2
1
C5818
39PF
5%
50V
2
CERM
402
48C7 48C3 48B4 7C5 TPAD_GND_F
48C3 7C5 7C3
PP3V3_S3_LDO
KBDLED_SW
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.25 MM
SWITCH_NODE=TRUE
KBDLED_CAP
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.25 MM
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
1 C5838
0.1UF
10%
16V
2
X7R-CERM
402
TPAD_GND_F
1 C5855
1UF
10%
35V
2
X5R
603
1
2 402
R5812
1M
1%
1/16W
MF-LF
R5813
71.5K
1
1%
1/16W
2 402
MF-LF
1 C5854
4.7UF
20%
6.3V
2 X5R
603
PP18V5_S3_SW
7A5 KBDLED_ANODE
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.25 MM
1
1 C5819
1UF
10%
25V
2 X5R
603-1
R5806
0
5%
1/16W
MF-LF
402
2
PP18V5_S3
SMC_KDBLED_PRESENT_L
48A6
7C3 7C5 48C1
48C7 48C4 48B4 7C5
APN 518S0691
CRITICAL on keyboard backlight flex
J5815
FF18-4A-R11AD-B-3H
F-RT-SM
1
2
3
4
48B4 7C5 7C3
TPAD_GND_F
Z2_CS_L
Z2_DEBUG3
Z2_MOSI
Z2_MISO
Z2_SCLK
Z2_BOOST_EN
Z2_HOST_INTN
Z2_BOOT_CFG1
Z2_CLKIN
PP3V3_S3_LDO
0.50MM
0.20MM
0.50MM
0.20MM
APN 516S0689
Preliminary
47C8 7C5
47C8 7C5
47C8 7C5
47C8 7C5
47C8 7C5
48C5 7C5
47D8 7B5
47C8 7B5
47B6 7B5
2
10
20
CRITICAL
J5800
55560-0227
M-ST-SM
4 3
6 5
8 7
APPLE INC.
1
9
12 11
14 13
16 15
18 17
19
22 21
SYNC_MASTER=YUAN.MA
WELLSPRING 2
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
0.20MM
SCALE
DRAWING NUMBER
NONE
Z2_KEY_ACT_L
Z2_RESET
PSOC_F_CS_L
PICKB_L
PSOC_MISO
PSOC_MOSI
PSOC_SCLK
=I2C_TPAD_SDA
=I2C_TPAD_SCL
0.50MM PP18V5_S3
7B5 47C8
7B5 47C8
7B5 47C8
7B5 47D8
7B5 47C8
7B5 47C8
7B5 47C8
42D1
42D1
SYNC_DATE=05/09/2008
SHT OF
58
7C3 7C5 48D3
REV.
051-7537 A
109
D
C
B
A

D
C
B
A
8 7 6 5 4 3 2 1
40D8 40C7 40C1 39D4 8D1
40B4 OUT
Pull-up required if SMS_INT_L not used.
SMS_INT_L
R5921 PULLS UP SMS_PWRDN TO TURN OFF SMS WHEN PIN IS NOT BEING DRIVEN BY SMC
39C8
IN
=PP3V3_S5_SMC
SMS_ONOFF_L
1
1 R5932
10K
5%
1/16W
MF-LF
2402
R5931
10K
5%
1/16W
MF-LF
2 402
49D6 8C3 =PP3V3_S3_SMS
PROD_DIGSMS
ENG_DIGSMS
Stuff R5931 AND NoStuff R5932 to use U5930
NoStuff R5931 AND Stuff R5932 if U5930 is not used
1
R5921
10K
5%
1/16W
MF-LF
402
2
SMS_PWRDN
MAKE_BASE=TRUE
42A3
42A3
49B7 8C3
=I2C_SMS_SCL
=I2C_SMS_SDA
14
VDD
U5920
AP344ALH
LGA
1 FS VOUTX 12 SMS_X_AXIS
SMS_SELFTEST
5
2
PD CRITICAL
VOUTY
ST
10 SMS_Y_AXIS
VOUTZ 8 SMS_Z_AXIS
15 RES
NC 4 RES
1
R5922
10K
5%
1/16W
MF-LF
402
2
NC
NC
NC
3
6
9
NC
NC
NC
GND
NC
NC
NC
11
13
16
NC
NC
NC
7
=PP3V3_S3_SMS
Digital SMS
Analog SMS
1
1
C5922
0.1UF
10%
16V
2 X5R
402
C5923
0.01UF
10%
16V
2 CERM
402
VDD
VDDIO
6 SCK
11 NC
273141043NC
7 SDO LGA 12 NC
8
CRITICAL
SDI
ENG_DIGSMS
1 NC
4 INT
RESERVED
10
5
NC
CSB
8 7 6 5 4 3 2 1
1
C5926
1
10UF
20%
4V
2 X5R
603
C5924
0.01UF
10%
2 CERM
16V
402
2
GND
3
9
U5930
1
OUT 39A8
OUT 39A8
OUT 39A8
C5925
0.01UF
10%
16V
2 CERM
402
1
Desired orientation when
placed on board top-side:
+Z (up)
ENG_DIGSMS
C5931
0.022UF
16V
10%
2 CERM-X5R
402
+Y
+X
1
ENG_DIGSMS
C5932
0.1UF
10%
16V 2 X5R
402
Front of system
Circle indicates pin 1 location when placed
in correct orientation
Desired orientation when
placed on board top-side:
+Z (up)
+Y
Circle indicates pin 1 location when placed
in correct orientation
Preliminary
+X
SYNC_MASTER=YUNWU
APPLE INC.
Front of system
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
SMS
SYNC_DATE=06/26/2008
051-7537
SHT OF
59
REV.
109
A
D
C
B
A

D
C
B
A
8 7 6 5 4 3 2 1
IN
R6190
IN
1
41C5 41A8 SPI_CLK_MUX
NO STUFF
10K
5%
1/16W
MF-LF
4022
R6150
0
1 2
PLACEMENT_NOTE=PLACE CLOSE TO U6100
41B5 SPI_MLB_CS_L
5%
1/16W
MF-LF
402
MCP79 SPI Frequency Select
Frequency
31 MHz
42 MHz
25 MHz
41C7 41B5 8A3
1 MHz
=PP3V3_S5_ROM
SPI_MOSI
0
0
1
1
SPI_CLK
0
1
0
1
R6100
SCLK
VCC
SI/SIO0
IN 41A8 41C5
CE*
SO/SIO1
WP*/ACC
HOLD*
GND
OUT
1
3.3K
5%
1/16W
MF-LF
4022
C6100
6
CRITICAL
U6100
32MBIT
SOP
5
R6152
0
1 2
MX25L3205DM2I-12G
OMIT
1
2
3
7
NO STUFF
1R6191
10K
5%
1/16W
MF-LF
2402
5% PLACEMENT_NOTE=PLACE CLOSE TO U6100
1/16W
R6105 MF-LF
0
402
1 2
41A8 41B5
5%
1/16W PLACEMENT_NOTE=PLACE CLOSE TO U6100
MF-LF
402
1
1R6101
2
0.1UF
20%
10V
CERM 2
402
402
74A3 41A1
3.3K
5%
1/16W
MF-LF
SPI_CLK
74A3 41B1 SPI_MOSI
SPI_MOSI_MUX
SPI_WP_L
SPI_HOLD_L
74A3 SPI_MISO_R
SPI_MISO_MUX
8 7 6 5 4 3 2 1
8
4
Preliminary
25MHz is selected with R5190 and R5191
Any of the 4 frequencies can be selected
with R6190, R6191, R5190 and R5191
SYNC_MASTER=CHANGZHANG
APPLE INC.
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
SPI ROM
DRAWING NUMBER
NONE
SHT OF
61
SYNC_DATE=05/02/2008
REV.
051-7537 A
109
D
C
B
A

D
C
B
A
8 7 6 5 4 3 2 1
ALIAS OF PP3V3_SO, MIN_LINE_WIDTH=0.6MM, MIN_NECK_WIDTH=0.2MM
55B5 54D8 52D6 51A7 8C5
74B3 21D2
IN
74A3 21C2
IN
74A3 21D2
IN
74A3 21D7
OUT
HP AMP. SHDN CONTROL
55D3 AUD_GPIO_0
OUT
PORT C RT=SUB. SPKR SIGNAL SOURCE
53B8 AUD_BI_PORT_C_R
OUT
55C4 AUD_BI_PORT_D_L
OUT
55B4 AUD_BI_PORT_D_R
OUT
PORT D=HP SIGNAL SOURCE
74A3 21D2
IN
55A2 54B3 53C8 53B8 53A8 52C6 52C3 52B6 51D3
55C4 55B8 55B5 55B4 55A8
VOLTAGE=3.3V
=PP3V3_S0_AUDIO
HDA_BIT_CLK
HDA_SYNC
HDA_SDOUT
HDA_SDIN0
HDA_RST_L
51A7 GND_AUDIO_CODEC
55A4 MIN_LINE_WIDTH=0.30 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=0V
FERR-220-OHM
1
CRITICAL
L6201
0402
2
R6204
2
22
5%
1/16W
MF-LF
402
1
1
R6270
100K
5%
1/16W
MF-LF
2
402
CRITICAL
C6200 1
1UF
10%
6.3V
CERM 2
402
ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM
VOLTAGE=5V
55D4 8C3
55B5 54D8 52D6 51D8 8C5
55A2 54B3 53C8 53B8 53A8 52C6 52C3 52B6 51D3 51B7
55C4 55B8 55B5 55B4 55A8 55A4
=PP5V_S3_AUDIO
=PP3V3_S0_AUDIO
GND_AUDIO_CODEC
MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
CODEC_SDATA_IN
1
R6202
1
1
10%
2
25V
X7R
402
1K 2
5%
1/16W
MF-LF
402
C6201
0.01UF
AUD_GPIO_1
NC_AUD_BI_PORT_C_L
R6203
100K
5%
1/16W
MF-LF
2
402
CRITICAL
1
C6208
0.1UF
10%
16V
2 X5R
402
CRITICAL
FERR-220-OHM
1
NO_TEST
23 PORT-C-L
24 PORT-C-R
L6200
1
1
0402
10%
2
16V
X5R
402
CODEC_DVDD
C6203
0.01UF
10%
2
25V
X7R
402
35
36
2
C6220
0.1UF
PORT-D-L
PORT-D-R
NC_BAL_IN_L NO_TEST18
CD-L
NC_BAL_IN_COM NO_TEST19
CD-GND
NC_BAL_IN_R NO_TEST20
CD-R
BEEP
BEEP
RESET*
THRM_PAD
AUDIO CODEC
APPLE P/N 353S1538
DVDD
DVSS
DVDD_IO
6 BCLK
SPDIFO 48
10 SYNC
SPDIFI/EAPD/MIDI-I/DMIC-R 47
5
8
SDATA_OUT
SDATA_IN
CRITICAL
U6200
ALC885Q-VB3-GR
QFN
SENSE_A
SENSE_B
13
34
2 GPIO0/DMIC-CLK
REV B3
PORT-A-L 39
3 GPIO1/DMIC-L
PORT-A-R 41
12
11
NO STUFF
1
R6201
0
2 402
5%
1/16W
MF-LF
49
10K
1
9
4
7
1 R6210
5%
1/16W
MF-LF
2
402
XW6200
SM
PLACE XW6200 AND XW6201 NEAR U6201
53C4 53B3 53A4 GND_SPKR_AMP
1
2
XW6201
SM
1 2
25
38
AVSS1
AVDD1
AVSS2
AVDD2
PORT-F-L 16
PORT-F-R 17
PORT-F-VREFO 30
PORT-A-VREFO/DCVOL 33 NO_TEST
PORT-E-L 14
PORT-E-R 15
PORT-E-VREFO 31 NO_TEST
PORT-B-VREFO 28
PORT-B-L 21
PORT-B-R 22
26
42
C6223
0.01UF
10%
25V
X7R
402
MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.20MM
AVDD_ADC_DAC
PORT-C-VREFO
PORT-B-VREFO2
1
2
PORT-G-L
PORT-G-R
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.30MM
PP5V_S3_AUDIO_F
PP4V6_ENABLE
CRITICAL
C6221
10UF
20%
6.3V
X5R
603
AUDIO 4.6V REGULATOR
STAR GND PT. FOR AUDIO SYSTEM
APPLE P/N 353S1897
MAX8902A
EN
TDFN
SELA 4
SELB 5
IN
OUT 8
BP
OUTS 6
GND
THRML
PAD
54B3 AUD_SPDIF_I
55C8 55A8 AUD_SENSE_A
55C8 AUD_SENSE_B
PORT A = LINE INPUT
55B1 AUD_BI_PORT_A_L
55A1 AUD_BI_PORT_A_R
OUT
SPKR. AMP. SHDN CONTROL
53C8 53B8 53A8 AUD_VREF_PORT_B OUT
53A8 AUD_BI_PORT_B_L OUT
53C8 AUD_BI_PORT_B_R OUT
PORT B=L AND R SPKR AMP. SIGNAL SOURCE
IN
IN
IN
IN
IN
IN
PORT F= MIC INPUT
IN
OUT PORT F VREF=MIC BIAS
IN PORT E = MIKEY MIC INPUT
8 7 6 5 4 3 2 1
29 NO_TEST
32 NO_TEST
43 NO_TEST
44 NO_TEST
PORT-H-L 45 NO_TEST
PORT-H-R 46 NO_TEST
CRITICAL
L6202
FERR-220-OHM
1 2
0402
VREF 27
AUD_CODEC_VREF
JDREF 40 AUD_CODEC_JDREF
NC 37 NC_VRP
NO_TEST
1R6205
20.0K
1%
1/16W
MF-LF
2
402
CRITICAL 1
3
1
MAX8902_BP
7
1
C6224
0.01UF
10%
50V
2 X7R
603-1
CRITICAL
C6204
100UF
20%
6.3V
TANT
CASE-AL1
1
2
CRITICAL
2
1
10%
2
25V
X7R
402
U6201
C6206
9
0.01UF
AUD_SPDIF_O
C6210
3.3UF
10%
16V
TANT
SMA-HF
CRITICAL
C6205
100UF
20%
6.3V
TANT
CASE-AL1
NC_AUD_VREF_PORT_A
NC_AUD_VREF_PORT_E
NC_AUD_VREF_PORT_C
NC_AUD_VREF_PORT_D
NC_AUD_BI_PORT_G_L
NC_AUD_BI_PORT_G_R
NC_AUD_BI_PORT_H_L
NC_AUD_BI_PORT_H_R
2
1
C6212
0.001UF
10%
2 CERM
402
50V
1
2
1
2
22
1
10%
2
25V
X7R
402
R6206
1 2
5%
1/16W
MF-LF
402
CRITICAL
C6222
C6207
0.01UF
10UF
20%
6.3V
X5R
603
MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=4.6V
PP4V6_AUDIO_ANALOG 7C3 51A3 52D6
1
GND_AUDIO_CODEC
0.01UF
10%
2
25V
X7R
402
1
C6225
R6209
100K
2 402
5%
1/16W
MF-LF
PP4V6_AUDIO_ANALOG
51A7 51B7 52B6 52C3 52C6 53A8 53B8 53C8 54B3 55A2
55A4 55A8 55B4 55B5 55B8 55C4
AUD_SPDIF_OUT
AUD_BI_PORT_F_L
AUD_BI_PORT_F_R
AUD_VREF_PORT_F
AUD_BI_PORT_E_L
Preliminary
52C6
55A4
55A4
55B4
54D3
7C3 51D3 52D6
SYNC_MASTER=AUDIO
APPLE INC.
AUDIO: CODEC
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
051-7537
SHT OF
62
SYNC_DATE=07/01/2008
REV.
109
A
D
C
B
A

D
C
B
A
8 7 6 5 4 3 2 1
PLACE R6301, R6305, R6306, R6307, AND R6308 OUTSIDE AUDIO SECTION TO CONSERVE AUDIO AREA
MIKEY
42B6
IN
42B6 BI
AUD_I2C_INT_L
21C3 21A4 OUT
47K PULL-UP ON MCP PAGE (R2142)
19D7
IN
=I2C_MIKEY_SCL
=I2C_MIKEY_SDA
51D3 51A3 7C3
55B5 54D8 51D8 51A7 8C5
R6305
0
5%
1/16W
MF-LF
402
MIKEY
R6306
0
5%
1/16W
MF-LF
402
MIKEY
R6307
0
5%
1/16W
MF-LF
402
MIKEY
R6308
PP4V6_AUDIO_ANALOG
=PP3V3_S0_AUDIO
HS_SCL
HS_SDA
HS_INT_L
HS_RST
51C3 OUT
MIKEY RECEIVER CKT
L6300
FERR-1000-OHM
MIKEY
R6301
100K
5%
1/16W
MF-LF
402
MIKEY
L6301
FERR-1000-OHM
0402
NO STUFF
AUD_IPHS_SWITCH_EN
0
5%
1/16W
MF-LF
402
GND_AUDIO_CODEC
55A2 54B3 53C8 53B8 53A8 52C3 52B6 51D3 51B7 51A7
55C4 55B8 55B5 55B4 55A8 55A4
55A2 54B3 53C8 53B8 53A8 52C6 52C3 51D3 51B7 51A7
55C4 55B8 55B5 55B4 55A8 55A4
0402
CRITICAL
MIKEY
C6300
2.2UF
10%
16V
X5R
603
MIKEY
XW6300
PART# QTY DESCRIPTION
REFERENCE DESIGNATOR(S)
132S0045 1 100PF 50V 10% 0402 CAPACITOR
C6304
SM
NOSTUFF
R6300
0
6
5
7
C6303
0.1UF
10%
16V
X7R-CERM
402
5%
1/16W
MF-LF
402
116S0114 1 100K 5% 0402 RESISTOR R6304
?
116S0004 1 0 OHMS 5% 0402 RESISTOR
116S0004 1 0 OHMS 5% 0402 RESISTOR
AUD_BI_PORT_E_L
GND_AUDIO_CODEC
R6304
C6304
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.2MM
AVDD_S0_HS
SCL
SDA
INT*
MIKEY
CRITICAL
AVDD
U6300
CD3275
DRC
MICBIAS
DETECT
BYPASS
8 ENABLE
GND THM
4
9
3
11
OMIT
R6304
100K
5%
1/16W
MF-LF
402
1
2
10
CRITICAL BOM OPTION
MIKEY
? NOMIKEY
? MIKEY
? NOMIKEY
8 7 6 5 4 3 2 1
HS_SW_DET
HS_RX_BP
OMIT
C6304
10%
50V
CERM
402
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
MIKEY
C6302
0.01UF
10%
25V
X7R
402
0.001UF
HS_MIC_BIAS
MIKEY
R6302
10K
1%
1/16W
MF-LF
402
MIKEY
R6303
2.2K
5%
1/16W
MF-LF
402
MIKEY
CRITICAL
C6301
2.2UF
20%
6.3V
TANT
402
HS_MIC_HI
HS_MIC_LO
GND_AUDIO_CODEC
IN 54D3
IN
54D3
51A7 51B7 51D3 52B6 52C6 53A8 53B8 53C8 54B3
55A2 55A4 55A8 55B4 55B5 55B8 55C4
Preliminary
APPLE INC.
AUDI0: MIKEY
SYNC_MASTER=AUDIO SYNC_DATE=07/03/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
SHT OF
63
REV.
051-7537 A
109
D
C
B
A

D
C
B
A
8 7 6 5 4 3 2 1
51C3 IN
IN
IN
IN
IN
IN
SATELLITE & SUB TWEETER AMPLIFIER
SATELLITE
SUB
GAIN
ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM
VOLTAGE=5V
53C8 53B8 8C3 =PP5V_S3_AUDIO_AMP
53B8 53A8 51C3
55C4 55B8
53A8 52C6 52C3 52B6 51D3 51B7 51A7
55B5 55B4 55A8 55A4 55A2 54B3 53B8
ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM
53D8 53B8 8C3 =PP5V_S3_AUDIO_AMP
51C7
53C8 53A8 51C3
53C8 53A8 52C6 52C3 52B6 51D3 51B7 51A7
55C4 55B8 55B5 55B4 55A8 55A4 55A2 54B3
53C8 53B8 51C3
L6610
FERR-1000-OHM
0402
ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM
53D8 53C8 8C3 =PP5V_S3_AUDIO_AMP
51C3
55C4 55B8
53B8 52C6 52C3 52B6 51D3 51B7 51A7
55B5 55B4 55A8 55A4 55A2 54B3 53C8
AUD_BI_PORT_B_R
AUD_VREF_PORT_B
GND_AUDIO_CODEC
AUD_BI_PORT_C_R
AUD_VREF_PORT_B
GND_AUDIO_CODEC
AUD_BI_PORT_B_L
AUD_VREF_PORT_B
GND_AUDIO_CODEC
1
2
169 HZ < FC < 282 HZ
80 HZ < FC < 132 HZ
12DB
CRITICAL
C6610
0.047UF
1 2 AUD_SPKRAMP_INR
10%
16V
X7R
402
CRITICAL
L6620
FERR-1000-OHM
C6620
0.1UF
1 2 AUD_SPKRAMP_INSUB_L AUD_SPKRAMP_INSUB
0402
R6609
0
1 2
10%
16V
X5R
402
SPKRAMP_SUB_SHDN
L6630
AUD_SPKRAMP_INR_L
5%
1/16W
MF-LF
402
R6610
1 2
5%
1/16W
MF-LF
402
FERR-1000-OHM
1 2 AUD_SPKRAMP_INL_L
0402
0
R6611
100K
5%
1/16W
MF-LF
402
CRITICAL
C6630
0.047UF
10%
16V
X7R
402
R6608
0
1 2
5%
1/16W
MF-LF
402
APN:353S1595
SPKRAMP_R_SHDN
AUD_SPKRAMP_INL
SPKRAMP_L_SHDN
CRITICAL
C6611 1
0.047UF
10%
16V
X7R 2
402
CRITICAL
C6621
0.1UF
10%
16V
X5R
402
CRITICAL
C6631
0.047UF
10%
16V
X7R
402
C6607
1
1uF
10%
6.3V
CERM 2
402
MAX9705_R_N
C6608
6.3V
CERM
1
1uF
10%
2
402
C6609
MAX9705_L_N
R6605
1
1uF
10%
6.3V
CERM 2
402
NO STUFF
0
1 2
5%
1/16W
MF-LF
402
MAX9705_SUB_N
NO STUFF
R6606
1
0
5%
1/16W
MF-LF
402
2
NO STUFF
R6607
0
1 2
5%
1/16W
MF-LF
402
1 10
VDD PVDD
U6610
MAX9705
TDFN1
2 IN+ OUT+ 8
3 IN- OUT- 9
5
CRITICAL
SHDN*
SYNC 6
THRML
GND PGND PAD
4 7 11
1 10
VDD PVDD
U6620
MAX9705
TDFN1
2 IN+ OUT+ 8
3 IN- OUT- 9
5
CRITICAL
SHDN*
SYNC 6
THRML
GND PGND PAD
4 7 11
1 10
VDD PVDD
U6630
MAX9705
TDFN1
2 IN+ OUT+ 8
3 IN- OUT- 9
5
CRITICAL
SHDN*
SYNC 6
THRML
GND PGND PAD
4 7 11
8 7 6 5 4 3 2 1
C6606
C6602
C6604
1UF
1
10%
6.3V
CERM 2
402
1UF
1
10%
6.3V
CERM 2
402
1
1UF
10%
6.3V
CERM 2
402
1
NO STUFF
1R6601
100
5%
1/16W
MF-LF
2 402
SPKRAMP_SYNC1 53A3
1
1
NO STUFF
1R6602
100
5%
1/16W
MF-LF
2 402
CRITICAL
C6601
100UF
20%
2 6.3V
TANT
CASE-AL1
CRITICAL
C6603
100UF
20%
2 6.3V
TANT
CASE-AL1
CRITICAL
C6605
100UF
20%
2 6.3V
TANT
CASE-AL1
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
GND_SPKR_AMP 51A6 53A4 53B3
GND_SPKR_AMP
SPKRAMP_SYNC2
GND_SPKR_AMP
1
1
5%
1/16W
MF-LF
2
402
R6603
0
R6604
0
SPKRAMP_SYNC2
5%
1/16W
MF-LF
2
402
51A6 53B3 53C4
51A6 53A4 53C4
SPKRAMP_SYNC1
MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_R_P_OUT
MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_R_N_OUT
MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_SUB_P_OUT
MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_SUB_N_OUT
Preliminary
53B3
53A4
53C4
7C7 54C2
7C7 54C2
7C7 54C2
7C7 54C2
MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_L_P_OUT
MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_L_N_OUT
7C7 54C2
7C7 54C2
APPLE INC.
AUDI0: SPEAKER AMP
SYNC_MASTER=AUDIO SYNC_DATE=07/01/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
051-7537
SHT OF
66
REV.
109
A
D
C
B
A

D
C
B
A
55B5 52D6 51D8 51A7 8C5
54B8 9C8
54B8
8 7 6 5 4 3 2 1
CRITICAL
J6700
AUDIO-JACK-TRANS-M97
54A8 9C8
54D8
=PP3V3_S0_AUDIO
PP3V3_S0_AUDIO_SPDIF
F-RT-TH3
AUDIO
OPERATING VOLTAGE 3.3
POF
SHELL
SHIELD
PINS
APN:514-0607
AUDIO
A - VDD
B - GND
C - VOUT
OPERATING VOLTAGE 3.3
POF
SHELL
SHIELD
PINS
APN:514-0608
6
5
2
1
3
4
A - VIN
7
B - VCC
8
C - GND
9
10
11
12
13
R6790
1
0 2
5%
1/16W
MF-LF
402
=GND_CHASSIS_AUDIO_JACK
PP3V3_S0_AUDIO_SPDIF
CRITICAL
J6750
AUDIO-RCVR-M97
F-RT-TH3
5
2
1
3
4
6
7
8
10
11
12
=GND_CHASSIS_AUDIO_JACK
9
1 C6700
1UF
10%
6.3V
2 CERM
402
AUDIO JACK 1: LO/HP CONNECTOR, SPDIF TX
R6749
CRITICAL
DZ6702
6.8V-100PF
402
AUD_CONNJ1_SLEEVEDET_F
CRITICAL
2
CHASSIS GND BAND AID
CRITICAL
DZ6752
6.8V-100PF
402
AUDIO JACK 2: LINE IN CONNECTOR, SPDIF RX
2
1
2
1
2
1
2
1
CRITICAL
DZ6703
1
6.8V-100PF
402
CRITICAL
DZ6753
6.8V-100PF
402
2
CRITICAL
DZ6754
6.8V-100PF
402
1
DZ6704
6.8V-100PF
402
CRITICAL
DZ6705
2
6.8V-100PF
402
1
CRITICAL
DZ6755
2
6.8V-100PF
402
1
FERR-120-OHM-1.5A
IN 51C3
OUT 52C3
OUT 52B3
OUT 51C2
BI
BI
BI
BI
OUT 55B6 55B8
OUT 55C8
OUT 55A8
55A6 OUT
55A6 OUT
53B2 7C7 IN
MIC CONNECTOR
APN:518S0520
SPEAKER CONNECTOR
IN
IN
APN:518S0519
IN
IN
53C3 7C7 IN
C6760 - C6763 ARE FOR FILTERING POTENTIAL FSB NOISE COUPLED ON SPKR LINES
MIC EMI FILTER
8 7 6 5 4 3 2 1
1
CRITICAL
L6751
0402-LF
L6754
FERR-1000-OHM
1
0402
2
2
XW6700
1
XW6701
AUD_J2_OPT_OUT 22
AUD_SPDIF_I
1 C6750
1UF
10%
6.3V
2 CERM
402
AUD_CONNJ1_MIC
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.4MM
AUD_CONNJ1_SLEEVE
AUD_CONNJ1_TIPDET
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.2MM
AUD_CONNJ1_TIP
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.2MM
AUD_CONNJ1_RING
AUD_CONNJ1_SLEEVEDET
5%
1/16W
MF-LF
402
AUD_CONNJ2_SLEEVE
AUD_CONNJ2_TIPDET
AUD_CONNJ2_TIP
AUD_CONNJ2_RING
CRITICAL
DZ6706
AUD_CONNJ2_SLEEVEDET
6.8V-100PF
402
R6702
0
5%
1/16W
MF-LF
402
NOSTUFF
R6760
0
5%
1/16W
MF-LF
402
R6703
0
5%
1/16W
MF-LF
402
R6704
0
5%
1/16W
MF-LF
402
R6705
0
5%
1/16W
MF-LF
402
R6706
0
5%
1/16W
MF-LF
402
R6707
0
5%
1/16W
MF-LF
402
R6752
0
5%
1/16W
MF-LF
402
R6753
0
5%
1/16W
MF-LF
402
R6754
0
5%
1/16W
MF-LF
402
R6755
0
5%
1/16W
MF-LF
402
R6756
0
5%
1/16W
MF-LF
402
AUD_CONNJ1_MIC_F
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.4MM
AUD_CONNJ1_SLEEVE_F
AUD_CONNJ1_TIPDET_F
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.2MM
AUD_CONNJ1_RING_F
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.2MM
AUD_CONNJ1_TIP_F
AUD_CONNJ2_SLEEVE_F
AUD_CONNJ2_TIPDET_F
AUD_CONNJ2_RING_F
AUD_CONNJ2_TIP_F
AUD_CONNJ2_SLEEVEDET_F
L6709
FERR-1000-OHM
0402
L6710
FERR-1000-OHM
0402
FERR-120-OHM-1.5A
1
L6756
FERR-1000-OHM
1 2
0402
1
100PF
5%
50V
2 CERM
402
CRITICAL
R6750
10K
1 2
C6756
L6701
0402-LF
L6704
5%
1/16W
MF-LF
402
2
FERR-1000-OHM
1
2
0402
L6706
FERR-1000-OHM
1
2
0402
R6700
10K
1 2
5%
1/16W
MF-LF
402
R6701
4.7
1 2
5%
1/16W
MF-LF
402
C6705
1
100PF
5%
50V
2 CERM
402
AUD_J2_COM
R6751
1
402
4.7
2
5%
1/16W
MF-LF
AUD_SPDIF_OUT
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.4MM
AUD_J1_COM
1
HS_MIC_HI
HS_MIC_LO
AUD_LO_AMP_OUTR
AUD_LO_AMP_OUTL
AUD_J1_SLEEVEDET_R
AUD_J1_TIPDET_R
SM
2
SM
AUD_PORTA_R
AUD_PORTA_L
2
55C1 55D1
GND_AUDIO_CODEC
55A3
55B3
AUD_J2_TIPDET_R
AUD_LO_GND
MIC_LO
1
53B2 7C7
53C3 7C7
51A7 51B7 51D3 52B6 52C3 52C6 53A8 53B8 53C8 55A2
55A4 55A8 55B4 55B5 55B8 55C4
MIC_HI
L6770
0402
2
53B2 7C7
53A2 7C7
FERR-1000-OHM
MIC_LO_CONN_F
1
L6772
FERR-1000-OHM
0402
=GND_CHASSIS_AUDIO_MIC
2
2
1
CRITICAL
DZ6770
6.8V-100PF
402
APPLE INC.
MIC_LO_CONN
MIC_HI_CONN
MIC_SHLD_CONN
SPKRAMP_SUB_P_OUT
SPKRAMP_SUB_N_OUT
SPKRAMP_R_P_OUT
SPKRAMP_R_N_OUT
Preliminary
55C1
55A4 9C8
54B1 7D7
54B1 7D7
55A6 7D7
SPKRAMP_L_P_OUT
SPKRAMP_L_N_OUT
1
MIC_HI_CONN_F
L6771
FERR-1000-OHM
2
1
C6760
C6761
5%
50V
CERM
402
0402
100PF
5%
50V
CERM
402
100PF
C6762
100PF
5%
50V
CERM
402
C6763
100PF
5%
50V
CERM
402
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
1
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
2
L6773
0402
DRAWING NUMBER
NONE
2
CRITICAL
J6702
78171-0002
M-RT-SM
3
1
2
4
CRITICAL
J6703
78171-0004
M-RT-SM
5
1
2
3
4
6
APN:518S0521
FERR-1000-OHM
MIC_HI_CONN
CRITICAL
DZ6771
6.8V-100PF
402
SYNC_MASTER=AUDIO
CRITICAL
J6701
78171-0003
M-RT-SM
4
AUDIO: JACK
051-7537
1
2
3
5
MIC_LO_CONN
SYNC_DATE=07/01/2008
SHT OF
67
7D7 54D2
7D7 54D2
REV.
109
A
D
C
B
A

D
C
B
A
FUNCTION
HP OUT
SAT SPKRS
SUB SPKR
SPDIF OUT
51C2 OUT AUD_SENSE_B
OUT
AUD_SENSE_A
IN
IN
8 7 6 5 4 3 2 1
CODEC OUTPUT SIGNAL PATHS
IN
VOLUME
0X0C (12)
0X0D (13)
0X0F (15)
N/A
CONVERTER
0X02 (2)
0X03 (3)
0X05 (5)
0X06 (6)
CODEC INPUT SIGNAL PATHS
FUNCTION
LINE IN
MIC IN
SPDIF IN
MIXER
0X23 (35)
0X24 (36)
N/A
VOLUME
0X08 (8)
0X07 (7)
N/A
55A8 51C2
55B8 55B4 55A8 PP3V3_S0_AUDIO_F
54C3
55B6 54C3
54A3
AUD_J1_TIPDET_R
55C4 55B8 55B5 55B4 55A8
52C6 52C3 52B6 51D3 51B7 51A7 GND_AUDIO_CODEC
55A4 55A2 54B3 53C8 53B8 53A8
55C8 55B4 55A8 PP3V3_S0_AUDIO_F
AUD_J1_SLEEVEDET_R
55C4 55B8 55B5 55B4 55A8
52C6 52C3 52B6 51D3 51B7 51A7 GND_AUDIO_CODEC
55A4 55A2 54B3 53C8 53B8 53A8
55C8 51C2 AUD_SENSE_A
55C8 55B8 55B4 PP3V3_S0_AUDIO_F
AUD_J2_TIPDET_R
55C4 55B8 55B5 55B4
52C6 52C3 52B6 51D3 51B7 51A7 GND_AUDIO_CODEC
55A4 55A2 54B3 53C8 53B8 53A8
1
R6801
270K
5%
1/16W
MF-LF
2
402
1
R6802
47K
1 2
5%
1/16W
MF-LF
402
R6861
270K
2
5%
1/16W
MF-LF
402
1
100K
5%
1/16W
MF-LF
402
5 G
2 G
D 3
S 4
LINE-IN (PORT A) DETECT
1
R6811
270K
5%
1/16W
MF-LF
2
402
1
R6812
47K 2
5%
1/16W
MF-LF
402
1
R6803
1
PIN COMPLEX
0X14 (20,PORTD)
0X18 (24,PORTB)
0X1A (26,PORTC)
0X1E (30,SPDIF OUT)
MUTE CONTROL
0X08 (8)
0X07 (7)
N/A
C6801
0.1UF
2
10%
X5R
16V
402
2
C6802
0.01UF
10%
16V
2 CERM
402
1
C6811
0.1UF
10%
2 X5R
Q6800
SSM6N15FEAPE
AUD_J1_DET_RC
Q6800
SSM6N15FEAPE
SOT563
AUD_J2_DET_RC
D 6
S 1
SSM3K15FV D 3
SOD-VESM-HF
16V
402
SOT563
AUD_J1_SLEEVEDET_INV
Q6802
R6813
39.2K
1%
1/16W
MF-LF
402
1 G S 2
CONVERTER
0X08 (8)
0X07 (7)
0X0A (10)
AUD_OUTJACK_INSERT_L
AUD_INJACK_INSERT_L
MUTE CONTROL
GPIO 0
VREF_B(100%)
VREF_B(100%)
N/A
NC
PIN COMPLEX
0X15 (21,PORTA)
0X19 (25,PORTF)
0X1F (31,SPDIF IN)
PORT D DETECT
Q6801
SSM6N15FEAPE
SOT563
5 G
54B3
54B3
54D2 7D7
D 3
S 4
IN
IN
IN
DET ASSIGNMENT
0X14 (20,PORTD)
N/A
N/A
0X16 (22, PORTG)
R6806
5.11K
1%
1/16W
MF-LF
402
AUD_PORTD_DET_L
55B8 54C3 AUD_J1_SLEEVEDET_R
MIC_HI
VREF
DET ASSIGNMENT
N/A
0X15 (21,PORTA)
VREF_F (80%) N/A
N/A N/A
NC
SSM6N15FEAPE
2 G
D 6
S 1
ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM
51A7 8C3 =PP5V_S3_AUDIO
PORT G DETECT(SPDIF DELEGATE)
Q6801
SOT563
680PF
10%
50V
CERM
402
2
CRITICAL
1 C6851
R6850
6.81K
1 2
1/16W 1%
MF-LF 402
R6805
10K
1%
1/16W
MF-LF
402
AUD_PORTG_DET_L
54B3 53C8 53B8 53A8 52C6 52C3 52B6 51D3 51B7 51A7 GND_AUDIO_CODEC
55C4 55B8 55B4 55A8 55A4 55A2
MIC_LO
MIC_SHLD_CONN
NC
PLACE L6800/C6800 CLOSE TO Q6800
L6800
54D8 52D6 51D8 51A7 8C5 =PP3V3_S0_AUDIO
MIC INPUT CIRCUITRY
R6855
2.2K
VREF_PORT_F_R 1 2
AUD_VREF_PORT_F 51C3
R6851
330
1
2
1/16W 5%
MF-LF 402
CRITICAL
1 C6853
10UF
20%
6.3V
2 X5R
603
1
R6852
100K
5%
1/16W
MF-LF
2
402
FERR-1000-OHM
1
54B3 53C8 53B8 53A8 52C6 52C3 52B6 51D3 51B7 51A7 GND_AUDIO_CODEC
55B8 55B5 55B4 55A8 55A4 55A2
0402
1/16W 5%
MF-LF 402
5%
1/16W
MF-LF
402
R6854
0
1
2
5%
1/16W
MF-LF
402
51C7 IN AUD_BI_PORT_D_L
IN
PLACE CLOSE TO U6801
6
8
INL
INR
VDD
CRITICAL
U6801
MAX9724A
TQFN
OUTL 11
OUTR 10
5 SHDN*
C1P 1
C1N 3
THRM
PAD
IN
HP/LO AMP
APN:353S1637
PORT D HP/LO
SGND
PGND
SVSS
PVSS
MAX9724 GAIN/FILTER COMPONENTS
AV_PB = -1 V/V, FC_HPF=5.28HZ, FC_LPF=34.45KHZ
PORT A LI
APPLE INC.
AUD_BI_PORT_A_L OUT 51C3
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
8 7 6 5 4 3 2 1
2
1
C6800
0.1UF
10%
16V
2
X5R
402
C6850
0.1uF
MIC_IN
1 2
AUD_BI_PORT_F_L 51C3
MAKE_BASE=TRUE
10% 16V
X5R 402
CRITICAL
CRITICAL
AUD_BI_PORT_F_R 51C3
XW6800
SM
1
2
NO STUFF
R6853
0
1
2
C6852 1
100PF
5%
50V
CERM 2
402
NO STUFF
PLACE C6852 NEAR U6200
GND_AUDIO_CODEC 51A7 51B7 51D3 52B6 52C3 52C6 53A8 53B8 53C8 54B3
55A2 55A8 55B4 55B5 55B8 55C4
NO STUFF
R6856
0
1
2
5%
1/16W
MF-LF
402
GND_AUDIO_CODEC
51C7
PP3V3_S0_AUDIO_F 55A8 55B8 55C8
=GND_CHASSIS_AUDIO_MIC
L6880
FERR-120-OHM-1.5A
1
0402-LF
55C2 AUD_LO_AMP_INL_M
55B2 AUD_LO_AMP_INR_M
AUD_GPIO_0
51C7
2
1
C6880
0.1UF
10%
2
16V
X7R-CERM
402
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
AUD_PP5V_F
1 C6881
10UF
20%
2
6.3V
X5R
603
10%
XW6880 2
10V
X5R
SM
402-1
1 2
CRITICAL
C6886
2.2UF
AUD_LO_AMP_INL_C
1 2
20%
6.3V
TANT
402
CRITICAL
C6889
2.2UF
AUD_BI_PORT_D_R 1 2 AUD_LO_AMP_INR_C 1 2
20%
6.3V
TANT
402
51A7 51B7 51D3 52B6 52C3 52C6 53A8 53B8 53C8 54B3
55A2 55A4 55A8 55B5 55B8 55C4
9C8 54A3
R6885
10K
5%
1/16W
MF-LF
402
54A3
13
1 2
1%
1/16W
MF-LF
402
7
R6883
13.7K
R6886
13.7K
1%
1/16W
MF-LF
402
12
2
AUD_PORTA_L
9
R6836
27.4K
1%
1/16W
MF-LF
1
20%
6.3V
TANT
402
402
2
GND_AUDIO_CODEC
R6837
27.4K
1%
1/16W
MF-LF
402
4
1
2
MAX9724_SVSS
CRITICAL
1
C6884
1UF
CRITICAL
C6888
220PF
1 2
5%
25V
CERM
402
R6884
21K
1 2
CRITICAL
C6832
2.2UF
CRITICAL
C6833
2.2UF
10%
2
10V
X5R
402-1
54A3 IN AUD_PORTA_R AUD_BI_PORT_A_R OUT 51C3
20%
6.3V
TANT
402
1
CRITICAL
C6885
1UF
SIZE
D
SCALE
DRAWING NUMBER
NONE
1
R6880
2.21K
1%
1/16W
MF-LF
2
402
1
R6881
2.21K
1%
1/16W
MF-LF
2
402
NO STUFF
R6882
1
0
5%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
AUD_LO_AMP_INL_M
55D3 AUD_LO_AMP_OUTL 54C3 55D1
AUD_LO_AMP_INR_M
55D3
R6888
21K
1 2
1%
1/16W
MF-LF
402
CRITICAL
C6891
220PF
1 2
5%
25V
CERM
402
SYNC_MASTER=AUDIO
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.2MM
AUD_LO_AMP_OUTL 54C3 55C1
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.2MM
MAX9724_C1P
MAX9724_C1N
CRITICAL
1 C6882
1UF
10%
2
10V
X5R
402-1
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.4MM
AUD_LO_GND 54B3
Preliminary
AUD_LO_AMP_OUTR 54C3 55D1
AUD_LO_AMP_OUTR 54C3 55B1
51A7 51B7 51D3 52B6 52C3 52C6 53A8 53B8 53C8 54B3
55A4 55A8 55B4 55B5 55B8 55C4
AUDIO: JACK TRANSLATORS
051-7537
SHT OF
68 109
2
SYNC_DATE=07/01/2008
REV.
A
D
C
B
A

D
C
B
A
516S0698
8 7 6 5 4 3 2 1
MagSafe DC Power Jack
56D1 8C2 =PP18V5_DCIN_CONN
57A2 56A7 BATT_POS_F
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.3 mm
VOLTAGE=12.6V
CRITICAL
J6950
BAT-M98
F-RT-SM
10
1
2
3
4
5
6
7
8
9
11
CRITICAL
J6900
78048-0573
M-RT-SM
518S0656
R6905
47
1 2
5%
1/8W
MF-LF
805
BATTERY POWER CONNECTOR
7B7 PPVBAT_G3H_CONN_F
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=12.6V
=SMBUS_BATT_SCL
=SMBUS_BATT_SDA
SMC_BS_ALRT_L
7A7 GND_BATT_CONN
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=0V
1
2
3
4
5 7B7 ADAPTER_SENSE
PPDCIN_S5_P3V42G3H
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.3 mm
VOLTAGE=18.5V
1
L6950
FERR-50-OHM
1 2
SM-LF
L6951
FERR-50-OHM
SM-LF
CRITICAL
D6950
RCLAMP2402B
SC-75
2
1
R6928
0
1 2
5%
1/16W
MF-LF
402
D6905
HN2D01JEAPE
1
3
SOT665
57A2 56B8 BATT_POS_F
3
2
C6956
7B7 PP18V5_DCIN_FUSE
MIN_LINE_WIDTH=1mm
MIN_NECK_WIDTH=0.20mm
VOLTAGE=18.5V
1
47PF
5%
50V
CERM 2
402
ADAPTER_SENSE_R
5
4
2
NC NC
C6950
1
C6905
0.01UF
20%
50V
2
CERM
603
NC
R6913 1
100K
5%
1/16W
MF-LF
402
2
R6914 1
100K
5%
1/16W
MF-LF
402
2
NC
ONEWIRE_DCIN_DIV
GND
C6915 1
0.1UF
10%
25V
X5R
2
402
Vth = Vdcin * (Rb / (Ra + Rb))
Vth = Vdcin / 2
R6920
24.3K
1
2 402
1%
1/16W
MF-LF
3.425V "G3Hot" Supply
518S0588
V+
V-
Supply needs to guarantee 3.31V delivered to SMC VRef generator
PPVIN_G3H_P3V42G3H
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=18.5V
1
0.1UF
10%
25V
X5R 2
402
C6990
10UF
1
10%
25V
X5R 2
805
3 6
VIN BOOST
U6990
1
LT3470ETS8
TSOT23-8
SHDN*
SW 5
2
CRITICAL
F6905
6AMP-24V
1 2
1206-1
BIAS 7
CRITICAL
FB 8
4
ONEWIRE_ESD
1-Wire OverVoltage Protection
P3V42G3H_BOOST
Vout = 1.25V * (1 + Ra / Rb)
3
1
5
2
C6994 1
0.22uF
20%
6.3V
X5R
2
402
P3V42G3H_SW
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE
P3V42G3H_FB
CRITICAL
J6955
78171-0005
M-RT-SM 6
1
2
3
4
5
7
1
If ADAPTER_SENSE > Vth
then turn off FET
2 50V
22pF
5%
CERM
402
CRITICAL
U6915
LM397
SOT23-5-HF
4 ONEWIRE_OVERVOLT
C6995
D 3
1 G S 2
VOLTAGE DIVIDER FROM DCIN ENSURES Q6910
Vgs is met when SYS_ONEWIRE is high or low.
Q6920 used as bilateral switch to ensure
SYS_ONEWIRE doesn’t drive unpowered U6990
CRITICAL
Q6920
SSM6N15FEAPE
D
S G
OUT 8D1 56B3
BI
BI
P-CHN
D
G
D
S
S
CRITICAL
N-CHN Q6910
NTUD3127CXXG
SOT-963
8 7 6 5 4 3 2 1
CRITICAL
L6995
33UH
1 2
CDPH4D19FHF-SM
R6995 1
348K
1%
1/16W
MF-LF
402
2
R6996 1
1/16W
402
2
1%
200K
MF-LF
R6915 1
270K
5%
1/16W
MF-LF
402
2
R6916 1
270K
5%
1/16W
MF-LF
402
2
Vout = 3.425V
200mA max output
(Switcher limit)
CRITICAL
1 C6999
2 6.3V
22UF
20%
CERM
805
BATTERY SIGNAL CONNECTOR
=PP3V42_G3H_BATT
=SMBUS_BATT_SDA
=SMBUS_BATT_SCL
7A7 SMC_BIL_BUTTON_DB_L
C6954
1
0.001UF
10%
50V
CERM
2
402
=PP3V42_G3H_REG
PP18V5_DCIN_ONEWIRE
MIN_LINE_WIDTH=0.25mm
MIN_NECK_WIDTH=0.20mm
VOLTAGE=18.5V
C6952 1
47PF
5%
50V
CERM
2
402
C6951 1
0.1UF
10%
25V
X5R
2
402
Q6910 restricts system load to 10K-70K window until
adapter detects system and enables 16.5V output.
ONEWIRE_EN
CRITICAL
Q6915
SSM3K15FV
SOD-VESM-HF
3
SOT563
C6953 1
47PF
5%
50V
CERM
2
402
1
R6917 1
270K
1/16W
402
2
5%
MF-LF
R6918 1
270K
5%
1/16W
MF-LF
402
2
C6917
0.001UF
10%
50V
2
CERM
402
5
4
42C3 56A6
42C3 56A6
CRITICAL
Q6910
NTUD3127CXXG
SOT-963
3
SYS_ONEWIRE_BILAT
5
G
2
S G
Vgs(max) = 8V
Vgs = 7.30V @ 20V DCIN
Vgs = 4.74V @ 13V DCIN
1
6
1
1
=PP3V42_G3H_BATT
4
D
BIL BUTTON DEBOUNCE CIRCUIT
C6960
0.1UF
10%
16V
2 X5R
402
(SMC_BIL_BUTTON_L)
ONEWIRE_PWR_EN_L_DIV
ONEWIRE_PWR_EN_L
2
CRITICAL
Q6920
SSM6N15FEAPE
SOT563
SMC_BC_ACOK_RC
6
1
1 2
R6960
10K
1/16W
402
MF-LF
5%
2
C6961
0.01UF
10%
2
25V
X7R
402
R6911
NC
1
NC
1
180K
5%
1/16W
MF-LF
402
2
R6912 1
470K
5%
1/16W
MF-LF
402
2
C6910 1
0.001UF
10%
50V
CERM 2
402
SYS_ONEWIRE
3
=PP18V5_DCIN_CONN
R6910
1K
1 2
BI
U6960
5%
1/16W
MF-LF
402
APPLE INC.
39B8 40B2
SMC_BC_ACOK
5
74LVC1G17DRL
SOT-553
4 SMC_BIL_BUTTON_L
Preliminary
42C3 56A3
42C3 56A3
8D2
56A3 8D1
TO SMC
SCALE
NONE
IN 39C5 40B2 40D5
OUT 39C5
DC-In & Battery Connectors
SYNC_MASTER=JACK SYNC_DATE=03/13/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
8C2 56B8
DRAWING NUMBER
SHT OF
69 109
REV.
051-7537 A
D
C
B
A

D
C
B
A
8C1
=PP18V5_G3H_CHGR
C7010
2
1
CHGR_DCIN
57C5
1
0.1UF
10%
25V
X5R 2
402
57C4 57B6
8 7 6 5 4 3 2 1
D7010
1SS418
SOD-723-HF
R7010
1
30.1K
1%
1/16W
MF-LF
402
2
R7011
GND_CHGR_SGND
57C6 CHGR_VDD
1
9.31K
1%
1/16W
MF-LF
402
2
57D4 57B5 44B3 CHGR_AMON
57D5 57C6 8D1 =PP3V42_G3H_CHGR
Q7070 D 3
SSM6N15FEAPE
SOT563
R7073
1
1K
5%
1/16W
MF-LF
402 2
5 G
S 4
C7063
(CHGR_ACIN)
1 C7044
0.01UF
10%
2
16V
CERM
402
AMON PULLDOWN LOGIC
R70741 1M
5%
1/16W
MF-LF
402 2
CHGR_VDD_R
PBUS SUPPLY / BATTERY CHARGER
Q7001
1
0.1UF
10%
25V
X5R
402
2
C7042
0.033UF
R70981
10%
16V
X5R
402
100K
5%
1/16W
MF-LF
402 2
C7047
R7045
1
1UF
10%
10V
X5R 2
402-1
56.2K
1
1%
1/16W
MF-LF
402
2
CHGR_VCOMP_R
C7045
0.001UF
1
10%
50V
CERM 2
402
R7046
1
3.01K
1/16W
1%
MF-LF
402
2
CHGR_VNEG_R
C7046
1
470PF
10%
50V
CERM 2
402
Q7070
SSM6N15FEAPE D 6
SOT563 R7075
2 G S 1
1
NOSTUFF
1M
5%
1/16W
MF-LF
402
2
CHGR_VDD_L
1
2
57D5 57A8 8D1
CHGR_ACIN
3
2
1
S
G
4
Q7000
HAT1127H
LFPAK-SM
CRITICAL
D
C7043
0.1UF
1 2
10%
16V
X5R
402
5
=PP3V42_G3H_CHGR
42C3
42B3
CHGR_SGATE
=SMBUS_CHGR_SCL
=SMBUS_CHGR_SDA
PPVDCIN_G3H_PRE2
57A8 1 2 CHGR_VDD 1
C7041
1UF
10%
X5R
10V
402-1
VDD
12 VHST
11 SCL
10 SDA
NC 4 VREF
3 ACIN
CHGR_ICOMP 5 ICOMP
CHGR_VCOMP 7 VCOMP
CHGR_VNEG 8 VNEG
CHGR_CSOP 18 CSOP
CHGR_CSON 17 CSON
(CHGR_CSOP)
(CHGR_CSON)
19
THRM_PAD
R7001
62K
1 2
5%
1/16W
MF-LF
402
R7040
4.7
5%
1/16W
MF-LF
402
QFN
AGND
2
20
CRITICAL
U7000
29
57C4 57B8
ISL6258A
26
6
VDDP
AGATE 1 CHGR_AGATE
CSIP 28 CHGR_CSIP
CSIN 27 CHGR_CSIN
22
1
BGATE 57A4 16 CHGR_BGATE
DCIN 2 CHGR_DCIN 57D8
BOOT 25 CHGR_BOOT
UGATE 24 CHGR_UGATE
23 CHGR_PHASE
LGATE 21 CHGR_LGATE
TRKL* 13 NC
57D4
AMON 9 CHGR_AMON 44B3
57A8
BMON 15 CHGR_BMON 44A6
ACOK 14 =CHGR_ACOK 40D4
PGND PHASE
2
XW7000
SM
GND_CHGR_SGND
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.3 MM
CHGR_VDDP
1 C7040
1UF
10%
2
10V
X5R
402-1
(CHGR_CSO_R_N)
C7050
=PP3V42_G3H_CHGR
57C6 57A8 8D1
R7060
1/16W
MF-LF
402
1%
1
57.6K
2
R7061
1.82K
1%
1/16W
MF-LF
402
2
1
1
10%
2
50V
X7R
402
VCC
GND
CHGR_LOWCURRENT_REF 3
2 U7060
C7026
0.001UF
BATTERY INRUSH FETS
8 7 6 5 4 3 2 1
1
C7025
0.1UF
10%
25V
X5R
402
5
1
2
1
0.1UF
10%
25V
2
X5R
402
4
CRITICAL
TL331
SOT23-5
C7060
10
5%
1/16W
MF-LF
402
1 2
XW7020
SM
1 2
1
0.047UF
10%
10V
CERM 2
402
CHGR_CSIP_XW7020
R7021
10
5%
1/16W XW7021
MF-LF
SM
402
1 2
1 2
CHGR_CSIN_XW7021
1CRITICAL
R7020
0.02
0.5%
1W
MF
20612
1
2
C7061 1
0.1UF
10%
25V
X5R
402 2
C7062
0.1UF
10%
25V
X5R
402
GND_CHGR_SGND 57B6 57B8
5
C7024
PPVBAT_G3H_CHGR_OUT
C7051
1
1
0.01uF
10%
2
16V
CERM
402
0.1UF
10%
2
16V
X5R
402
57B5
44B3 CHGR_AMON
57A8
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
3
2
1
4
R7023
Q7050
CRITICAL
FDS6681Z
SO-8
5 6 7 8
CRITICAL
Q7021
LFPAK-HF
CHGR_BGATE
4
4
RJK0305DPB
5
1 2 3
1 2 3
BATT_POS_INRUSH
CHGR_LOWCURRENT_GATE
1
2
D
G
S
R7099
100K
CHGR_LOWCURRENT_GATE_R 1 2
R7062
CRITICAL
Q7020
LFPAK-HF
1
62K
5%
1/16W
MF-LF
402
2
RJK0305DPB
CRITICAL
L7000
1
8
7
6
5
4.7UH-9.5A
IHLP4040DZ-SM
R7031
10
Q7052
5
5%
1/16W
MF-LF
402
MIN_NECK_WIDTH=0.3 MM
MIN_LINE_WIDTH=0.6 MM
PP18V5_S5_CHGR_SW_R
CRITICAL CRITICAL
1
1
C7020 C7021
22UF 22UF 1UF
20%
20%
10%
25V
2
25V
POLY-TANT
2 25V
POLY-TANT X5R
CASE-D2-SM CASE-D2-SM 603-1
2
CRITICAL
FDS6681Z
SO-8
4
5%
1/16W
MF-LF
402
1 2 3
4
HAT1127H
LFPAK-SM
CRITICAL
3
2
1
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
PPVBAT_G3H_CHGR_REG
BATT_POS_GATE
CRITICAL
1 C7008
33UF
20%
2 16V
POLY-TANT
CASED2E-SM
77D3 44A8
5%
1/16W
MF-LF R7047
402 10
77D3 44A8
CHGR_CSO_R_P
1
PPVDCIN_G3H_PRE
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.3 MM
CHGR_CSO_R_N
C7052
0.1UF
10%
16V
2 X5R
402
R7052
1 2 1 2
C7022
1M
5%
MF-LF
402
1/16W
R7053
330K
5%
MF-LF
402
1/16W
1
2
CRITICAL
R7008
0.01
0.5%
1W
MF
0612
1 2
3 4
C7023
1UF
10%
25V
X5R
603-1
CRITICAL
Preliminary
57B1
57C5
1 2
F7000
7AMP
1206
C7011
1
1UF
10%
25V
2 X5R
603-1
TO BATTERY
BATT_POS_F
APPLE INC.
1 C7027
0.001UF
20%
50V
2 CERM
402
56A7 56B8
1
2
C7028
0.001UF
20%
50V
CERM
402
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
=PPBUS_G3H
DRAWING NUMBER
NONE
SHT OF
70
TO SYSTEM
PWM FREQ. = 400 kHz
MAX CURRENT = 7A
(??? limited)
PBUS Supply/Battery Charger
SYNC_MASTER=RAYMOND
8C2
PPVBAT_G3H_CHGR_OUT 57A5
SYNC_DATE=01/31/2008
051-7537
REV.
109
A
D
C
B
A

D
C
B
A
8 7 6 5 4 3 2 1
PWM FREQ. = 300 KHZ
MAX CURRENT = 4A
8D6
=PP5VRT_S0_REG
VOLTAGE=5V
1 C7290
10UF
20%
2 6.3V
X5R
603
ROUTING NOTE:
Place XW7203 by Pin1 OF L7260.
ROUTING NOTE:
5V_RT/3.3V POWER SUPPLY
Place XW7202 by C7292.
1
CRITICAL
1
C7291
150UF
20%
2
POLY-TANT
6.3V
CASE-B2-SM
CRITICAL
C7280
33UF
2 20%
16V
POLY-TANT
CASED2E-SM
CRITICAL
1
C7292
150UF
58B6 8C1
1
=P5VRTS0_EN_L
64D1 IN
VOUT = (2 * RA / RB) + 2
XW7203
SM
2 1
L7260
XW7202
SM
2 1
=PPVIN_S0_5VRTS0
2
CRITICAL
3.3UH
IHLP
1
C7281
1UF
10%
2 25V
X5R
603-1
CRITICAL
Q7260
SI7110DN
PWRPK-1212-8-HF
CRITICAL
Q7261
SI7110DN
20%
S
2
POLY-TANT
6.3V PWRPK-1212-8-HF
CASE-B2-SM
3 2 1
5VRT_S0_VFB_XW7203
=PPVIN_S0_5VRTS0
5
D
S
3 2 1
5
D
2 G
8C1 58C6
G 4
G 4
D 6
S 1
C7260
Q7221
SSM6N15FEAPE
SOT563
R7267 R7268 R7269 R7270
15.0K
1%
1/16W
MF-LF
402
1 2
5VRTS3_3V3S5_VREF
10%
0.1UF
10%
2 10V
CERM
16V
402
X5R
402 MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
2 1
5VRT_S0_VBST
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM 5VRT_S0_DRVH
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM 5VRT_S0_LL
1
C7271
0.22UF
5VRT_S0_DRVL
5VRT_S0_VO1
5VRT_S0_VFB
64D6
10K
1%
1/16W
MF-LF
402
1 2
1
5VRT_S0_ENTRIP
C7272
1UF
10%
2 25V
X5R
603-1
VIN
14
SKIPSEL
4
TONSEL
VREG5
17 5V3V3S5_REG5
22 CRITICAL
VBST1
VBST2
9
21
DRVH1
20
LL1
19
DRVL1
24
VO1
2
VFB1
16
1
ENTRIP1
TPS51125
3
U7200
15
QFN
=P3V3S5_EN_L 5 G
IN
VREF
VREG3
8
25
DRVH2
10
LL2
11
DRVL2
12
VO2
7
VFB2
5 3V3S5_VFB
8 7 6 5 4 3 2 1
10K
1%
1/16W
MF-LF
402
1 2
ENTRIP2
6
D 3
S 4
VOUT = (2 * RC / RD) + 2
Q7221
SSM6N15FEAPE
SOT563
6.49K
1%
1/16W
MF-LF
402
1 2
C7220
0.1UF
10%
16V
X5R
402
3V3S5_VBST 2 1
MIN_LINE_WIDTH=0.6 MM
3V3S5_DRVH MIN_NECK_WIDTH=0.2 MM
VCLK
18
NC
1
2
R7271
75K
1%
1/16W
MF-LF
402
GND
PGOOD
23
EN0
13
THRM_PAD
NC
1
1 C7273
10UF
20%
2 6.3V
X5R
603
2
R7272
57.6K
1%
1/16W
MF-LF
402
58C4
5V3V3S5_REG3
58A5
GND_5VRT3V3S5_SGND
GND_5VRT3V3S5_SGND
3V3S5_ENTRIP
1 C7270
10UF
20%
2 6.3V
X5R
603
3V3S5_LL
3V3S5_VFB_R7270
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
1 2
XW7201
SM
1
8
Q1
Q2
ROUTING NOTE:
XW7204
SM
2 1
XW7205
9 4 3 2
7 6 5
SM
2 1
CRITICAL
Q7220
FDMS9600S
MLP
10
SW
10%
2 25V
X5R
603-1
ROUTING NOTE:
Place XW7204 by Pin 2 of L7220.
1UF
ROUTING NOTE:
=PPVIN_S5_3V3S5
Place XW7205 by C7252.
Place XW7201 between Pin 15 and Pin 25 of U7200.
SEPERATED MASTER PGOOD FOR BOTH 5V AND 3V3.
1
C7241
L7220
1 2
IHLP2525CZ
1
CRITICAL
4.7UH-5.5A
P5V3V3_PGOOD
CRITICAL
C7240
33UF
2 20%
16V
POLY-TANT
CASED2E-SM
1
CRITICAL
C7252
150UF
20%
2
POLY-TANT
6.3V
CASE-B2-SM
1
CRITICAL
C7251
150UF
20%
2
POLY-TANT
6.3V
CASE-B2-SM
Preliminary
3V3S5DRVL
3V3S5VO2
8C1
64A5
APPLE INC.
PWM FREQ. = 375 KHZ
MAX CURRENT = 4A
1 C7250
10UF
20%
2 6.3V
X5R
603
5V/3.3V SUPPLY
SYNC_MASTER=RAYMOND
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
=PP3V3_S5_REG
VOLTAGE=3.3V
SCALE
DRAWING NUMBER
NONE
SYNC_DATE=02/08/2008
051-7537
8B4
SHT OF
72 109
REV.
A
D
C
B
A

D
C
B
A
8 7 6 5 4 3 2 1
=DDRVTT_EN
=PPVTT_S3_DDR_BUF
27D3 8C4
=PP0V75_S0_REG
8C8
65A3 26C1
64C6
=DDRREG_EN
1.5V/0.75V(DDR3) POWER SUPPLY
VOUT = 0.75V * (1 + RA / RB)
10%
16V
X5R
402
CRITICAL
1
XW7303
C7307
22UF
1 2
20%
2 6.3V
X5R-CERM
603
1 2
C7340
0.033UF
C7300
1UF
10%
10V
X5R
402-1
2
1
SM
1
R7310
10.7K
2 402
1%
1/16W
MF-LF
1 2
R7322
20K
0.1%
1/16W
MF
402
16
ROUTING NOTE:
Place XW7303 by C7308.
1
1V5S3_VTTSNS
1V5S3_CS
CRITICAL
C7308
22UF
20%
2 6.3V
X5R-CERM
603
1V5S3_V5FILT
10 S3
11 S5
6
VDDQSET VTTREF VLDOIN VTT V5FILT VBST V5IN VDDQSNS VTTSNS
COMP
CS
9
1V5S3_VDDQSET
5
THRM_PAD
25
ROUTING NOTE:
PUT 6 VIAS UNDER THE THERMAL PAD
C7303
R7321 100PF
20K
1 402
0.1%
1/16W
MF
2
23
CS_GND
CRITICAL
U7300
SYM (1 OF 2)
ROUTING NOTE:
CONNECT CS_GND TO
Q7321 PIN1,2.3
USING KEVIN CONNECTION.
17
24
NO STUFF
1 2
5%
50V
CERM
402
14
1 2
R7307
4.7
5%
1/16W
MF-LF
402
TPS51116
QFN
GND PGND VTTGND
3
22
15
18
1
C7301
10UF
20%
2
6.3V
X5R
603
=PP5V_S3_1V5S30V75S0
1 C7302
10UF
2
8
1
20%
6.3V
X5R
603
2
GND_1V5S3_SGND
GND_1V5S3_CSGND
1V5S3_VBST
PGOOD
DRVH 211V5S3_DRVH
LL 201V5S3_LL
DRVL
MODE
NC0
NC1
13
191V5S3_DRVL
4
7 NC
12NC
1 2
XW7300
SM
XW7302
SM
1 2
8C3
1 2
0 R7300
5%
1/16W
MF-LF
402
ROUTING NOTE:
Place XW7300 between
Pin 3 and Pin 25
of U7300.
ROUTING NOTE:
Place XW7302 by Q7321.
8 7 6 5 4 3 2 1
1
2
1V5S3_VDDQSNS
1V8S3_VBST_RC
C7309
0.1uF
10%
16V
X5R
402
4 G
MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.25 mm
4 G
D
5
S
1 2 3
5
D
S
1 2 3
XW7301
SM
1 2
ROUTING NOTE:
Place XW7301 by L7320.
CRITICAL
Q7320
SI7110DN
PWRPK-1212-8-HF
CRITICAL
1 C7330
33UF
20%
2
POLY-TANT
16V
CASED2E-SM
CRITICAL
1 C7331
33UF
20%
2
POLY-TANT
16V
CASED2E-SM
1 C7332
1UF
10%
2 25V
X5R
603-1
1 C7333
0.001UF
20%
2 50V
CERM
402
CRITICAL
L7320
1.0UH-13A-5.6M-OHM
SM-IHLP-1
VOLTAGE=1.5V
MIN_LINE_WIDTH=1.5 mm
1 2 MIN_NECK_WIDTH=0.25 mm
CRITICAL
CRITICAL 1 C7342 1
330UF C7341
Q7321 20%
10UF
2.5V
20%
SI7108DN 2 POLY-TANT
CASE-D2E-SM
2 6.3V
X5R
PWRPK-1212-8-HF
603
PUT ONE BULK CAP NEXT TO THE LOAD
=PP1V5_S3_REG
8D4
CRITICAL
1 C7343 1
330UF C7344
20%
0.001UF
2 2.5V
20%
POLY-TANT 50V
2
CASE-C2-SM1 CERM
402
STATE
S0
S3
R7399
100K
5%
1/16W
MF-LF
402
1 2 =PP3V3_S3_PDCISENS 8D3
S5/G3HOT
=PPVIN_S5_1V5S30V75S0
DDRREG_PGOOD
Preliminary
64A2
PM_SLP_S4_L
HIGH
HIGH
PM_SLP_S3_L
HIGH
LOW
APPLE INC.
1.5V
1.5V
LOW LOW
0.0V
8C1
MAX CURRENT = 12A
PWM FREQ. = 400 KHZ
PP1V5_S3
SYNC_MASTER=RAYMOND
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
PP0V75_S0
0.75V
0.0V
0.0V
1.5V/0.75V DDR3 SUPPLY
SYNC_DATE=01/31/2008
051-7537
SHT OF
73
REV.
109
A
D
C
B
A

D
C
B
A
8D5
60D4 60C2 8C1
71B3 21C7
IN
8C5
60B7 60A4
8 7 6 5 4 3 2 1
=PP5V_S0_CPU_IMVP
=PPVIN_S5_CPU_IMVP
PM_DPRSLPVR
=PP3V3_S0_IMVP1
1
2
R7409
1
1K
1%
1/16W
MF-LF
2 402
C7414
470PF
10%
50V
CERM
402
1 R7414
97.6K
1%
1/16W
MF-LF
2
402
1
2
R7412
10
5%
1/16W
MF-LF
402
2
R7421
GND_IMVP6_SGND
10
5%
1/16W
MF-LF
402
NO STUFF
R7427
4.02K
1%
1/16W
MF-LF
402
1 2
NO STUFF
R7426
71B3 40D4 14B6 10C5
1
NO STUFF
C7410
0.01uF
10%
16V
CERM
402
2
C7405
0.015uF
10%
16V
X7R
402
1
2
VIN VDD PVCC
71A3 11B6
470K
CPU_VID
402 CRITICAL
71A3 11B6 CPU_VID
71A3 11B6
1
2
CPU_VID
11B6 CPU_VID
1 71A3 R7445 11B6 CPU_VID
499
71A3
ERT-J0EV474J 1%
71A3 11B6 CPU_VID
1/16W
MF-LF 71A3 11B6 CPU_VID
2402
71B3 14A3 10B2 9B2
IN CPU_DPRSTP_L
71B3
43
42
41
40
39
38
37
46
45
VID6
BOOT1 60A8 36
CRITICAL 26
VID5
BOOT2 60A6
U7400
VID4 QFN
VID3
UGATE1 60A8 35
VID2
34
PHASE1 60A8
VID1
32
VID0
LGATE1 60A8
33
PGND1
DPRSTP*
24
DPRSLPVR
ISEN1 60A8
10A2
IN
44B3
OUT
CPU_PSI_L
IMVP6_IMON
2
3
PSI*
IMON
UGATE2 60A6 27
1 2
NO STUFF
R7406
0
5%
1/16W
MF-LF
CPU_PROCHOT_L 402
1 2
R7408
147K
1%
1/16W
MF-LF
402
1 2
C7406
0.001UF
10%
50V
CERM
402
R7411
1
255
1%
1/16W
MF-LF
2 402
1
2
(IMVP6_FB)
(IMVP6_COMP)
FROM SMC
MIN_LINE_WIDTH MIN_NECK_WIDTH
1.5 MM
0.25 MM
0.25 MM 0.25 MM
1.5 MM
0.25 MM
1.5 MM 0.25 MM
0.25 MM 0.25 MM
48
3V3
(NC) 47
CLK_EN*
44
39C8
IN IMVP_VR_ON
26A8
1
OUT VR_PWRGOOD_DELAY
IMVP6_VR_TT 5
VR_ON
PGOOD
VR_TT*
IMVP6_NTC 6
NTC
(IMVP6_VW)
NOTE 1: C7432,C7433 = 27.4 OHM FOR VALIDATING CPU ONLY.
1
2
C7413
220PF
5%
25V
CERM
402
C7426
1UF
10%
6.3V
CERM
402
1
2
R7420
10
5%
1/16W
MF-LF
402
1 2
NO STUFF
R7413
1K
1%
1/16W
MF-LF
402
1
2
PPVIN_S5_IMVP6_VIN
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
C7496
0.01UF
10%
16V
CERM
402
C7430
0.1uF
10%
16V
X5R
402
1
2
1
2
C7407
0.001UF
10%
50V
CERM
402
R7410
1/16W
2 402
1
6.81K
1%
MF-LF
7
SOFT
4
RBIAS
13
VDIFF
12
FB2
11
FB
10
COMP
9
VW
25
NC
XW7400
GND
21
PHASE2 60A6 28
LGATE2 60A6 30
29
PGND2
ISEN2 60A6 23
19
VSUM 60A4
OCSET
8 60A4
60A4 18
VO
16
DROOP 60A4
60A4 17
DFB
14
VSEN
15
RTN
TPAD
DPRSLPVR
(IMVP6_VO)
MIN_LINE_WIDTH MIN_NECK_WIDTH
IMVP6_PHASE2
0.25 MM 0.25 MM
IMVP6_BOOT2 0.25 MM
0.25 MM
IMVP6_UGATE2 0.25 MM
0.25 MM
IMVP6_LGATE2 0.25 MM 0.25 MM
IMVP6_ISEN2 0.25 MM 0.25 MM
0
0
1
IMVP6_LGATE1
(GND)
IMVP6_LGATE2
(GND)
DPRSTP*
1
1
0
1 0
IMVP6 CPU VCORE REGULATOR
60C6
60C6
60C6
60C6
60C6
IMVP6_COMP_RC
IMVP6_PHASE1
IMVP6_BOOT1
IMVP6_UGATE1
IMVP6_LGATE1
IMVP6_ISEN1
IMVP6_NTC_R
IMVP6_VDIFF_RC
PP5V_S0_IMVP6_VDD
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
PP3V3_S0_IMVP6_3V3
1
R7447
2.0K
5%
1/16W
MF-LF
2402
OMIT
SM
20
ISL9504BCRZ
22
2
1
31
1
2
NO STUFF
C7432
0.01UF
10%
16V
CERM
402
1
2
1
2
C7433
0.018UF
10%
16V
X7R
402
1
49
2
C7421
0.22uF
10%
6.3V
CERM-X5R
402
C7435
10UF
20%
6.3V
X5R
603
IMVP_DPRSLPVR IMVP6_ISEN1
60A4
60C8
60A4
60A4
60A4
60A4
60A4
60A4
60A4
IMVP6_SOFT
IMVP6_RBIAS
IMVP6_VDIFF
IMVP6_FB2
IMVP6_FB
IMVP6_COMP
IMVP6_VW
GND_IMVP6_SGND
VOLTAGE=0V
60A4
IMVP6_BOOT1
IMVP6_BOOT2
IMVP6_PHASE2
IMVP6_VSUM
IMVP6_OCSET
IMVP6_VO
IMVP6_DROOP
IMVP6_RTN
IMVP6_UGATE1
IMVP6_PHASE1
IMVP6_UGATE2
IMVP6_ISEN2
IMVP6_DFB
1
2
C7431
IMVP6_VSEN
0.068UF
10%
10V
CERM
402 60A4
R7418
PSI*
1
0
1
0
1
2
C7427
0.1UF
10%
16V
X5R
402
1 2
OPERATION MODE
2-PHASE CCM
1-PHASE CCM
1-PHASE DCM
1-PHASE DCM
1
2
C7415
0.1UF
10%
16V
X5R
402
1
R7417 1 C7429
1K 5.36K 180pF
1% 1%
1/16W 1/16W
5%
MF-LF MF-LF 2 50V
402
2 402
CERM
402
1
2
1
0
5%
1/16W
MF-LF
402
1 2IMVP6_BOOT2_RC
1
0.12UF
10%
10.0V
CERM-X5R
402 2
C7428
8 7 6 5 4 3 2 1
R7416
1
13.7K
1%
1/16W
MF-LF
2 402
0.22UF
10%
6.3V
CERM-X5R
402
1 R7415
11K
1%
1/16W
MF-LF
2 402
1 R7430
3.92K
1%
1/16W
MF-LF
2
402
IMVP6_VO_R
1
CRITICAL
2
ERT-J1VR103J
MIN_LINE_WIDTH MIN_NECK_WIDTH
IMVP6_OCSET 0.25 MM
0.20 MM
IMVP6_VSUM 0.25 MM
0.20 MM
GND_IMVP6_SGND
0.50 MM 0.20 MM
IMVP6_VO
0.25 MM 0.20 MM
IMVP6_DROOP
0.25 MM
0.20 MM
IMVP6_DFB 0.25 MM
0.20 MM
IMVP6_SOFT
0.25 MM
0.20 MM
IMVP6_RBIAS
0.25 MM
0.20 MM
IMVP6_VDIFF
0.25 MM
0.20 MM
IMVP6_FB2 0.25 MM
0.20 MM
IMVP6_FB
0.25 MM
0.20 MM
IMVP6_COMP
0.25 MM
0.20 MM
IMVP6_VW 0.25 MM
0.25 MM
(IMVP6_PHASE1)
(IMVP6_ISEN1)
RJK0305DPB
LFPAK-HF
(IMVP6_PHASE2)
(IMVP6_ISEN2)
(IMVP6_VSUM)
(IMVP6_VO)
R1100/R1101 **ON THE CPU PAGE** PROTECT THE IMVP6 IF THE CPU IS NOT INSTALLED
R7422
R7425
0
5%
1/16W
MF-LF
402
2
R7424
C7434
IMVP6_BOOT1_RC
1 1 R7423
0
5%
1/16W
MF-LF
2 402
0
5%
1/16W
MF-LF
2 402
CPU_VCCSENSE_P
CPU_VCCSENSE_N
11A5 71A3
11A5 71A3
NO STUFF
C7416
0.001UF
10%
50V
CERM
402
60C8 60B7
1
2
R7431
10KOHM-5%
0603-LF
60D8 60C2 8C1
=PPVIN_S5_CPU_IMVP
1
2
4
5
NO STUFF
C7400
4
0.0022UF
10%
50V
CERM
402
4
NO STUFF
1 C7402
0.0022UF
10%
2
50V
CERM
402
1 2 3
4
5
1 2 3
5
1 2 3
CRITICAL
Q7400
1
2
RJK0305DPB
LFPAK-HF
CRITICAL
Q7401
RJK0328DPB
5
LFPAK-HF
1 2 3
1
2
CRITICAL
C7409
33UF
20%
16V
POLY-TANT
CASED2E-SM
=PPVIN_S5_CPU_IMVP
CRITICAL CRITICAL
C7401
33UF
20%
16V
POLY-TANT
CASED2E-SM
CRITICAL
Q7402
CRITICAL
Q7403
RJK0328DPB
LFPAK-HF
IMVP6_RTN 0.25 MM 0.25 MM
0.25 MM
0.25 MM
IMVP6_VSEN
1
2
33UF
1
2
1 C7408
20%
16V
POLY-TANT
2
CASED2E-SM
CRITICAL
C7417
1
33UF
20%
16V
POLY-TANT
CASED2E-SM
2
C7411
1UF
10%
25V
X5R
603-1
1
1
2
R7400
10K
1%
1/16W
MF-LF
402
1
CRITICAL
L7401
0.36UH-30A-0.80MOHM
MPC1055-SM
MPC1055LR36
DCR=0.8MOHM
0.36UH-30A-0.80MOHM
MPC1055-SM
MPC1055LR36
DCR=0.8MOHM
2
R7405
1%
MF-LF
10K
1/16W
402
1UF
10%
25V
X5R
603-1
1 R7443
3.65K
1%
1/16W
MF-LF
2 402
C7418
C7422
1
0.001UF
20%
50V
2 CERM
402
1
CRITICAL
Preliminary
60C6
60C6
60C6
60C6
60C6
60B6
60C6
60B6
60B6
60B6
60C7
60B7
60B7
60B7
60B7
60B7
60B7
60B6
60B5
L7400
8C1 60D4
60D8
1
1
APPLE INC.
1
0.001UF
20%
50V
2 CERM
402
PWM FREQ. = 300 KHZ
MAX CURRENT = 44A
1 R7401
3.65K
1%
1/16W
MF-LF
2 402
2
2
2
C7403
0.22uF
10%
6.3V
CERM-X5R
402
C7404
0.22uF
10%
6.3V
CERM-X5R
402
C7419
LOAD LINE SLOPE = -2.1 MV/A
2
1 2
NO STUFF
R7451
10K
1%
1/16W
MF-LF
402
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
1
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
2
R7404
1
5%
1/16W
MF-LF
402
1
2
R7407
1
5%
1/16W
MF-LF
402
NO STUFF
1 2
R7452
10K
1%
1/16W
MF-LF
402
C7420
1
0.001UF
20%
50V
2
CERM
402
C7423
1
0.001UF
20%
50V
CERM
2 402
IMVP6 CPU VCore Regulator
SYNC_MASTER=RAYMOND
=PPVCORE_S0_CPU_REG
SYNC_DATE=01/31/2008
051-7537
SHT OF
74 109
8D8
REV.
A
D
C
B
A

D
C
B
A
8C1
VOLTAGE=12.6V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
(Q7510 LIMIT)
7A MAX OUTPUT
VOUT = 5V
=PP5VLT_S3_REG
8C4
FREQ = 400 KHZ
1
2
8 7 6 5 4 3 2 1
=PPVIN_S3_5VLTS3
CRITICAL
1
C7510
33UF
20%
16V 2
POLY-TANT
CASED2E-SM
1
1
10UF
20%
10V
2
X5R
805
21C3 21A3
21C3 21A3
21C3 21A3
C7511
1UF
10%
25V
2
X5R
603-1
C7516
1 C7515
150UF
20%
2 6.3V
0.001UF
POLY-TANT
20%
CASE-B2-SM
50V
CERM
402
C7518
CRITICAL
CRITICAL
C7517
1
PWRPK-1212-8-HF
150UF
20%
2 6.3V
POLY-TANT
CASE-B2-SM
CRITICAL
L7520
3.3UH
IHLP
IN
IN
IN
1
2
1 2
(=PP5VLT_S3_REG)
2
XW7501
SM
D
S
D
S
G 4
G 4
PLACEMENT_NOTE=Place next to C7516
1
NO STUFF
1
R7521
61.9K
1%
1/16W
MF-LF
2
402
1
R7522
0
5%
1/16W
MF-LF
2 402
C7512
0.001UF
20%
50V
CERM
402
P5VLTS3_VSNS
5
3 2 1
5
3 2 1
NO STUFF
C7520
100PF
5%
50V
CERM
2
402
MCP VCORE/5V_S3 LEFT REGULATOR
(P5VLTS3_UGATE)
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
GATE_NODE=TRUE
(P5VLTS3_LGATE)
(P5VLTS3_BOOT)
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
1 C7514
0.1UF
10%
50V
2
X7R
603-1
(P5VLTS3_PHASE)
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
SWITCH_NODE=TRUE
Vout = 0.7V * (1 + Ra / Rb)
64B6 IN =P5VLTS3_EN
64A5 OUT MCPCORES0_PGOOD
64A5 OUT P5V_LT_S3_PGOOD
64C1 IN =MCPCORES0_EN
MCP_VID
MCP_VID
MCP_VID
1
CRITICAL
Q7510
SI7110DN
PWRPK-1212-8-HF
CRITICAL
Q7511
SI7110DN
PWRPK-1212-8-HF
(=P5VLTS3_EN)
R7520
MCP79 Rev A01 requires higher core & analog voltage
C7500
10UF
10%
25V
X5R
2
805
(=P5VLTS3_EN)
PP5V_S0_MCPREG_VCC
C7501
V5DRV
V5FILT
VREF3
LDO 7
6 VIN
LDOREFIN 8
17 VBST1
15 DRVH1
16 LL1
18 DRVL1
CRITICAL
U7500
QFN
VBST2
DRVH2
LL2
DRVL2
24
26
25
23
10 VOUT1
VOUT2 30
14 EN1
9 VSW
EN2 27
11 VFB1
REFIN2 32
12 TRIP1
29 SKIPSEL
TRIP2 31
4 EN_LDO
VREF2 1
20 V5DRV1
PGOOD1 13
2 TONSEL
PGOOD2 28
THRM_PAD GND PGND
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
1
180K
5%
1/16W
MF-LF
402
2
114S0383 1 RES,MTL FILM,1/16W,49.9K,1,0402,SMD,LF
R7570
114S0401 1 RES,MTL FILM,1/16W,78.7K,1,0402,SMD,LF
R7571
114S0484
1
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
GATE_NODE=TRUE
RES,MTL FILM,1/16W,549K,1,0402,SMD,LF
PP5V_S3_MCPREG_LDO
61C5
8C1 =PPVIN_S0_MCPREG_VIN
61C5
P5VLTS3_BOOT
P5VLTS3_UGATE
P5VLTS3_PHASE
P5VLTS3_LGATE
P5VLTS3_FB
P5VLTS3_ILIM
1
1UF
10%
6.3V
CERM
402
19
33
3
SN0802043
21
(Internal 10-ohm path
from PVCC to VCC)
61B6 PP5V_S0_MCPREG_VCC
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V
5
22
XW7500
SM
1 2
MCP_A01
MCP_A01
MCP_A01
114S0454 1
RES,MTL FILM,1/16W,274K,1,0402,SMD,LF R7581
MCP_A01
114S0423 1
RES,MTL FILM,1/16W,133K,1,0402,SMD,LF R7582 MCP_A01
114S0373 1 RES,MTL FILM,1/16W,40.2K,1,0402,SMD,LF
R7570
MCP_A01P&MCP_A01Q
114S0458 1 RES,MTL FILM,1/16W,301K,1,0402,SMD,LF R7580
MCP_A01P&MCP_A01Q
114S0411 1 RES,MTL FILM,1/16W,100K,1,0402,SMD,LF
R7582
MCP_A01P&MCP_A01Q
R7580
MCPREG_VREF3
114S0404 1 RES,MTL FILM,1/16W,84.5K,1,0402,SMD,LF
R7571 MCP_A01P&MCP_A01Q
114S0447 1 RES,MTL FILM,1/16W,237K,1,0402,SMD,LF
R7581
MCP_A01P&MCP_A01Q
C7504 1
1UF
10%
6.3V
CERM 2
402
C7503
1UF
10%
6.3V
CERM
402
Max load 100mA
61C6 PP5V_S3_MCPREG_LDO
VOLTAGE=5V
(SGND)
MCPCORES0_BOOT
MCPCORES0_UGATE
MCPCORES0_PHASE
MCPCORES0_LGATE
ISNS_PVCORES0MCP_N
REGULATE TO AFTER SENSE RES
MCPCORES0_REFIN
MCPCORES0_ILIM
PP2V_S0_MCPREG_REF
VOLTAGE=2V
Max load 50uA
1 C7530
0.1UF
20%
10V
2
CERM
402
GND_MCPREG_SGND
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0V
Vout = 2.0V * Req / (Ra + Req)
Req = Rb || Rc || Rd || Re
Rev A01 Production
(MCPCORES0_UGATE)
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
GATE_NODE=TRUE
MCP_VID0_L
MCP_VID1_L
8 7 6 5 4 3 2 1
1
R7530
180K
5%
1/16W
MF-LF
402
2
R7590
7.5K
1 2
5%
1/16W
MF-LF
402
R7592
7.5K
1 2
5%
1/16W
MF-LF
402
C7502
4.7UF
20%
6.3V
2 X5R-CERM
402
VID Voltage Voltage MCP Target
000 +1.224V +1.060V +1.05V
001 +1.159V +0.994V +1.00V
010 +1.101V +0.937V +0.95V
011 +1.049V +0.885V +0.90V
100 +0.995V +0.830V +0.85V
101 +0.952V +0.789V +0.80V
110 +0.913V +0.752V +0.75V
111 +0.876V +0.719V +0.70V
1
MCP_PROD
1
R7570
48.7K
0.1%
1/16W
MF
402
2
MCP_PROD
1
R7571
54.9K
0.1%
1/16W
MF
402
2
R7591
7.5K
1 2
5%
1/16W
MF-LF
402
(MCPCORES0_PHASE)
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
SWITCH_NODE=TRUE
(MCPCORES0_LGATE)
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
GATE_NODE=TRUE
MCP_PROD
1
R7580
475K
0.1%
1/16W
MF
402
2
MCP_VID0_RC
MCP_VID1_RC
MCP_VID2_RC
Q7580
SSM6N15FEAPE
SOT563
C7590
0.1UF
8C1 =PPVIN_S0_MCPCORES0
20%
10V
CERM 2
402
5 G
1
D 3
S 4
C7564
0.22UF
1
5%
10V
CERM-X7R
2
603
4
4
MCP_PROD
1
R7581
237K
0.1%
1/16W
MF
402
2
Q7580
SSM6N15FEAPE
SOT563
5
2 G
C7591
0.1UF
20%
10V
CERM
402
1
2
1 2 3
5
1 2 3
CRITICAL
1
C7560
33UF
20%
16V 2
POLY-TANT
CASED2E-SM
D 6
S 1
CRITICAL
Q7560
RJK0305DPB
LFPAK-HF
L7500
MPL104-SM
CRITICAL
Q7565
RJK0328DPB
LFPAK-HF
C7561
1UF
10%
25V
2
X5R
603-1
0.6UH-30A-1.5MOHM
Preliminary
44D8 77D3
M97 DIFFERENCES FROM LAST SYNC ON 12/05/07 TO T18 MLB:
Added C7568 bulk cap on output.
Tied TON to REF.
Changed Q7510 to 376S0674.
C7500 changed to 138S0638.
L7560 changed from T18 MLB inductor to 152S0782.
Changed Q7565 to 376S0637.
Changed R7514 to 280K, R7564 to 180K.
1
CRITICAL
1
2
1 C7567
10UF
20%
4V
2
X5R
603
1 G S 2
C7568 NEEDS TO BE PLACE CLOSE TO LOAD SIDE
CONNECTING IT TO AFTER SENSE RESISTOR INSTEAD OF BEFORE
APPLE INC.
C7566
1
10UF
20%
4V
X5R
2
603
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
Vout = See below
Max Current: 25A?
(Q7560 Limit)
FREQ = 300 KHZ
CRITICAL
1
C7565
330UF
20%
2 2.5V
POLY-TANT
CASE-C2-SM
1 C7569
0.0027UF
10%
50V
2
CERM
402
MCP_PROD
1
R7582
110K
0.1%
1/16W
MF
402
2
MCP_VID2_L
PLACE C7565 AND C7568 ONE CLOSE TO U7500 AND ANOTHER CLOSE TO MCP.
Q7582
SSM3K15FV D 3
SOD-VESM-HF
=PPVCORE_S0_MCP
8C8 22D5
24D8 44D7
C7592
0.1UF
20%
10V
CERM
402
1
2
1
2
C7562
0.001UF
20%
50V
CERM
402
C7570
0.001UF
20%
50V
CERM
402
SYNC_MASTER=RAYMOND
=PPMCPCORE_S0_REG
CRITICAL
C7568
330UF
20%
2.5V
POLY-TANT
CASE-C2-SM
MCP VCORE REGULATOR
051-7537
8C8
SYNC_DATE=01/31/2008
SHT OF
75 109
REV.
A
D
C
B
A

D
C
B
A
8 7 6 5 4 3 2 1
8D5 =PP5V_S0_CPUVTTS0
1
R7601
301 2
1%
1/16W
MF-LF
402
PP5V_S0_CPUVTTS0_V5FILT
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
64C1
IN
64A5 OUT
=CPUVTTS0_EN
CPUVTTS0_PGOOD
(=PPCPUVTT_S0_REG)
CPUVTTS0_VFB
CPUVTTS0_TRIP
1
R7604
6.65K
1%
1/16W
MF-LF
2
402
CPUVTTS0_VOUT
CPUVTT POWER SUPPLY
C7601
1
1UF
10%
10V
X5R
2
402-1
CRITICAL
U7600
TPS51117RGY_QFN14
SYM QFN (2 OF 2)
1 EN_PSV
TON 2
6 PGOOD
3 VOUT
5 VFB
11 TRIP
V5FILT
V5DRV
GND THRM_PAD PGND
7
4
15
XW7600
1
SM
2
10
8
VBST 14
DRVH 13
LL 12
DRVL 9
ROUTING NOTE:
8C1 =PPVIN_S0_CPUVTTS0
1
C7604
4.7UF
10%
6.3V
2
X5R-CERM
603
CPUVTTS0_TON
(GND)
Place XW7600 between Pin 7 and Pin 15 of U7600. MF-LF
ROUTING NOTE:
(CPUVTTS0_VFB)
CRITICAL
C7630
(=PPCPUVTT_S0_REG)
1
33UF
20%
16V 2
POLY-TANT
CASED2E-SM
1
C7695
1UF
10%
25V
2
X5R
603-1
CPUVTTS0_VBST
CPUVTTS0_DRVH
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
GATE_NODE=TRUE MIN_LINE_WIDTH=0.6MM
CPUVTTS0_LL
MIN_NECK_WIDTH=0.2MM
SWITCH_NODE=TRUE
MIN_LINE_WIDTH=0.6MM
CPUVTTS0_DRVL
MIN_NECK_WIDTH=0.2MM
GATE_NODE=TRUE
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
GND_CPUVTTS0_SGND
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
R7603
1 C7603
0.1UF
10%
50V
X7R
2
603-1
8 7 6 5 4 3 2 1
C7696
1
0.001UF
20%
50V
CERM
2 402
1
187K
1%
1/16W
MF-LF
402
2
4 G
4 G
5
D
S
1 2 3
D
5
S
1 2 3
CRITICAL
Q7620
SI7110DN
PWRPK-1212-8-HF
R7670
8.45K
1
1%
1/16W
MF-LF
2
402
1
R7671
20.0K
1%
1/16W
2
402
SM-IHLP-1
CRITICAL
Q7621
SI7108DN
PWRPK-1212-8-HF
Vout = 0.75V * (1 + Ra / Rb)
1
CPUVTTS0_VSNS
L7620
1.0UH-13A-5.6M-OHM
CRITICAL
2
SM
2
XW7665
1
NO STUFF
1
C7670
50V
CERM
402
5%
100PF
2
PLACEMENT_NOTE=Place XW7665 next to L7620
1 C7665
10UF
20%
6.3V
2
X5R
603
CRITICAL
1
C7660
330UF
20%
2.5V 2
POLY-TANT
CASE-C2-SM
2
SM
1
=PPCPUVTT_S0_REG
C7661
1
0.001UF
20%
50V
CERM
2 402
XW7601
Place XW7601 by C7660.
Vout = 1.052V
8A max output
F = 400 KHZ
Preliminary
8D8 65A6
SYNC_MASTER=RAYMOND
APPLE INC.
CPU VTT(1.05V) SUPPLY
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
SYNC_DATE=02/08/2008
051-7537
SHT OF
76 109
REV.
A
D
C
B
A

D
C
B
A
8 7 6 5 4 3 2 1
8A3
64D6
=PP3V3_S5_P1V05S5
=P1V05_S5_EN
VOUT = 1.102V
1V05S5_SGND
1
2
5%
1/16W
MF-LF
402
1
1
MCP 1.05V_S5 AUXC SUPPLY
R7722
C7781
0.1UF
10%
2 16V
X5R
402
1V05S5_AVIN
6
5
7
9
3
10
2
11
CRITICAL
1 C7720
22UF
20%
2 6.3V
CERM
805
VOUT = 0.6V * (1 + Ra / Rb)
MCP79 Rev A01 requires higher voltage
CRITICAL
L7720
2.2UH-3.25A
XW7700
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
SM
INPUT RAIL IS 3.3V S0
=PPVIN_S0_P1V8S0
1.8V S0 SWITCHER
=P1V8S0_EN
1 CRITICAL
VI
CRITICAL
U7760
L7760
TPS62202
10UH-0.55A-330MOHM
SOT23-5
PCAA031B-SM
4 FB
3 EN SW 5 P1V8S0_SW 1
2
GND
2
C7762
10uF
MAX CURRENT = 200MA
=PP1V8_S0_REG
8 7 6 5 4 3 2 1
1 C7760
10uF
20%
6.3V
X5R
2
603
AVINPVIN
IHLP1616BZ-SM
EN CRITICAL SW 1
1 2
=PP1V05_S5_REG
1V05S5_SW
8B4
1
Vout = 1.05V
OVT U7750FB
4 1V05S5_FB
1 C7782
TPS62510
22PF R7780
5% 301K
MAX Current = 1.5A
MODE BQA PG 8
2 50V 1% CRITICAL
CERM 1/16W
402 2 MF-LF 1 C7783
FREQ = 1Mhz
402 22UF
AGND PGND THRM_PAD
20%
1
2 6.3V
CERM
R7781 805
MCP_PROD 392K
P1V05_S5_PGOOD 64B1
1%
1/16W
MF-LF
2 402
1 2
114S0464 1 RES,MTL FILM,1/16W,348K,1%,0402,SMD,LF R7781 MCP_A01&MCP_A01P&MCP_A01Q
8B5
Preliminary
64C1
1
20%
6.3V
X5R 2
603
SYNC_MASTER=RAYMOND
APPLE INC.
8B8
MISC POWER SUPPLIES
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
SYNC_DATE=01/23/2008
SHT OF
77
REV.
051-7537 A
109
D
C
B
A

D
C
B
A
IN
IN
8 7 6 5 4 3 2 1
64D3 64B3 8D1 =PP3V42_G3H_PWRCTL
39D5 7C3
40A2 39C5 21C3 7C3
SMC_PM_G2_EN
PM_SLP_S4_L
MAKE_BASE=TRUE
1
R7800
100K
5%
1/16W
MF-LF
402
2
3.3V 1.05V S5 ENABLE
1
R7810
100K
5%
1/16W
MF-LF
402
2
R7802
100K
2 1
5%
1/16W
MF-LF
402
8B5 =PP3V3_S0_VMON
SSM3K15FV
SOD-VESM-HF
S3 ENABLE
=PP1V5_S0_VMON
8B7
8B7
=PP1V05_S0_VMON
Q7800
D 3
1 G S 2
1
1
R7811
5.1K
5%
1/16W
MF-LF
402
R7812
0
5%
1/16W
MF-LF
402
2
2
NO STUFF
1 C7802
0.068UF
10%
10V
2 CERM
402
PM_G2_P3V3S5_EN_L
MAKE_BASE=TRUE
R7801
5.1K
2 1 PM_G2_P1V05S5_EN
MAKE_BASE=TRUE
5%
1/16W
MF-LF
1
402
C7801
0.47UF
10%
6.3V
2 CERM-X5R
402
SEL
REF
VCC
TMR
RST*
GND THRM_PAD
OUT 58A5
OUT 63B7
3.3V 1.05V AND 1.5V S0 RAILS MONITOR CIRCUIT
1
6
NC
8
ADJ1
7
ADJ2
C7810
0.47UF
1
DDRREG_EN
MAKE_BASE=TRUE
10%
6.3V
CERM-X5R
402
NO STUFF
C7812
0.47UF
1
2
10%
6.3V
CERM-X5R
402
5
3
2
U7870
LTC2909
DFN
9
=P3V3S5_EN_L
=P1V05_S5_EN
(PM_S4_STATE_L)
P5VLTS3_EN
MAKE_BASE=TRUE
C7870 1
0.1uF
20%
10V
2 CERM
402
2
4
=P3V3S3_EN
=DDRREG_EN
=USB_PWR_EN
=P5VLTS3_EN
LTC2909 THRESHOLD IS 95% (3.136V)
1.5V 1.05V COMPARED TO 0.5V
OUT 65C8
OUT 59B8
OUT 37B7
OUT 61B8
TIE TMR TO GND
TRST = 200MS
S0PGOOD_PWROK
State
Run (S0)
Sleep (S3)
Soft-Off (S5)
Battery Off (G3Hot)
68D8 41A5 39C5 34B7 21C3 7C3
Power Control Signals
IN
PM_SLP_S3_L
OTHER S0 RAILS PGOOD
58A2 IN
R7879
IN
IN
61B8 IN
SMC_PM_G2_ENABLE
100K
5%
1/16W
MF-LF
402
2
8B5 =PP3V3_S0_PWRCTL
61B8
62B7
1
1 1
1
1
0
P5V3V3_PGOOD
MCPCORES0_PGOOD
CPUVTTS0_PGOOD
P5V_LT_S3_PGOOD
(S0PGOOD_PWROK)
PM_SLP_S4_L
20%
10V
CERM
NO STUFF 402
(PM_SLP_S3_L)
2
1
5 TC7SZ08AFEAPE
SOT665
A
4 (PM_SLP_S3_L_BUF)
U7859 Y
B
OUT 26A8 39D8
3.3V_S0, 1.8V_S0 ENABLE
MCPDDR, CPUVTT,MCPCORES0 ENABLE
1.5V S0 AND 1.05V S0 ENABLE
1 G S
(PM_SLP_S3_L)
2
D 3 SSM3K15FV
Q7813
Unused PGOOD signal
VOLTAGE MONITOR
5 SENSE
6
VDD
TPS3808G33DBVRG4
4 CT
SOT23-6
MR* 3
8 7 6 5 4 3 2 1
1
0
0
64B3 8A3 =PP3V3_S5_PWRCTL
R7820
1
10K
5%
1/16W
MF-LF
402
2
ALL_SYS_PWRGD
MAKE_BASE=TRUE
PM_SLP_S3_L
1
0
0
0
3
R7859
2
100
1
5%
1/16W
MF-LF
402
NO STUFF
C7858
0.1UF
2 1
=PP3V42_G3H_PWRCTL
64D8 64B3 8D1
2
1
1
R7880 2
5%
1/16W
MF-LF
402
22K 1
MCPCORES0_EN
MAKE_BASE=TRUE
C7880
0.47UF
10%
6.3V
2
CERM-X5R
402
1
R7813
2
68K
1
5%
1/16W
MF-LF
402
PM_SLP_S3_L_BUF
MAKE_BASE=TRUE
R7881 2
5%
1/16W
MF-LF
402
33K 1
CPUVTTS0_EN
MAKE_BASE=TRUE
C7881
0.47UF
10%
6.3V
2
CERM-X5R
402
TP_DDRREG_PGOOD
MAKE_BASE=TRUE
1
R7882
5%
1/16W
MF-LF
402
0
MCPDDR_EN
MAKE_BASE=TRUE
NO STUFF
C7882
0.47UF
10%
6.3V
2
CERM-X5R
402
2
1
1
C7841 1
0.001UF
20%
50V
CERM 2
402
SOD-VESM-HF
PM_SLP_S3_L_INVERT
MAKE_BASE=TRUE
NO STUFF
1
C7813
0.068UF
10%
10V
2 CERM
402
MCP_A01&MCP_A01P&MCP_A01Q
R7883 2
5%
R7884
5%
1/16W
1/16W
MF-LF
MF-LF
402
5.1K 1
402
0
P1V8S0_EN
MAKE_BASE=TRUE
NO STUFF
C7883 1 C7884
0.47UF
10%
6.3V
2 CERM-X5R
402
0.47UF
10%
6.3V
2
CERM-X5R
402
64D8 64D3 8D1 =PP3V42_G3H_PWRCTL
64C4 8A3 =PP3V3_S5_PWRCTL
Preliminary
CT
DDRREG_PGOOD
U7840
GND
2
C7840 1
0.1uF
20%
10V
2 CERM
402
RESET* 1
59B3
=P5VRTS0_EN_L
=P3V3S0_EN
=PBUSVSENS_EN
APPLE INC.
P1V05S0_EN
=P1V8S0_EN
=MCPDDR_EN
=CPUVTTS0_EN
=MCPCORES0_EN
OUT 58A7
1
2 402
R7840
100K
5%
1/16W
MF-LF
TPS3808 MR* HAS INTERNAL PULLUP
SYNC_MASTER=YUAN.MA
OUT 65B8
OUT 43B7
RSMRST_PWRGD
P1V05_S5_PGOOD
OUT 65A8
OUT 63C4
OUT 65C4
OUT 62B7
OUT 61B8
POWER SEQUENCING
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
39D8
DRAWING NUMBER
NONE
63A6
051-7537
SYNC_DATE=04/22/2008
SHT OF
78
REV.
109
A
D
C
B
A

D
C
B
A
64C6 IN
64C1
8A3 =PP3V3_S5_P3V3S3FET
IN
=P3V3S3_EN
8A3 =PP3V3_S5_P3V3S0FET
=P3V3S0_EN
8C3 =PP5V_S3_P1V05S0FET
8A3 =PP3V3_S5_P1V05FET
64C1 IN
8 7 6 5 4 3 2 1
P1V05S0_EN
R7912
10K
Q7903
SSM3K15FV
SOD-VESM-HF
D 3
1 G S 2
D 3
1 G S 2
5 G
5%
1
1/16W
MF-LF
402
2
R7932
100K
Q7905
SSM3K15FV
SOD-VESM-HF
5%
1/16W
1
MF-LF
402
2
NO STUFF
1
R7953
10K
NO STUFF
Q7951
SSM6N15FEAPE
SOT563
5%
1/16W
MF-LF
402
2
D 3
S 4
3.3V S3 FET
R7910
47K
1/16W
MF-LF
402
C7911
0.033UF
10%
16V
X5R
P3V3S3_EN_L 1 2
P3V3S3_SS
P3V3S0_EN_L
NO STUFF
C7952
5%
402
3.3V S0 FET
R7930
47K
1 2
5%
1/16W
MF-LF
402
C7931
0.033UF
1
2
1
10%
16V
2
X5R
402
1.05V S0 FET
NO STUFF
R7952
220K
1
2
5%
1/16W
MF-LF
402
0.1UF
2 1 P1V05S0_RC 510
1 2
20%
10V
CERM
402
P1V05_EN_L
NO STUFF
R7951
100K
1
5%
1/16W
MF-LF
402
NO STUFF
R7954
5%
1/16W
MF-LF
402 NO STUFF
SSM6N15FEAPE
SOT563
2
P3V3S0_SS
P1V05S0_SS
Q7951
2 G
4
4
D 6
S 1
CRITICAL
Q7910
S
P1V05_EN_L_RC
FDC638P_G
3
SM
G
3
C7910
0.01UF
CRITICAL
1
FDC606P_G
SOT-6
10%
16V
CERM
402
Q7930
D
6
5
2
1
C7930
0.01UF
1
2
1 2 5 6
10%
16V
CERM
402
2
3
4
1
FDC655BN_G
SOT6-HF
D
G
S
NO STUFF
C7953
0.068UF
10%
10V
2 CERM
402
=PP3V3_S3_FET
=PP3V3_S0_FET
8B3 =PP1V05_S5_P1V05S0FET
NO STUFF
CRITICAL
Q7953
62C2 8D8 =PPCPUVTT_S0_REG
1
2
5
6
=PP1V05_S0_FET
1
R7955
0
5%
1/8W
MF-LF
805
2
8D4
8C6
MOSFET
CHANNEL
RDS(ON)
LOADING
MOSFET
CHANNEL
RDS(ON)
LOADING
MOSFET
CHANNEL
RDS(ON)
LOADING
3.3V S3 FET
FDC638P
P-TYPE
3.3V S0 FET
48 mOhm @4.5V
0.182 A (EDP)
FDC606P
P-TYPE
26 MOHM @4.5V
1.431 A (EDP)
1.05V S0 FET
FDC655BN
N-TYPE
30 MOHM @4.0V VGS
1.1A (EDP)
8C3 =PP5V_S3_MCPDDRFET
8 7 6 5 4 3 2 . 1
64C1 IN
=MCPDDR_EN
R7903
Q7971
SSM6N15FEAPE
SOT563
59C8 26C1
5 G
IN
1
100K
5%
1/16W
MF-LF
402
2
D 3
S 4
1.5V S0 FET
(1.5V S0 FET FOR DDR3 MEM, MCP79 AND CPU)
R7901
10K
1
2
5%
1/16W
MF-LF
402
5 G
D 3
S 4
R7971
47K
1 2
5%
1/16W
MF-LF
402
C7902
0.1UF
Q7971
20%
10V
CERM
2
402
SSM6N15FEAPE
SOT563
2 G
MCP79 DDRVTT FET
2 G
D 6
S 1
MCP79 DDR PAD LEAKAGE IS HIGH ENOUGH THAT
NVIDIA RECOMMENDS UNPOWERING DURING SLEEP.
IN ORDER TO SUPPORT UNPOWERING RAIL, HARDWARE
MUST GUARANTEE MEM_CKE SIGNALS ARE LOW
BEFORE RAIL IS TURNED OFF, AND REMAINS LOW
UNTIL AFTER RAIL TURNS BACK ON OR DIMMS
WILL EXIT SELF-REFRESH PREMATURELY.
MEM_VTT_EN OUTPUT FROM MCP79 USED TO ENABLE CLAMP
ON VTT RAIL, WHICH PULLS ALL CKE SIGNALS
LOW THROUGH VTT TERMINATION RESISTORS.
R7975
10
8C7 =PPVTT_S0_VTTCLAMP 2 1 VTTCLAMP_L
8C3 =PP5V_S3_VTTCLAMP
=DDRVTT_EN
8D3 =PP1V5_S3_P1V5S0FET
R7976
100K
Q7975
SSM6N15FEAPE
SOT563
MCPDDR_SS
1
5%
1/16W
MF-LF
402
2
5%
1/10W
MF-LF
603
Q7975
SSM6N15FEAPE
SOT563
NO STUFF
1 C7976
0.001UF
20%
50V
CERM 2
402
1
MCPDDR_EN_L_RC
Preliminary
8C8
MCPDDR_EN_L
VTTCLAMP_EN
D 6
S 1
4
G
1
D
S
1 2 3
10%
10V
2
CERM
402
90mA max load @ 0.9V
81mW max power
5
CKT FROM T18
C7903
0.068UF
APPLE INC.
CRITICAL
Q7901
SI7108DN
PWRPK-1212-8-HF
=PP1V5_S0_FET
MOSFET
CHANNEL
RDS(ON)
LOADING
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
1.5V S0 FET
DRAWING NUMBER
NONE
SI7108DNS
N-TYPE
6 MOHM @3.5V VGS
5A (EDP)
POWER FETS
SYNC_MASTER=YUAN.MA SYNC_DATE=04/04/2008
8B8
051-7537
SHT OF
79 109
REV.
A
D
C
B
A

D
C
B
A
18B6
8 7 6 5 4 3 2 1
1R9002
2
D
G S
1 C9011
0.1UF
10%
2
16V
X5R
402
(LVDS DDC POWER)
1 C9012
10UF
20%
2 6.3V
X5R
603
SYM_VER-1
NC
NC
402
100K
5%
1/16W
MF-LF
R9023
1 10K 2
5%
1/16W
Q9004
MF-LF
SSM3K15FV
402
3
SOD-VESM-HF
1
2
1R9014
2
CRITICAL
L9008
120-OHM-0.3A-EMI
1 2
0402-LF
402
1
1
1K
5%
1/16W
MF-LF
1 C9009
0.001UF
10%
50V
2 CERM
402
4
CRITICAL
Q9003
FDC606P_G
SOT-6 6
5
2
1
3
0.001UF 0.001UF
10%
10%
50V
50V
X7R 2 X7R 2
402
402
1R9009
2
CRITICAL
L9080
90-OHM-200MA
AMC2012-SM
4
1
3
2
402
1R9008
100K
5%
1/16W
MF-LF
2402 8A3 =PP3V3_S5_LCD
LCDVDD_PWREN_L
LVDS_IG_PANEL_PWR
LCDVDD_PWREN_L_R
C9013
0.0033UF
1 2
10%
50V
CERM
402
L9004
FERR-120-OHM-1.5A
1 2
7C7 7C3 PP3V3_LCDVDD_SW_F
0402-LF
MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3VMIN_LINE_WIDTH=0.30 MM
PP3V3_LCDVDD_SW
MIN_NECK_WIDTH=0.20 MM
69C6 BKL_SYNC
VOLTAGE=3.3V
7C7 PP3V3_S0_LCD_F
MIN_LINE_WIDTH=0.30 MM
MIN_LINE_WIDTH=0.25 MM VOLTAGE=3.3V
MIN_NECK_WIDTH=0.20 MM
18B3 7C7 LVDS_IG_A_DATA_N
73B3
8C5 =PP3V3_S0_LCD
18B3 7C7 LVDS_IG_A_DATA_P
73B3
18B3 7C7 LVDS_IG_A_DATA_N
73B3
73B3 18B3 7C7 LVDS_IG_A_DATA_P
100K
5%
1/16W
MF-LF
73B3 18B3 7C7 LVDS_IG_A_DATA_N
73B3 18B3 7C7 LVDS_IG_A_DATA_P
18A3 7C7 LVDS_IG_DDC_CLK
18A3 7C7 LVDS_IG_DDC_DATA
73B3 7C7 LVDS_IG_A_CLK_F_N
73B3 7C7 LVDS_IG_A_CLK_F_P
73B3 18B3 LVDS_IG_A_CLK_N
73B3 18B3 LVDS_IG_A_CLK_P
69C1 69B3 7C7 7C3 PPVOUT_S0_LCDBKLT
69C1 7B7 LED_RETURN_1
69B1 7B7 LED_RETURN_2
69B1 7B7 LED_RETURN_3
69B1 7B7 LED_RETURN_4
69B1 7B7 LED_RETURN_5
LED_RETURN_6
S
G
D
Preliminary
LCD CONNECTOR
LVDS CONNECTOR:518S0650
8 7 6 5 4 3 2 1
C9015
69B1 7B7
C9010
APPLE INC.
NC
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
CRITICAL
J9000
20474-030E-11
F-RT-SM
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
33
34
SHT OF
90
LVDS I/F
LED BKLT I/F
LVDS CONNECTOR
SYNC_MASTER=NMARTIN SYNC_DATE=04/04/2008
REV.
051-7537 A
109
D
C
B
A

D
C
B
A
8 7 6 5 4 3 2 1
67D1
BI
Display Port Interoperability spec says that sources
or sinks which do both DP and DVI must depend on the
external adapter for pull ups on DDC lines (since DP
AUX CH has 100K pull up/down on the MLB)..
67D1
BI
DP_IG_DDC_DATA
DP_IG_DDC_CLK
73B3 18B6
73B3 18B6
68B8
IN
BI
BI
DP_IG_AUX_CH_P
DP_IG_AUX_CH_N
DP_CA_DET
R9300
1
R9301
1
R9306
33
5%
1/16W
MF-LF
402
33 2
5%
1/16W
MF-LF
402
1K
1
5%
1/16W
MF-LF
402
2
2
C9301
0.1UF
1
10%
16V
X5R
402
73B3
2
100K
5%
1/16W
MF-LF
2
402
3 D
=PP5V_S0_DP_AUX_MUX
8D5
DP_AUX_CH_SW_P
1 R9302
4 S G 5
3 D
2 S
Q9300
G 1
C9300
0.1UF
1
10%
16V
X5R
402
SSM6N15FEAPE
SOT563
DDC_CA_DET_LS5V_L
Q9301
SSM3K15FV
SOD-VESM-HF
DP_IG_CA_DET
73B3
2
DP_AUX_CH_SW_N
SSM6N15FEAPE
OUT 18B6
Q9300
SOT563
2 G
D 6
S 1
DP_AUX_CH_C_N
DP_AUX_CH_C_P
8 7 6 5 4 3 2 1
BI
BI
68B8 73B3
68C8 73B3
18B6 =MCP_HDMI_TXC_P
18B6 =MCP_HDMI_TXC_N
18B6 =MCP_HDMI_TXD_P
DP_ML_P
DP_ML_N
DP_ML_P
68C8 73C3
MAKE_BASE=TRUE
68C8 73B3
MAKE_BASE=TRUE
68C1 73C3
18B6 =MCP_HDMI_TXD_N
18B6 =MCP_HDMI_TXD_P
18B6 =MCP_HDMI_TXD_N
18B6 =MCP_HDMI_TXD_P
18B6 =MCP_HDMI_TXD_N
DP_ML_N
DP_ML_P
DP_ML_N
DP_ML_P
DP_ML_N
MAKE_BASE=TRUE
68B1 73B3
MAKE_BASE=TRUE
68C1 73C3
MAKE_BASE=TRUE
68C1 73B3
MAKE_BASE=TRUE
68C1 73C3
MAKE_BASE=TRUE
68C1 73B3
18B6 =MCP_HDMI_HPD
18A3 =MCP_HDMI_DDC_CLK
18A3 =MCP_HDMI_DDC_DATA
DP_HPD
DP_IG_DDC_CLK
DP_IG_DDC_DATA
MAKE_BASE=TRUE
68A8
MAKE_BASE=TRUE
67C8
MAKE_BASE=TRUE
67C8
MAKE_BASE=TRUE
Preliminary
SYNC_MASTER=AMASON
APPLE INC.
DISPLAYPORT SUPPORT
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
SYNC_DATE=04/18/2008
SHT OF
93 109
REV.
051-7537 A
D
C
B
A

D
C
B
A
73C3 67D1
73B3 67D1
73B3 67C4
73B3 67D4
IN
IN
BI
BI
8 7 6 5 4 3 2 1
64D5 41A5 39C5 34B7 21C3 7C3
DP_ML_P
DP_ML_N
DP_AUX_CH_C_P
DP_AUX_CH_C_N
68A8 8B5 =PP3V3_S0_DPCONN
67A7 OUT DP_CA_DET
IN
C9414 1 2 73C3 DP_ML_C_P
0.1uF
10% 16V X5R 402
C9415 1 2 73B3 DP_ML_C_N
0.1uF
10% 16V X5R 402
R9443
Q9440
2N7002DW-X-G
SOT-363
6
MCP79 requires pull
D
down HPD input with Q9441
2N7002DW-X-G
100K if DP_HPD is used. SOT-363
S
D
S
Port Power Switch
G
G
5 IN
TPS2051B
SOT23
OUT 1
4 EN
Q9440
2N7002DW-X-G
SOT-363
D
S
D
S
OC* 3
GND
2
Q9440 must have Drain to Gate leakage of 5MOhm
68B8 8B5 =PP3V3_S0_DPCONN
67D1 OUT DP_HPD
R9446
1
100K
5%
1/16W
MF-LF
402
2
8A3 =PP3V3_S5_DP_PORT_PWR
PM_SLP_S3_L
C9480
1
10UF
20%
6.3V
X5R
2
603
1
100K
5%
1/16W
MF-LF
402
2
6
1
1
R9445
10K
5%
1/16W
MF-LF
402
2
1
C9481
1
0.1UF
20%
10V
2
CERM
402
2
2
R9403 0
R9413 0
R9442
1
100K
5%
1/16W
MF-LF
402
2
DP_CA_DET_L_Q
R9444
3
4
1
10K
5%
1/16W
MF-LF
402
2
DP_HPD_L_Q
Q9441
2N7002DW-X-G
SOT-363
3
4
CRITICAL
U9480
G
G
12-OHM-100MA
TCM1210-4SM
4 SYM_VER-2 1
5
5
NO STUFF
C9485
1
10UF
20%
6.3V
X5R
2
603
FL9403
3 2
R9420
1
100K
5%
1/16W
MF-LF
402
2
NO STUFF
1 2
5%
NO STUFF
1/16W MF-LF 402
1 2
5% 1/16W MF-LF 402
DP_HPD_Q
1
TP_DPPWR_OC_L
CRITICAL
C9486
22UF
20%
2
6.3V
X5R-CERM
603
R9421
1
100K
5%
1/16W
MF-LF
402
2
DP_CA_DET_Q
R9422
1
1M
5%
1/16W
MF-LF
402
2
R9423
PP3V3_S0_DPILIM
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V
1
100K
5%
1/16W
MF-LF
402
2
73B3
73B3
DP_ESD
CRITICAL
D9411
RCLAMP0524P
SLP2510P8
2 IO IO 1
9 NC NC 10
GND
DP to DVI/HDMI
Cable Adapter
(CA) has 100k
pull-up to DP_PWR.
3
R9425
1M
DP Source must pull
down HPD input with
greater than or equal
to 100K (DPv1.1a).
1
5%
1/16W
MF-LF
402
2
DP_ML_CONN_P
DP_ML_CONN_N
HDMI_CEC
1
L9400
FERR-120-OHM-3A
C9400
0.01UF
10%
16V
2
CERM
402
1 2
0603
PP3V3_S0_DPPWR
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V
D9400
RCLAMP0504F
1
3
DP_ESD
CRITICAL
8 7 6 5 4 3 2 1
SC70-6-1
SHIELD PINS
6
2 5
CRITICAL
J9400
DSPLYPRT-M97-2
F-RT-THSM
4
22
21
514-0610
R9401
R9431
DP_ESD
CRITICAL
D9410
RCLAMP0524P
SLP2510P8
5 IO IO 4
6 NC NC 7
BOT ROW
TOP ROW
73B3 DP_ML_CONN_P
2
4
TH PINS
DP_HPD
DP_C_A_DET
SM PINS
GND
ML_LANE0P
1
3
73B3 DP_ML_CONN_N
FL9401
6
HDMI_CEC ML_LANE0N
5
8
10
12
GND
ML_LANE3P
ML_LANE3N
7
GND
9 73B3 DP_ML_CONN_P
ML_LANE1P
73B3 11 DP_ML_CONN_N
ML_LANE1N
2 3
14
16
GND
AUX_CHP
GND
ML_LANE2P
13
15
73B3 DP_ML_CONN_P
18
20
AUX_CHN
DP_PWR
ML_LANE2N
RETURN
17
19
73B3 DP_ML_CONN_N
GND
0
0
3
12-OHM-100MA
TCM1210-4SM
1 SYM_VER-2 4
DP_ESD
CRITICAL
D9411
RCLAMP0524P
SLP2510P8
5 IO IO 4
6 NC NC 7
GND
3
R9402 0
R9432 0
DP_ESD
CRITICAL
D9410
RCLAMP0524P
SLP2510P8
2 IO IO 1
9 NC NC 10
GND
3
R9400 0
R9430
NO STUFF
0 1 2
1 2
5%
NO STUFF
1/16W MF-LF 402
1 2
5% 1/16W MF-LF 402
FL9402
12-OHM-100MA
TCM1210-4SM
1 SYM_VER-2 4
2
NO STUFF
1 2
3
5% 1/16W MF-LF 402
NO STUFF
12-OHM-100MA
1 SYM_VER-2 4
TCM1210-4SM
2
NO STUFF
1 2
FL9400
5% 1/16W
5% 1/16W MF-LF 402
NO STUFF
1 2
5% 1/16W MF-LF 402
3
MF-LF 402
73C3 DP_ML_C_P
73B3 DP_ML_C_N
73C3 DP_ML_C_P
73B3 DP_ML_C_N
73C3 DP_ML_C_P
73B3 DP_ML_C_N
Preliminary
SYNC_MASTER=AMASON
APPLE INC.
C9410 1 2 DP_ML_P
0.1uF
10% 16V X5R 402
C9411 1 2 DP_ML_N
0.1uF
10% 16V X5R 402
C9412 1 2 DP_ML_P
0.1uF
10% 16V X5R 402
C9413 1 2 DP_ML_N
0.1uF
10% 16V X5R 402
C9416 1 2 DP_ML_P
0.1uF
10% 16V X5R 402
C9417 1 2 DP_ML_N
0.1uF
10% 16V X5R 402
DisplayPort Connector
SCALE
NONE
IN 67D1 73C3
IN 67D1 73B3
IN 67D1 73C3
IN 67D1 73B3
IN 67D1 73C3
IN 67D1 73B3
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
DRAWING NUMBER
051-7537
SYNC_DATE=06/30/2008
SHT OF
94 109
REV.
A
D
C
B
A

D
C
B
A
69A8 7C3
69C4 69B6
BKL_VREF_4V9
70A7 18B6
IN
8 7 6 5 4 3 2 1
1 2
1 2
R9707
3.01K
1%
1/16W
MF-LF
402
PLACEMENT_NOTE=Away from Q9701
PLACEMENT_NOTE=Away from Q9701
R9708
100K
1%
1/16W
MF-LF
402
69C8 69C4 69B6 7C3
BKL_SSTCMP_RC
1
LVDS_IG_BKL_PWM
C9705
0.1UF
20%
10V
2 CERM
402
R9700
100K
1%
1/16W
MF-LF
402
2
1
BKL_VREF_4V9
CRITICAL
Q9702
NTUD3127CXXG
SOT-963
2
1 C9703
1UF
10%
10V
2 X5R
402-1
N-CHN
G
S
6
G
D
S
1
70C3 69C7
CRITICAL
Q9702
NTUD3127CXXG
SOT-963
4
2
1
5
D
3
P-CHN
IN
PLACEMENT_NOTE=Away from Q9701
R9709
1K
1%
1/16W
MF-LF
402
BKL_PWR_EN_L
69D6 69C3 69B4 GND_BKL_PWRGND
PLACEMENT_NOTE=Place near C9701
69D7 PPBUS_S0_LCDBKLT_PWR
70C3
R9703
2.0M
5%
1/16W
MF-LF
402
NOSTUFF
PPBUS_S0_LCDBKLT_PWR
BKL_VREF_IN_4V9
2
1
2
1
R9731
1
2
187K
1%
1/16W
MF-LF
402
R9710
10K
1%
1/16W
MF-LF
402
R9711
30.1K
1%
1/16W
MF-LF
402
VOLTAGE=12.6V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.4 mm
XW9701
1
SM
2
69D7 69C3 69B4
1 C9713
0.1UF
10%
25V
2
X5R
402
*R9707, R9708, R9709, R9713, R9714, R9727, AND R9729 SHOULD AWAY FROM BOOST CIRCUIT
2
1
BKLT_PWM_RC
69C4 69A8 7C3
69C8
66C2
R9705
100K
1%
1/16W
MF-LF
402
IN
2 1
R9733
5%
MF-LF
402
0
1 C9706 1/16W
0.0022UF
10%
50V
2 CERM
402
NOSTUFF
PLACEMENT_NOTE=Away from Q9701
2
R9730
0.1
1%
1/6W
MF
402-HF
GND_BKL_PWRGND
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.5MM
BKL_VREF_4V9
1
BKLT_EN
2
1
1 C9714
1UF
10%
10V
2 X5R
402
NOSTUFF
R9713
0
5%
1/16W
MF-LF
402
BKLT_PLL_NOT
10UF
10%
25V
2
X5R
805
BKL_SYNC
CRITICAL
1
C9701
BKLT_PLL
2 1
R9734
0
5%
1/16W
MF-LF
402
BKLT_PLL
1
PPVIN_S0_LCDBKLT_BUF
VOLTAGE=12.6V
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.5MM
PLACEMENT_NOTE=Place near L9701
C9707
2.2UF
20%
6.3V
2 CERM
402-LF
PLACEMENT_NOTE=Away from Q9701
2
1
BKL_VSYNC
2
1
BKL_LPF
BKLT_PLL
R9714
10K
5%
1/16W
MF-LF
402
R9706
10K
5%
1/16W
MF-LF
402
BKL_ISET
BKL_RT
BKL_SSTCMP
BKL_DIM
BKLT_PLL
BKL_LRT_RC
1
0.1UF
10%
25V
2 X5R
402
C9708
1 2
*Q9701, D9701, C9709, C9710, L9701, R9702, AND R9715 SHOULD ALL BE PLACED NEAR EACHOTHER.
*BOOST_FET_CNTL AND PPVOUT_S0_LCDBKLT_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.
5 ENA
17 VSYNC
GNDA
DRV 1
ISWSEN 2
ISEN1 10
8 ISET ISEN2 11
CRITICAL
6 RT
ISEN3 12
8 7 6 5 4 3 2 1
2
1
R9727
15.0K
1%
1/16W
MF-LF
402
1
7 SSTCMP
20 DIM
19 LPF
18 LRT
VIN
4 VREF QFN
1
C9702
0.1UF
10%
25V
2
X5R
402
BKL_VREF_4V9
BKL_LRT
69D7 69D6 69C3
13
CRITICAL
L9701
22UH-2.5A
3
U9701
APP001A
ISEN4 14
ISEN5 15
ISEN6 16
VSEN 9
THRM_PAD
21
PLACEMENT_NOTE=Away from Q9701
2
PPVOUT_S0_LCDBKLT_SW
VOLTAGE=30V
IHLP2525CZ-SM
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
R9701
SWITCH_NODE=TRUE
PLACEMENT_NOTE=Place near Q9701
100
1%
1/16W
MF-LF
402
PLACEMENT_NOTE=Place near PPVOUT_S0_LCDBKLT_SW
BKL_VIN
7C3 69A8
69B6 69C8
GND_BKL_PWRGND
BOOST_FET_CNTL
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.6MM
BKL_ISEN1
BKL_ISEN2
BKL_ISEN3
BKL_ISEN4
BKL_ISEN5
BKL_ISEN6
BKL_VSEN
2
1
3
BOOST_SINK
R9704
100
1%
1/16W
MF-LF
402
G
2
1
D
S
4
R9702
0.4
1%
1/6W
MF
402
PLACEMENT_NOTE=Place near Q9701
D9701
POWERDI-123
1
DFLS1100
CRITICAL
SM
GND_BKL_PWRGND_X
MIN_NECK_WIDTH=0.20MM
1 2
MIN_LINE_WIDTH=0.5MM
PLACEMENT_NOTE=Place near C9709 and Q9701
*R9702 AND R9715 PIN 1 SHOULD BE PLACED NEAR C9709 PIN 2
2
1
2
1
1 C9712
47PF
5%
50V
2 CERM
402
NOSTUFF
1 2 5 6
R9723
1.2M
1%
1/10W
MF-LF
603
R9724
71.5K
1%
1/16W
MF-LF
402
Q9701
FDC5612
SSOT6
PLACEMENT_NOTE=Place near C9709
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.5MM
2
69D7 69D6 69B4 GND_BKL_PWRGND
PLACEMENT_NOTE=Place near C9709 and Q9701
2
1
R9715
0.4
1%
1/6W
MF
402
PPVOUT_S0_LCDBKLT
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
PLACEMENT_NOTE=Place near C9710
XW9702
PLACEMENT_NOTE=Place near J9000
CRITICAL CRITICAL
1 C9709 1 C9710
4.7UF 4.7UF
10%
50V
2 X7R-CERM
10%
50V
2 X7R-CERM
1206
1206
R9717
10.2
1
2
0.1%
1/16W
TF
402
R9718
10.2
1 2
0.1%
1/16W
TF
402
R9719
10.2
1 2
0.1%
1/16W
TF
402
R9720
10.2
1 2
0.1%
1/16W
TF
402
R9721
10.2
1 2
0.1%
1/16W
TF
402
R9722
10.2
1 2
0.1%
1/16W
TF
402
PPVOUT_S0_LCDBKLT
LED_RETURN_1
LED_RETURN_2
LED_RETURN_3
LED_RETURN_4
LED_RETURN_5
LED_RETURN_6
Preliminary
7C3 7C7 66B2 69C1
SYNC_MASTER=YITE
APPLE INC.
SCALE
NONE
OUT 7C3 7C7 66B2
69B3
OUT
LCD BACKLIGHT DRIVER
OUT
OUT
OUT
OUT
OUT
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
VOLTAGE=30V
MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
DRAWING NUMBER
SHT OF
97
7B7 66B3
7B7 66B3
7B7 66B3
7B7 66B3
7B7 66B3
7B7 66B3
SYNC_DATE=08/12/2008
REV.
051-7537 A
109
D
C
B
A

D
C
B
A
8 7 6 5 4 3 2 1
8C1
70B7 18B6
26C1
IN
IN
IN
1
2 402
1K
5%
1/16W
MF-LF
=PPBUS_S0_LCDBKLT
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V
R9840
LVDS_IG_BKL_ON
BKLT_PLT_RST_L
1
R9841
2 402
1K
5%
1/16W
MF-LF
LVDS_IG_BKL_ON
LVDS_IG_BKL_PWM
18B6 70C8
18B6 69A8
1
F9800
2AMP-32V
0402-HF
2
PPBUS_S0_LCDBKLT_FUSED
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
1
VOLTAGE=12.6V
R9808
301K
Q9807
SSM6N15FEAPE
SOT563
5 G
1%
1/16W
2 402
MF-LF
D 3
S 4
2 G
1 C9802
0.1UF
10%
16V
2 X5R
402
PPBUS_S0_LCDBKLT_EN_L
BKLT_EN_L
Q9807
SSM6N15FEAPE
SOT563
PPBUS_S0_LCDBKLT_EN_DIV
D 6
S 1
1
R9809
147K
1%
2 402
1/16W
MF-LF
FDC638APZ_SBMS001
SSOT6-HF
4
Q9806
3
6
5
2
1
PPBUS S0 LCDBkLT FET
8 7 6 5 4 3 2 . 1
MOSFET
CHANNEL
RDS(ON)
LOADING
FDC638APZ
P-TYPE
43 mOhm @4.5V
0.4 A (EDP)
PPBUS_S0_LCDBKLT_PWR
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V
OUT 69C7 69D7
Preliminary
SYNC_MASTER=YITE
APPLE INC.
LCD Backlight Support
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
SHT OF
98
SYNC_DATE=06/30/2008
REV.
051-7537 A
109
D
C
B
A

D
C
B
A
PHYSICAL_RULE_SET
8 7 6 5 4 3 2 1
FSB (Front-Side Bus) Constraints CPU / FSB Net Properties
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
FSB_50S * =50_OHM_SE
=50_OHM_SE
=50_OHM_SE =50_OHM_SE =STANDARD
=STANDARD
FSB_DSTB_50S *
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=1:1_DIFFPAIR
=1:1_DIFFPAIR
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
FSB_DATA * =2x_DIELECTRIC
?
FSB_DSTB * =3x_DIELECTRIC
FSB_ADDR *
=STANDARD
?
FSB_ADSTB * =2x_DIELECTRIC
?
FSB_1X *
=STANDARD
?
PHYSICAL_RULE_SET
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
PHYSICAL_RULE_SET
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
PHYSICAL_RULE_SET
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended.
FSB 1X signals shown in signal table on right.
Signals within each 1x group should be matched to CPU clock, +0/-1000 mils.
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
FSB 4X signals / groups shown in signal table on right.
Signals within each 4x group should be matched within 5 ps of strobe.
DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 300 ps.
Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s.
DSTB# complementary pairs are spaced normally and are NOT routed as differential pairs.
FSB 2X signals / groups shown in signal table on right.
Signals within each 2x group should be matched within 20 ps. ADTSB#s should be matched +/- 300 ps.
Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#.
Design Guide recommends each strobe/signal group is routed on the same layer.
Intel Design Guide recommends FSB signals be routed only on internal layers.
NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened.
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2
SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3
CPU Signal Constraints
CPU_27P4S
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
CPU_50S * =50_OHM_SE =50_OHM_SE
=50_OHM_SE =50_OHM_SE
=STANDARD =STANDARD
NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.
CPU_AGTL * =STANDARD
?
CPU_8MIL *
8 MIL
?
CPU_COMP * 25 MIL
CPU_GTLREF * 25 MIL
?
CPU_ITP * =2:1_SPACING
?
CPU_VCCSENSE *
25 MIL
?
Most CPU signals with impedance requirements are 55-ohm single-ended.
Some signals require 27.4-ohm single-ended impedance.
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2
SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4
MCP FSB COMP Signal Constraints
MCP_FSB_COMP
FSB Clock Constraints
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
SR DG recommends at least 25 mils, >50 mils preferred
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
MCP_50S * =50_OHM_SE =50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD =STANDARD
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.4
CLK_FSB_100D
CLK_FSB *
* =27P4_OHM_SE =27P4_OHM_SE
=27P4_OHM_SE =27P4_OHM_SE 7 MIL
7 MIL
* 8 MIL
?
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
*
=3x_DIELECTRIC ?
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.5
?
?
FSB_DATA TOP,BOTTOM =4x_DIELECTRIC
?
FSB_DSTB TOP,BOTTOM =5x_DIELECTRIC
?
FSB_ADDR TOP,BOTTOM =3x_DIELECTRIC
?
FSB_ADSTB TOP,BOTTOM =4x_DIELECTRIC
?
FSB_1X TOP,BOTTOM =3x_DIELECTRIC
?
CPU_AGTL TOP,BOTTOM =2x_DIELECTRIC
?
=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
=100_OHM_DIFF
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
CLK_FSB TOP,BOTTOM =4x_DIELECTRIC
?
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
=100_OHM_DIFF
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
FSB 4X Signal Groups
FSB 2X
Signals
FSB 1X Signals
ELECTRICAL_CONSTRAINT_SET
CPU_VCCSENSE
(CPU_VCCSENSE)
(CPU_VCCSENSE)
8 7 6 5 4 3 2 1
FSB_DATA_GROUP0
FSB_DATA_GROUP0
(See above)
(FSB_CPURST_L)
PHYSICAL
FSB_50S
FSB_1X FSB_50S
CPU_ASYNC CPU_50S
NET_TYPE
SPACING
FSB_DATA
FSB_DSTB0 FSB_DSTB_50S FSB_DSTB
FSB_DSTB0 FSB_DSTB_50S
FSB_DATA_GROUP1 FSB_50S
FSB_DATA_GROUP1 FSB_50S
FSB_DSTB1 FSB_DSTB_50S
FSB_DSTB1 FSB_DSTB_50S FSB_DSTB
FSB_1X
CPU_AGTL
FSB_D_L
FSB_DINV_L
FSB_DSTB_L_P
FSB_DSTB_L_N
FSB_D_L
FSB_DINV_L
FSB_DSTB_L_P
FSB_DSTB_L_N
FSB_DATA_GROUP2 FSB_50S
FSB_DATA FSB_D_L
FSB_DATA_GROUP2 FSB_50S
FSB_DATA FSB_DINV_L
FSB_DSTB2 FSB_DSTB_50S FSB_DSTB FSB_DSTB_L_P
FSB_DSTB2 FSB_DSTB_50S FSB_DSTB FSB_DSTB_L_N
FSB_DATA_GROUP3
FSB_50S
FSB_DATA FSB_D_L
FSB_DATA_GROUP3 FSB_50S
FSB_DATA FSB_DINV_L
FSB_DSTB3 FSB_DSTB_50S FSB_DSTB FSB_DSTB_L_P
FSB_DSTB3 FSB_DSTB_50S FSB_DSTB FSB_DSTB_L_N
FSB_ADDR_GROUP0 FSB_50S
FSB_ADDR FSB_A_L
FSB_ADDR_GROUP0
FSB_50S FSB_ADDR FSB_REQ_L
FSB_ADSTB0
FSB_50S FSB_ADSTB FSB_ADSTB_L
FSB_ADDR_GROUP1 FSB_50S
FSB_ADSTB1
FSB_1X FSB_50S
FSB_BREQ0_L FSB_50S
FSB_BREQ1_L
FSB_1X FSB_50S
FSB_1X FSB_50S
FSB_1X FSB_50S
FSB_1X FSB_50S
FSB_1X FSB_50S
FSB_1X FSB_50S
FSB_1X FSB_50S
FSB_CPURST_L FSB_50S
FSB_1X FSB_50S
FSB_1X FSB_50S
CPU_BSEL CPU_50S
CPU_FERR_L CPU_50S
CPU_ASYNC CPU_50S
CPU_INIT_L CPU_50S
CPU_ASYNC_R CPU_50S
CPU_ASYNC_R CPU_50S
CPU_PROCHOT_L CPU_50S
CPU_PWRGD CPU_50S
CPU_ASYNC CPU_50S
CPU_ASYNC CPU_50S
PM_THRMTRIP_L CPU_50S
FSB_CPUSLP_L CPU_50S
CPU_FROM_SB CPU_50S
CPU_DPRSTP_L CPU_50S
CPU_ASYNC CPU_50S
MCP_CPU_COMP MCP_50S
MCP_FSB_COMP
MCP_CPU_COMP MCP_50S
MCP_FSB_COMP
MCP_CPU_COMP MCP_50S
MCP_FSB_COMP
MCP_CPU_COMP MCP_50S
MCP_FSB_COMP
FSB_CLK_CPU
FSB_CLK_CPU
FSB_CLK_ITP
FSB_CLK_ITP
FSB_CLK_MCP
FSB_CLK_MCP
CPU_IERR_L
PM_DPRSLPVR CPU_50S
CPU_GTLREF
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TCK
XDP_TRST_L
XDP_BPM_L
XDP_BPM_L5
CPU_VCCSENSE
FSB_50S
FSB_50S FSB_ADSTB
FSB_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_27P4S
CPU_50S
CPU_27P4S CPU_COMP
CPU_50S
CPU_50S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
FSB_DATA
FSB_DSTB
FSB_DATA
FSB_DATA
FSB_DSTB
FSB_ADDR
FSB_1X
FSB_1X
FSB_1X
FSB_1X
FSB_1X
FSB_1X
FSB_1X
FSB_1X
FSB_1X
FSB_1X
FSB_1X
FSB_1X
FSB_1X
CPU_AGTL
CPU_8MIL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_8MIL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_GTLREF
CPU_COMP
CPU_COMP
CPU_COMP
CPU_8MIL
CPU_8MIL
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
FSB_A_L
FSB_ADSTB_L
FSB_ADS_L
FSB_BREQ0_L
FSB_BREQ1_L
FSB_BNR_L
FSB_BPRI_L
FSB_DBSY_L
FSB_DEFER_L
FSB_DRDY_L
FSB_HIT_L
FSB_HITM_L
FSB_LOCK_L
FSB_CPURST_L
FSB_RS_L
FSB_TRDY_L
CPU_A20M_L
CPU_BSEL
CPU_FERR_L
CPU_IGNNE_L
CPU_INIT_L
CPU_INTR
CPU_NMI
CPU_PROCHOT_L
CPU_PWRGD
CPU_SMI_L
CPU_STPCLK_L
PM_THRMTRIP_L
FSB_CPUSLP_L
CPU_DPSLP_L
CPU_DPRSTP_L
FSB_DPWR_L
MCP_BCLK_VML_COMP_VDD
MCP_BCLK_VML_COMP_GND
MCP_CPU_COMP_VCC
MCP_CPU_COMP_GND
CLK_FSB_100D CLK_FSB FSB_CLK_CPU_P
CLK_FSB_100D CLK_FSB FSB_CLK_CPU_N
CLK_FSB_100D CLK_FSB
FSB_CLK_ITP_P
CLK_FSB_100D CLK_FSB
FSB_CLK_ITP_N
CLK_FSB_100D CLK_FSB
FSB_CLK_MCP_P
CLK_FSB_100D CLK_FSB
FSB_CLK_MCP_N
CPU_IERR_L
PM_DPRSLPVR
IMVP_DPRSLPVR
CPU_GTLREF
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_50S
CPU_ITP
XDP_TDI
CPU_50S
CPU_ITP
XDP_TDO
CPU_50S
CPU_ITP
XDP_TMS
CPU_50S
CPU_ITP
XDP_TCK
CPU_50S
CPU_ITP
XDP_TRST_L
CPU_50S
CPU_ITP
XDP_BPM_L
CPU_50S
CPU_ITP
XDP_BPM_L
CPU_50S CPU_ITP XDP_CPURST_L
CPU_VID
IMVP6_VID
CPU_VCCSENSE_P
CPU_VCCSENSE_N
IMVP6_VSEN_P
IMVP6_VSEN_N
10C4 14D3
10C4 14D6
10C4 14D6
10C4 14D6
10B4 10C4 14C3 14D3
10B4 14D6
10B4 14D6
10B4 14D6
10C2 14B3 14C3
10C2 14D6
10C2 14D6
10C2 14D6
10B2 10C2 14B3
10B2 14D6
10B2 14D6
10B2 14D6
10D8 14C6 14D6
10D8 14B6
10D8 14B6
10C8 14B6 14C6
10C8 14B6
10D6 14B6
9B2 10D6 14B6
10D6 14B6
10D6 14B3
10D6 14B6
10D6 14B3
10D6 14B6
10C6 14B6
10C6 14B6
10D6 14B6
9B2 10D6 13B2 14A3
10D6 14A6
10D6 14B6
10C8 14A3
9C2 10A4 10B4
10C8 14B7
10C8 14A3
10D6 14A3
9B2 10B8 14A3
9B2 10B8 14A3
10C5 14B6 40D4 60C8
10B2 13C7 14A3
10B8 14A3
10B8 14A3
10C6 14B7 40C4
10A2 14A3
10B2 14A3
9B2 10B2 14A3 60C7
Preliminary
14B6
10B2 14A3
14A6
14A6
14A6
14A6
10B6 14B3
10B6 14B3
13C3 14A3
13B3 14A3
14A4
14A4
10D6
21C7 60D8
60C7
10B4 27B1
10B3
10B3
10B3
10B3
6C6 10B6 10C6 13B3
6C4 10B6 10C6
6C6 6C7 10B6 10C6 13B3
6C6 6C7 10A6 10C6 13B6
6C6 6C7 10A6 10C6 13B3
10C6 13C6
10C5 13C6
13B4
11B6 60C7
11A5 60A5
11A5 60A5
APPLE INC.
CPU/FSB Constraints
SYNC_MASTER=T18_MLB SYNC_DATE=01/04/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
051-7537
SHT OF
100 109
REV.
A
D
C
B
A

D
C
B
A
PHYSICAL_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2
NET_SPACING_TYPE1 NET_SPACING_TYPE2
PHYSICAL_RULE_SET
8 7 6 5 4 3 2 1
Memory Bus Constraints
MEM_40S
MEM_40S_VDD
NET_SPACING_TYPE1 NET_SPACING_TYPE2
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
MEM_70D * =70_OHM_DIFF =70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
MEM_70D_VDD * =70_OHM_DIFF =70_OHM_DIFF
=70_OHM_DIFF =70_OHM_DIFF
=70_OHM_DIFF =70_OHM_DIFF
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
MEM_CLK2MEM
MEM_CTRL2CTRL
MEM_CTRL2MEM
TABLE_SPACING_ASSIGNMENT_HEAD
AREA_TYPE SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
AREA_TYPE SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
AREA_TYPE SPACING_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
Memory Bus Spacing Group Assignments
MEM_DQS MEM_CLK
*
MEM_DQS2MEM
MEM_DQS MEM_CTRL
*
MEM_DQS2MEM
MEM_DQS MEM_CMD
* =40_OHM_SE =40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=STANDARD
=STANDARD
* =40_OHM_SE =40_OHM_SE =40_OHM_SE =40_OHM_SE
=STANDARD
=STANDARD
*
* =2:1_SPACING
*
=4:1_SPACING ?
=2.5:1_SPACING ?
MEM_CMD2CMD *
=1.5:1_SPACING
MEM_CMD2MEM
MEM_DATA2DATA
MEM_DATA2MEM
*
*
=3:1_SPACING ?
=1.5:1_SPACING ?
* =3:1_SPACING
MEM_DQS2MEM *
=3:1_SPACING ?
MEM_2OTHER *
25 MIL
MEM_CLK
MEM_CLK
MEM_CLK
MEM_CTRL
* MEM_CLK2MEM
* MEM_CLK2MEM
MEM_CLK MEM_CMD
*
MEM_CLK2MEM
MEM_CLK MEM_DATA
*
* MEM_DQS2MEM
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_HEAD
NET_SPACING_TYPE1 NET_SPACING_TYPE2
NET_SPACING_TYPE1 NET_SPACING_TYPE2
Need to support MEM_*-style wildcards!
DDR2:
DQ signals should be matched within 20 ps of associated DQS pair.
DQS intra-pair matching should be within 1 ps, no inter-pair matching requirement.
All DQS pairs should be matched within 100 ps of clocks.
CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 140 ps.
A/BA/cmd signals should be matched within 75 ps, no CLK matching requirement.
All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).
DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.
DDR3:
DQ signals should be matched within 5 ps of associated DQS pair.
DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 180 ps
No DQS to clock matching requirement.
CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps.
A/BA/cmd signals should be matched within 5 ps of CLK pairs.
All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).
DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2
MCP MEM COMP Signal Constraints
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3.4
?
?
?
?
MEM_CLK2MEM
MEM_CLK MEM_DQS
*
MEM_CLK2MEM
MEM_CTRL
MEM_CLK *
MEM_CTRL2MEM
MEM_CTRL MEM_CTRL *
MEM_CTRL2CTRL
MEM_CTRL MEM_CMD
*
MEM_CTRL2MEM
MEM_CTRL MEM_DATA
* MEM_CTRL2MEM
MEM_CTRL MEM_DQS
*
MEM_CTRL2MEM
MEM_DQS MEM_DATA
*
MEM_DQS2MEM
MEM_DQS MEM_DQS
* MEM_DQS2MEM
MEM_CMD
TABLE_SPACING_ASSIGNMENT_HEAD
AREA_TYPE SPACING_RULE_SET
MEM_CLK *
MEM_CMD2MEM
MEM_CMD MEM_CTRL *
MEM_CMD2MEM
MEM_CMD MEM_CMD
*
MEM_CMD2CMD
MEM_CMD MEM_DATA *
MEM_CMD2MEM
MEM_CMD MEM_DQS *
MEM_CMD2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
AREA_TYPE SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DATA MEM_CLK
*
MEM_DATA2MEM
MEM_DATA
MCP_MEM_COMP *
Y 7 MIL 7 MIL =STANDARD
MCP_MEM_COMP
* 8 MIL
?
MEM_CTRL *
MEM_DATA2MEM
MEM_DATA MEM_CMD *
MEM_DATA2MEM
MEM_DATA MEM_DATA
*
MEM_DATA2DATA
MEM_DATA MEM_DQS *
MEM_DATA2MEM
MEM_CLK * *
MEM_2OTHER
MEM_CTRL *
*
MEM_2OTHER
MEM_CMD * *
MEM_2OTHER
MEM_DATA *
*
MEM_2OTHER
MEM_DQS * *
MEM_2OTHER
=STANDARD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
=STANDARD
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
Memory Net Properties
ELECTRICAL_CONSTRAINT_SET PHYSICAL
SPACING
MEM_A_CNTL MEM_40S_VDD
MEM_A_DQ_BYTE7 MEM_40S
8 7 6 5 4 3 2 1
MEM_A_DQS6
MEM_70D
NET_TYPE
MEM_A_CLK MEM_70D_VDD MEM_CLK
MEM_A_CLK MEM_70D_VDD MEM_CLK
MEM_A_CNTL MEM_40S_VDD
MEM_A_CNTL MEM_40S_VDD
MEM_A_CMD MEM_40S_VDD MEM_CMD MEM_A_A
MEM_A_CMD MEM_40S_VDD MEM_CMD
MEM_A_BA
MEM_A_CMD
MEM_40S_VDD MEM_CMD
MEM_A_RAS_L
MEM_A_CMD MEM_40S_VDD MEM_CMD
MEM_A_CAS_L
MEM_A_CMD
MEM_40S_VDD MEM_CMD
MEM_A_WE_L
MEM_A_DQ_BYTE0
MEM_A_DQ_BYTE1
MEM_A_DQ_BYTE2
MEM_A_DQ_BYTE4 MEM_40S
MEM_A_DQ_BYTE5 MEM_40S
MEM_DATA
MEM_A_DQS0 MEM_70D
MEM_DQS
MEM_A_DQS5
MEM_A_DQS7
MEM_B_CLK
MEM_B_CLK
MEM_70D
MEM_70D
MEM_DQS
MEM_DQS
MEM_DQS
MEM_B_CNTL MEM_40S_VDD MEM_CTRL
MEM_B_CNTL MEM_40S_VDD MEM_CTRL
MEM_A_DM
MEM_A_DM
MEM_A_DM
MEM_A_DM
MEM_A_DM
MEM_A_DM
MEM_A_DM
MEM_A_DM
MEM_A_DQS_P
MEM_A_DQS_N
MEM_A_DQS_P
MEM_A_DQS_N
MEM_A_DQS_P
MEM_A_DQS_N
MEM_A_DQS_P
MEM_A_DQS_N
MEM_A_DQS_P
MEM_A_DQS_N
MEM_A_DQS_P
MEM_A_DQS_N
MEM_A_DQS_P
MEM_A_DQS_N
MEM_A_DQS_P
MEM_A_DQS_N
MEM_70D_VDD MEM_CLK
MEM_B_CLK_P
MEM_70D_VDD MEM_CLK MEM_B_CLK_N
MEM_B_CKE
MEM_B_CS_L
MEM_B_ODT
MEM_B_CMD MEM_40S_VDD MEM_CMD MEM_B_A
MEM_B_CMD
MEM_40S_VDD MEM_CMD
MEM_B_BA
MEM_B_CMD
MEM_40S_VDD MEM_CMD
MEM_B_RAS_L
MEM_B_CMD
MEM_40S_VDD MEM_CMD
MEM_B_CAS_L
MEM_B_CMD
MEM_40S_VDD MEM_CMD
MEM_B_WE_L
MEM_B_DQ_BYTE0
MEM_40S MEM_DATA MEM_B_DQ
MEM_B_DQ_BYTE1
MEM_40S MEM_DATA MEM_B_DQ
MEM_B_DQ_BYTE2
MEM_40S MEM_DATA MEM_B_DQ
MEM_B_DQ_BYTE3
MEM_40S MEM_DATA MEM_B_DQ
MEM_B_DQ_BYTE4 MEM_40S MEM_DATA MEM_B_DQ
MEM_B_DQ_BYTE5
MEM_40S MEM_DATA MEM_B_DQ
MEM_B_DQ_BYTE6
MEM_40S MEM_DATA MEM_B_DQ
MEM_B_DQ_BYTE7
MEM_40S MEM_DATA MEM_B_DQ
MEM_B_DQ_BYTE0
MEM_B_DQ_BYTE1
MEM_B_DQ_BYTE2
MEM_B_DQ_BYTE3
MEM_B_DQ_BYTE4
MEM_B_DQ_BYTE5
MEM_B_DQ_BYTE6
MEM_B_DQ_BYTE7
MEM_40S
MEM_40S
MEM_A_DQ_BYTE3 MEM_40S
MEM_A_DQ_BYTE6
MEM_A_DQ_BYTE7
MEM_40S
MEM_40S
MEM_40S
MEM_A_DQ_BYTE0 MEM_40S
MEM_A_DQ_BYTE1 MEM_40S
MEM_A_DQ_BYTE2 MEM_40S
MEM_A_DQ_BYTE3 MEM_40S
MEM_A_DQ_BYTE4 MEM_40S
MEM_A_DQ_BYTE5 MEM_40S
MEM_A_DQ_BYTE6 MEM_40S
MEM_A_DQS0
MEM_A_DQS2
MEM_A_DQS2
MEM_A_DQS3
MEM_A_DQS4
MEM_A_DQS4
MEM_A_DQS5
MEM_A_DQS6
MEM_A_DQS7
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_A_DQS1 MEM_70D
MEM_DQS
MEM_A_DQS1
MEM_A_DQS3
MEM_70D
MEM_70D
MEM_70D
MEM_CTRL
MEM_CTRL
MEM_CTRL
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_B_CNTL MEM_40S_VDD MEM_CTRL
MEM_40S MEM_DATA
MEM_40S MEM_DATA
MEM_40S MEM_DATA
MEM_40S MEM_DATA
MEM_40S MEM_DATA
MEM_40S MEM_DATA
MEM_40S MEM_DATA
MEM_40S MEM_DATA
MEM_A_CLK_P
MEM_A_CLK_N
MEM_A_CKE
MEM_A_CS_L
MEM_A_ODT
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_A_DQ
MEM_B_DM
MEM_B_DM
MEM_B_DM
MEM_B_DM
MEM_B_DM
MEM_B_DM
MEM_B_DM
MEM_B_DM
MEM_B_DQS0
MEM_70D MEM_DQS
MEM_B_DQS_P
MEM_B_DQS0
MEM_70D MEM_DQS
MEM_B_DQS_N
MEM_B_DQS1
MEM_70D MEM_DQS
MEM_B_DQS_P
MEM_B_DQS1
MEM_70D MEM_DQS
MEM_B_DQS_N
MEM_B_DQS2
MEM_70D MEM_DQS
MEM_B_DQS_P
MEM_B_DQS2
MEM_70D MEM_DQS
MEM_B_DQS_N
MEM_B_DQS3
MEM_70D MEM_DQS
MEM_B_DQS_P
MEM_B_DQS3
MEM_70D MEM_DQS
MEM_B_DQS_N
MEM_B_DQS4
MEM_70D MEM_DQS
MEM_B_DQS_P
MEM_B_DQS4 MEM_70D MEM_DQS
MEM_B_DQS_N
MEM_B_DQS5
MEM_70D MEM_DQS
MEM_B_DQS_P
MEM_B_DQS5
MEM_70D MEM_DQS
MEM_B_DQS_N
MEM_B_DQS6
MEM_70D MEM_DQS
MEM_B_DQS_P
MEM_B_DQS6
MEM_70D MEM_DQS
MEM_B_DQS_N
MEM_B_DQS7
MEM_70D MEM_DQS
MEM_B_DQS_P
MEM_B_DQS7
MEM_70D MEM_DQS
MEM_B_DQS_N
MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP_VDD
MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP_GND
15B5 28C5 28C7
15B5 28C5 28C7
15A5 28D5 28D7
15B5 28C5 28C7
15A5 28C5
15B5 15C5 28C5 28C7
15C5 28C5 28C7
15C5 28C5
15C5 28C7
15C5 28C7
15B7 28C2 28C4 28D2 28D4
15B7 28C2 28C4
15B7 15C7 28B2 28B4 28C2 28C4
15C7 28C2 28C4
15C7 28B5 28B7
15C7 28B5 28B7
15D7 28B5 28B7
15D7 28A5 28A7
15A7 28C4
15A7 28C2
15A7 28B4
15A7 28C2
15A7 28B5
15B7 28B7
15B7 28B5
15B7 28A7
15D5 28C2
15D5 28C2
15D5 28C4
15D5 28C4
15D5 28B2
15D5 28B2
15D5 28C4
15D5 28C4
15D5 28B7
15D5 28B7
15D5 28B5
15D5 28B5
15D5 28B7
15D5 28B7
15D5 28A5
15D5 28A5
15B1 29C5 29C7
15B1 29C5 29C7
15A1 29D5 29D7
15B1 29C5 29C7
15A1 29C5
15B1 15C1 29C5 29C7
15C1 29C5 29C7
15C1 29C5
15C1 29C7
15C1 29C7
15B3 29C2 29C4 29D2 29D4
15B3 29C2 29C4
15B3 15C3 29C2 29C4
15C3 29B2 29B4 29C2 29C4
Preliminary
15C3 29B5 29B7
15C3 29B5 29B7
15D3 29B5 29B7
15D3 29A5 29A7
15A3 29C4
15A3 29C2
15A3 29C2
15A3 29B4
15A3 29B5
15B3 29B7
15B3 29B5
15B3 29A7
15D1 29C2
15D1 29C2
15D1 29C4
15D1 29C4
15D1 29C4
15D1 29C4
15D1 29B2
15D1 29B2
15D1 29B7
15D1 29B7
15D1 29B5
15D1 29B5
15D1 29B7
15D1 29B7
15D1 29A5
15D1 29A5
16C6
16C6
APPLE INC.
Memory Constraints
SYNC_MASTER=T18_MLB SYNC_DATE=01/04/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
SHT OF
101
REV.
051-7537 A
109
D
C
B
A

D
C
B
A
PCI-Express
PHYSICAL_RULE_SET
PCIE_90D
CLK_PCIE_100D
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
PCIE
CLK_PCIE
MCP_PEX_COMP
PHYSICAL_RULE_SET
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
PHYSICAL_RULE_SET
8 7 6 5 4 3 2 1
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
*
*
*
=90_OHM_DIFF
=100_OHM_DIFF
8 MIL
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.4
Digital Video Signal Constraints
DP_100D
LVDS_100D
MCP_DV_COMP
DISPLAYPORT
LVDS
LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length.
DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.
DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.
Max length of LVDS/DisplayPort/TMDS traces: 12 inches.
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4.
SATA Interface Constraints
SATA_100D
SATA_100D_HDD
SATA_TERMP
*
*
*
*
*
*
*
*
*
=3X_DIELECTRIC
* 20 MIL
=100_OHM_DIFF
=100_OHM_DIFF
8 MIL
=90_OHM_DIFF
=100_OHM_DIFF
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1.
Y
=3x_DIELECTRIC
=3x_DIELECTRIC
=100_OHM_DIFF
=100_OHM_DIFF_HDD
?
=100_OHM_DIFF
20 MIL
?
?
=100_OHM_DIFF
?
?
=100_OHM_DIFF
=100_OHM_DIFF_HDD
?
=90_OHM_DIFF
=100_OHM_DIFF
PCIE
=100_OHM_DIFF
=100_OHM_DIFF
=90_OHM_DIFF
=100_OHM_DIFF =100_OHM_DIFF
=100_OHM_DIFF
TOP,BOTTOM
=100_OHM_DIFF
=STANDARD
=90_OHM_DIFF
=4X_DIELECTRIC
=100_OHM_DIFF
=STANDARD
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
SATA *
=4x_DIELECTRIC ?
SATA TOP,BOTTOM =3x_DIELECTRIC
?
20 MIL
DISPLAYPORT
LVDS
=100_OHM_DIFF
=100_OHM_DIFF_HDD
=100_OHM_DIFF
TOP,BOTTOM
TOP,BOTTOM
=100_OHM_DIFF
=100_OHM_DIFF_HDD
=100_OHM_DIFF
=4x_DIELECTRIC
=4x_DIELECTRIC
=100_OHM_DIFF
=100_OHM_DIFF_HDD
?
?
?
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
=90_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=STANDARD
=100_OHM_DIFF
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
=100_OHM_DIFF_HDD
ELECTRICAL_CONSTRAINT_SET PHYSICAL
SPACING
8 7 6 5 4 3 2 1
I183
I182
PCIE_FC_R2D
PCIE_FC_D2R
MCP_PE4_REFCLK
TMDS_IG_TXC
DP_ML
DP_ML
DP_AUX_CH
MCP_HDMI_RSET MCP_DV_COMP
MCP_HDMI_VPROBE MCP_DV_COMP
NET_TYPE
PCIE_90D
PCIE
PCIE_MINI_R2D_P
PCIE_90D
PCIE
PCIE_MINI_R2D_N
PCIE_MINI_R2D PCIE_90D
PCIE PCIE_MINI_R2D_C_P
PCIE_90D
PCIE
PCIE_MINI_R2D_C_N
PCIE_MINI_D2R
PCIE_90D
PCIE
PCIE_MINI_D2R_P
PCIE_90D
PCIE
PCIE_MINI_D2R_N
LVDS_IG_A_CLK LVDS_100D LVDS
LVDS_IG_A_CLK
LVDS_IG_A_DATA
LVDS_IG_A_DATA LVDS_100D
DP_ML
PCIE_90D
PCIE_90D
PCIE_90D
MCP_IFPAB_RSET MCP_DV_COMP
PCIE_90D PCIE
PCIE_90D PCIE
MCP_PE1_REFCLK CLK_PCIE_100D CLK_PCIE
MCP_PEX_CLK_COMP
CLK_PCIE_100D CLK_PCIE
CLK_PCIE_100D CLK_PCIE
DP_100D
TMDS_IG_TXC DP_100D
DISPLAYPORT
TMDS_IG_TXD DP_100D
DISPLAYPORT
TMDS_IG_TXD DP_100D
DISPLAYPORT
MCP_IFPAB_VPROBE
DP_100D
DISPLAYPORT DP_ML_P
DP_100D
DISPLAYPORT DP_ML_C_P
DP_100D DISPLAYPORT DP_ML_N
DP_100D DISPLAYPORT DP_ML_C_N
DP_100D DISPLAYPORT DP_IG_AUX_CH_P
DP_100D DISPLAYPORT DP_IG_AUX_CH_N
DP_100D
DISPLAYPORT DP_AUX_CH_SW_P
DP_100D DISPLAYPORT DP_AUX_CH_SW_N
DP_100D DISPLAYPORT DP_AUX_CH_C_P
DP_100D
DISPLAYPORT DP_AUX_CH_C_N
LVDS_100D LVDS
LVDS_100D LVDS
LVDS_100D LVDS
DISPLAYPORT
LVDS
DP_100D DISPLAYPORT
DP_100D DISPLAYPORT
PCIE_FC_R2D_P
PCIE_FC_R2D_N
PCIE_FC_R2D_C_P
PCIE_FC_R2D_C_N
PCIE_FC_D2R_P
PCIE_FC_D2R_N
PCIE_CLK100M_MINI_P
PCIE_CLK100M_MINI_N
PCIE_CLK100M_MINI_CONN_P
PCIE_CLK100M_MINI_CONN_N
PCIE_CLK100M_FC_P
PCIE_CLK100M_FC_N
TMDS_IG_TXC_P
TMDS_IG_TXC_N
TMDS_IG_TXD_P
TMDS_IG_TXD_N
MCP_HDMI_RSET
MCP_HDMI_VPROBE
LVDS_IG_A_CLK_P
LVDS_IG_A_CLK_F_P
LVDS_IG_A_CLK_N
LVDS_IG_A_CLK_F_N
LVDS_IG_A_DATA_P
LVDS_IG_A_DATA_N
DP_ML_CONN_P
DP_ML_CONN_N
MCP_IFPAB_RSET
MCP_IFPAB_VPROBE
SATA_HDD_R2D
SATA_100D_HDD SATA
SATA_HDD_R2D_C_P
SATA_100D_HDD SATA
SATA_HDD_R2D_C_N
SATA_100D_HDD SATA SATA_HDD_R2D_P
SATA_100D_HDD SATA SATA_HDD_R2D_N
SATA_100D_HDD SATA
SATA_HDD_R2D_UF_P
SATA_100D_HDD SATA
SATA_HDD_R2D_UF_N
SATA_HDD_D2R SATA_100D_HDD SATA SATA_HDD_D2R_P
SATA_100D_HDD SATA
SATA_HDD_D2R_N
SATA_100D_HDD SATA
SATA_HDD_D2R_C_P
SATA_100D_HDD SATA
SATA_HDD_D2R_C_N
SATA_100D_HDD SATA
SATA_HDD_D2R_UF_P
SATA_100D_HDD SATA
SATA_HDD_D2R_UF_N
SATA_ODD_R2D
SATA_100D
SATA
SATA_ODD_R2D_C_P
SATA_100D SATA
SATA_ODD_R2D_C_N
SATA_100D
SATA
SATA_ODD_R2D_P
SATA_100D
SATA
SATA_ODD_R2D_N
SATA_100D
SATA
SATA_ODD_R2D_UF_P
SATA_100D
SATA
SATA_ODD_R2D_UF_N
SATA_ODD_D2R SATA_100D SATA SATA_ODD_D2R_P
SATA_100D SATA SATA_ODD_D2R_N
SATA_100D SATA SATA_ODD_D2R_C_P
SATA_100D
SATA
SATA_ODD_D2R_C_N
SATA_100D SATA
SATA_ODD_D2R_UF_P
SATA_100D
SATA
SATA_ODD_D2R_UF_N
MCP_SATA_TERMP
PCIE_90D
PCIE
PCIE
PCIE
CLK_PCIE_100D CLK_PCIE
CLK_PCIE_100D CLK_PCIE
CLK_PCIE_100D
PCIE
LVDS_100D LVDS
CLK_PCIE
MCP_PEX_COMP
SATA_TERMP
MCP_PEX_CLK_COMP
MCP_SATA_TERMP
7D5 31C7
7D5 31C7
17B3 31C5
17B3 31C5
7D5 17B6 31C7
7D5 17B6 31C7
9B5 32C6
9B5 32C6
9B5 32B5
9B5 32B5
17C3 31C5
17C3 31C5
7D5 31C8
7D5 31C8
9B5 32C5
9B5 32C5
67D1 68C1 68C8
68C2 68C7
67D1 68B1 68C1 68C8
68B2 68C2 68C7
18B6 67C7
18B6 67B7
67C6
67C5
67C4 68C8
67D4 68B8
18A6 25C7
18A6 25C7
18B3 66B3
7C7 66B2
18B3 66B3
7C7 66B2
7C7 18B3 66C2
7C7 18B3 66C2
68C3 68C4 68C5
68B3 68C3 68C4 68C5
Preliminary
32C5
32C5
17A6
18A3 25C6
18A3 25C6
20D6 36A3
20D6 36A3
7C5 36A7
7C5 36A7
36A5
36A5
20D6 36A3
20D6 36A3
7C5 36A7
7C5 36A7
36A5
36A5
20D6 36C2
20D6 36C2
7B7 36B5
7B7 7C5 36B5
36C4
36C4
20D6 36B2
20D6 36B2
7B7 36B5
7B7 36B5
36B4
36B4
20A6
SYNC_MASTER=T18_MLB
APPLE INC.
MCP Constraints 1
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
051-7537
SHT OF
102
SYNC_DATE=01/04/2008
REV.
109
A
D
C
B
A

D
C
B
A
PHYSICAL_RULE_SET
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
PHYSICAL_RULE_SET
8 7 6 5 4 3 2 1
PCI Bus Constraints
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
PHYSICAL_RULE_SET
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
PCI_55S * =55_OHM_SE =55_OHM_SE
=55_OHM_SE =55_OHM_SE
=STANDARD
CLK_PCI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
PCI * =STANDARD
?
CLK_PCI * 8 MIL
?
LPC Bus Constraints
PHYSICAL_RULE_SET
PHYSICAL_RULE_SET
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TABLE_SPACING_RULE_HEAD
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.8.
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
USB 2.0 Interface Constraints
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.9.1.
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.10.1.
SMBus Interface Constraints
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
HD Audio Interface Constraints
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.11.1.
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
PHYSICAL_RULE_SET
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.12.1.
SIO Signal Constraints
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TABLE_SPACING_RULE_HEAD
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.13.
SPI Interface Constraints
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.14.
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
=STANDARD
LPC_55S *
=55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD
=STANDARD
CLK_LPC_55S *
LPC * 6 MIL
?
CLK_LPC
USB_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF
=90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF
SMB
*
=2x_DIELECTRIC ?
HDA * =2x_DIELECTRIC
?
MCP_HDA_COMP
* 8 MIL
* 8 MIL
CLK_SLOW *
8 MIL
?
SPI_55S * =55_OHM_SE =55_OHM_SE
=55_OHM_SE =55_OHM_SE
?
USB TOP,BOTTOM =4x_DIELECTRIC
?
HDA_55S * =55_OHM_SE =55_OHM_SE
=55_OHM_SE =55_OHM_SE
=STANDARD
=STANDARD
SPI *
8 MIL
?
=55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE
CLK_SLOW_55S *
=55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE
?
=STANDARD =STANDARD
MCP_USB_RBIAS *
=STANDARD 8 MIL 8 MIL =STANDARD
=STANDARD =STANDARD
USB
* =2x_DIELECTRIC
?
SMB_55S * =55_OHM_SE
=55_OHM_SE =55_OHM_SE =55_OHM_SE
=STANDARD =STANDARD
=STANDARD =STANDARD
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
ELECTRICAL_CONSTRAINT_SET PHYSICAL
8 7 6 5 4 3 2 1
MCP_USB_RBIAS
MCP_USB_RBIAS
NET_TYPE
SPACING
MCP_DEBUG PCI_55S
PCI
MCP_DEBUG
PCI_AD PCI_55S
PCI
PCI_AD
PCI_AD24 PCI_55S
PCI PCI_AD
PCI_AD
PCI_55S
PCI
PCI_AD
PCI_AD
PCI_55S
PCI
PCI_PAR
PCI_C_BE_L
PCI_55S
PCI
PCI_C_BE_L
PCI_CNTL PCI_55S
PCI PCI_IRDY_L
PCI_CNTL PCI_55S
PCI
PCI_DEVSEL_L
PCI_CNTL PCI_55S
PCI PCI_PERR_L
PCI_CNTL PCI_55S
PCI PCI_SERR_L
PCI_CNTL PCI_55S PCI
PCI_STOP_L
PCI_CNTL PCI_55S
PCI
PCI_TRDY_L
PCI_CNTL
PCI_55S
PCI
PCI_FRAME_L
PCI_REQ0_L PCI_55S
PCI PCI_REQ0_L
PCI_GNT0_L
PCI_55S
PCI
PCI_GNT0_L
PCI_REQ1_L
PCI_55S
PCI
PCI_REQ1_L
PCI_GNT1_L
PCI_55S
PCI
PCI_GNT1_L
PCI_INTW_L PCI_55S
PCI PCI_INTW_L
PCI_INTX_L
PCI_55S
PCI
PCI_INTX_L
PCI_INTY_L PCI_55S
PCI
PCI_INTY_L
PCI_INTZ_L PCI_55S
PCI
PCI_INTZ_L
MCP_PCI_CLK2 CLK_PCI_55S CLK_PCI
PCI_CLK33M_MCP_R
CLK_PCI_55S CLK_PCI PCI_CLK33M_MCP
LPC_AD LPC_55S
LPC LPC_AD
LPC_FRAME_L
LPC_55S LPC
LPC_FRAME_L
LPC_RESET_L LPC_55S
LPC LPC_RESET_L
MCP_LPC_CLK0 CLK_LPC_55S CLK_LPC LPC_CLK33M_SMC_R
CLK_LPC_55S CLK_LPC
LPC_CLK33M_SMC
CLK_LPC_55S CLK_LPC
LPC_CLK33M_LPCPLUS
USB_EXTA
USB_CAMERA
USB_BT
USB_TPAD
USB_IR
USB_EXTB
MCP_USB_RBIAS_GND
SMBUS_MCP_0_CLK
SMB_55S
SMB
SMBUS_MCP_0_CLK
SMBUS_MCP_0_DATA SMB_55S
SMB
SMBUS_MCP_0_DATA
SMBUS_MCP_1_CLK
SMB_55S SMB SMBUS_MCP_1_CLK
SMBUS_MCP_1_DATA
SMB_55S SMB SMBUS_MCP_1_DATA
HDA_BIT_CLK
HDA_55S HDA
HDA_BIT_CLK
HDA_55S HDA HDA_BIT_CLK_R
HDA_SYNC HDA_55S
HDA HDA_SYNC
HDA_55S HDA HDA_SYNC_R
HDA_RST_L HDA_55S HDA HDA_RST_R_L
HDA_55S HDA HDA_RST_L
HDA_SDIN0
HDA_55S HDA
HDA_SDIN0
HDA_55S
HDA
HDA_SDIN_CODEC
HDA_SDOUT HDA_55S
HDA HDA_SDOUT
HDA_55S HDA HDA_SDOUT_R
MCP_HDA_PULLDN_COMP
MCP_SUS_CLK
USB_90D USB
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
CLK_SLOW_55S
USB
USB
USB
USB
USB
MCP_HDA_COMP
CLK_SLOW
CLK_SLOW_55S CLK_SLOW
USB_EXTA_P
USB_EXTA_N
USB_EXTA_MUXED_P
USB_EXTA_MUXED_N
CONN_USB_EXTA_P
CONN_USB_EXTA_N
USB_90D
USB
USB_CAMERA_P
USB_90D
USB
USB_CAMERA_N
USB_90D
USB
USB_CAMERA_CONN_P
USB_90D USB USB_CAMERA_CONN_N
USB_90D
USB
USB_BT_P
USB_90D
USB
USB_BT_N
USB_90D USB
CONN_USB2_BT_P
USB_90D USB CONN_USB2_BT_N
USB_90D USB
USB_TPAD_P
USB_90D
USB
USB_TPAD_N
USB_90D USB USB_TPAD_R_P
USB_90D USB USB_TPAD_R_N
USB_90D
USB
USB_IR_P
USB_90D
USB
USB_IR_N
USB_90D USB
USB_EXTB_P
USB_90D USB USB_EXTB_N
USB_90D USB CONN_USB_EXTB_P
USB_90D
USB
CONN_USB_EXTB_N
MCP_HDA_PULLDN_COMP
PM_CLK32K_SUSCLK_R
PM_CLK32K_SUSCLK
SPI_CLK SPI_55S
SPI SPI_CLK_R
SPI_55S
SPI
SPI_CLK
SPI_55S
SPI
SPI_ALT_CLK
SPI_MOSI SPI_55S
SPI
SPI_MOSI_R
SPI_55S
SPI
SPI_MOSI
SPI_55S
SPI
SPI_ALT_MOSI
SPI_MISO SPI_55S
SPI SPI_MISO
SPI_55S SPI
SPI_MISO_R
SPI_55S
SPI
SPI_ALT_MISO
SPI_CS0
SPI_55S
SPI
SPI_CS0_R_L
SPI_55S
SPI
SPI_CS0_L
SPI_55S SPI SPI_CS1_R_L
SPI_55S SPI SPI_CS1_R_L_USE_MLB
13C3 19D7
19D2 19D7
19D2 19D7
19B3 39C8 41D3 41D5
Preliminary
19C5
19C5
19C3 39C8 41D5
19B3 26D4
19B3 26C4
26C1 39C8
26B1 41D3
20D3 37A8
20D3 37A8
37C4
37C4
37C3
37C3
20D3 31B5
20D3 31B5
7D5 31B7
7D5 31B7
20C3 31B5
20C3 31B5
7C5 31B7
7C5 31B7
20D3 47B8
20D3 47B8
47B7
47B7
20D3 38C7
20D3 38C7
20C3 37A4
20C3 37A4
37A3
37A3
20B4
13B6 21C3 42D8
13B6 21C3 42D8
21C3 42C8
21C3 42C8
21D2 51C7
21A7 21D4
21C2 51C7
21A7 21C4
21A7 21D4
21D2 51B7
21D7 51C7
21D2 51C7
21A7 21D4
21C7
21B3 26B4
26B1 39C5
21B3 41A5 41C8
41A1 50C5
41C5 41D3
21B3 41A5 41C7
41B1 50C4
41C5 41D5
21B3 41A5 41B7
50C4
41B5 41D5
21B3 41B7
41B2
SYNC_MASTER=T18_MLB SYNC_DATE=12/14/2007
APPLE INC.
MCP Constraints 2
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
SHT OF
103
REV.
051-7537 A
109
D
C
B
A

D
C
B
A
PHYSICAL_RULE_SET
PHYSICAL_RULE_SET
8 7 6 5 4 3 2 1
MCP RGMII (Ethernet) Constraints
MCP_MII_COMP
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ENET_MII_55S *
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD =STANDARD
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
MCP_BUF0_CLK
ENET_MII *
12 MIL
TABLE_SPACING_RULE_ITEM
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4
88E1116R (Ethernet PHY) Constraints
ENET_MDI
*
* =3:1_SPACING
?
*
=STANDARD
7.5 MIL
25 MIL ?
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
SOURCE: MCP73 Interface DG (DG-02974-001_v01), Section 2.7.4
?
7.5 MIL =STANDARD
=STANDARD =STANDARD
ENET_MDI_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
=100_OHM_DIFF
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
ELECTRICAL_CONSTRAINT_SET PHYSICAL
8 7 6 5 4 3 2 1
MCP_MII_COMP
MCP_MII_COMP
ENET_RXCLK
ENET_RXD_STRAP
MCP_MII_COMP
NET_TYPE
SPACING
MCP_CLK25M_BUF0 ENET_MII_55S MCP_BUF0_CLK
ENET_MII_55S
MCP_BUF0_CLK
ENET_MII_55S ENET_MII
ENET_MII_55S ENET_MII
ENET_MII_55S ENET_MII
MCP_MII_COMP_VDD
MCP_MII_COMP_GND
MCP_CLK25M_BUF0_R
RTL8211_CLK25M_CKXTAL1
ENET_INTR_L ENET_MII_55S ENET_MII ENET_INTR_L
ENET_MDIO
ENET_MII_55S ENET_MII ENET_MDIO
ENET_MDC ENET_MII_55S ENET_MII ENET_MDC
ENET_PWRDWN_L ENET_MII_55S ENET_MII ENET_PWRDWN_L
ENET_RXD
ENET_RXD
MCP_MII_COMP
ENET_MII_55S
ENET_MII
ENET_MII_55S ENET_MII
ENET_CLK125M_RXCLK_R
ENET_CLK125M_RXCLK
ENET_RXD_R
ENET_RXD
ENET_RXD
ENET_RX_CTRL
ENET_RXCTL_R
ENET_MII_55S ENET_MII ENET_CLK125M_TXCLK_R
ENET_TXCLK ENET_MII_55S ENET_MII ENET_CLK125M_TXCLK
ENET_TXD0 ENET_MII_55S ENET_MII ENET_TXD
ENET_TXD ENET_MII_55S ENET_MII ENET_TXD
ENET_TXD
ENET_MII_55S ENET_MII ENET_TX_CTRL
ENET_MDI
ENET_MII_55S ENET_MII
ENET_MII_55S
ENET_MII
ENET_MII_55S ENET_MII
ENET_RESET_L
ENET_MDI_100D ENET_MDI ENET_MDI_P
ENET_MDI_100D ENET_MDI ENET_MDI_N
ENET_MDI_100D ENET_MDI ENET_MDI_TRAN_P
ENET_MDI_100D ENET_MDI ENET_MDI_TRAN_N
Preliminary
18C6
18C6
18C3 34A5
33B6 34A3
18C3 33B6
18C3 33B6
33C4
18D6 33C1
33B4 33C4
18D6 33C1
18D6 33B1 33C1
18D6 33B1
33B4
33C6
18D3 33C8
18D3 33C6
18D3 33B6 33C6
18C3 33B6
18C3 33B7
33B3 35B7 35C7
33B3 35B7 35C7
35B4 35C4 35C5
35B4 35C4 35C5
SYNC_MASTER=T18_MLB
APPLE INC.
Ethernet Constraints
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
051-7537
SYNC_DATE=03/19/2008
SHT OF
104 109
REV.
A
D
C
B
A

D
C
B
A
PHYSICAL_RULE_SET
1TO1_DIFFPAIR
8 7 6 5 4 3 2 1
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
* =STANDARD
=STANDARD
=STANDARD =STANDARD 0.1 MM 0.1 MM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
SMC SMBus Net Properties
ELECTRICAL_CONSTRAINT_SET
SMBus Charger Net Properties
ELECTRICAL_CONSTRAINT_SET
8 7 6 5 4 3 2 1
PHYSICAL
NET_TYPE
SMBUS_SMC_A_S3_SCL SMB_55S
SMB
SMBUS_SMC_A_S3_SDA SMB_55S
SMB
SMBUS_SMC_B_S0_SCL
SMBUS_SMC_B_S0_SDA
SMBUS_SMC_0_S0_SCL
SMB_55S
SMB_55S
SMB_55S
NET_TYPE
SMB
SMB
SMB
SMBUS_SMC_0_S0_SDA SMB_55S
SMB
SMBUS_SMC_BSA_SCL
SMB_55S
SMB
SMBUS_SMC_BSA_SDA SMB_55S
SMB
SMBUS_SMC_MGMT_SCL
SMBUS_SMC_MGMT_SDA
CHGR_CSI
CHGR_CSO
SMB_55S
SMB_55S
SMB
SMB
SPACING
PHYSICAL SPACING
1TO1_DIFFPAIR
1TO1_DIFFPAIR
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_B_S0_SCL
SMBUS_SMC_B_S0_SDA
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
SMBUS_SMC_MGMT_SCL
SMBUS_SMC_MGMT_SDA
CHGR_CSI_P
CHGR_CSI_N
CHGR_CSO_P
CHGR_CSO_N
Preliminary
1TO1_DIFFPAIR
1TO1_DIFFPAIR
7B5 7D5 42D2
7B5 7C5 42D2
42C2
42C2
42D5
42D5
7A7 42C5
42C5
42B5
42B5
APPLE INC.
SMC Constraints
SYNC_MASTER=T18_MLB SYNC_DATE=01/04/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
SHT OF
106
REV.
051-7537 A
109
D
C
B
A

D
C
B
A
PHYSICAL_RULE_SET
8 7 6 5 4 3 2 1
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
DIFFPAIR * =STANDARD
=STANDARD
=STANDARD =STANDARD 0.1 MM 0.1 MM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
M97 SENSOR NET PROPERTIES
8 7 6 5 4 3 2 1
NET_TYPE
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
CHGR_CSO_R_P
CHGR_CSO_R_N
CPUTHMSNS_D2_P
CPUTHMSNS_D2_N
CPU_THERMD_P
CPU_THERMD_N
ISNS_CPUVTT_P
ISNS_CPUVTT_N
ISNS_P1V5S0MCP_P
ISNS_P1V5S0MCP_N
ISNS_PVCORES0MCP_P
ISNS_PVCORES0MCP_N
MCPTHMSNS_D2_P
MCPTHMSNS_D2_N
MCP_THMDIODE_P
MCP_THMDIODE_N
Preliminary
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
44A8 57B3
44A8 57B3
45C5
45C5
10C6 45D5
10C6 45D5
44B7
44B7
44C7
44C7
44D8
44D8 61C4
7C7 45B5
7C7 45B5
21C3 45C5
21C3 45B5
SYNC_MASTER=M97_MLB
APPLE INC.
M97 SPECIAL CONSTRAINTS
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
SCALE
DRAWING NUMBER
NONE
051-7537
SHT OF
107 109
REV.
A
D
C
B
A

D
C
B
A
PHYSICAL_RULE_SET
PHYSICAL_RULE_SET
PHYSICAL_RULE_SET
PHYSICAL_RULE_SET
PHYSICAL_RULE_SET
PHYSICAL_RULE_SET
PHYSICAL_RULE_SET
PHYSICAL_RULE_SET
PHYSICAL_RULE_SET
8 7 6 5 4 3 2 1
M97 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS
PHYSICAL_RULE_SET
50_OHM_SE
PHYSICAL_RULE_SET
BOARD LAYERS BOARD AREAS
BOARD UNITS
(MIL or MM)
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
70_OHM_DIFF * N
=STANDARD =STANDARD =STANDARD
=STANDARD
=STANDARD
70_OHM_DIFF ISL3,ISL4,ISL9,ISL10 Y
0.151 MM
0.100 MM
70_OHM_DIFF TOP,BOTTOM Y
0.185 MM
0.100 MM
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
90_OHM_DIFF *
N =STANDARD =STANDARD =STANDARD
=STANDARD
=STANDARD
90_OHM_DIFF ISL3,ISL4,ISL9,ISL10
90_OHM_DIFF TOP,BOTTOM
Y
100_OHM_DIFF
100_OHM_DIFF
100_OHM_DIFF
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
* N =STANDARD
=STANDARD
=STANDARD
=STANDARD
ISL3,ISL4,ISL9,ISL10 Y 0.075 MM
0.075 MM
0.244 MM 0.244 MM
TOP,BOTTOM
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
100_OHM_DIFF_HDD * N =STANDARD
Y 0.091 MM 0.091 MM
0.230 MM
0.230 MM
=STANDARD
=STANDARD
=STANDARD =STANDARD
=STANDARD
100_OHM_DIFF_HDD TOP,BOTTOM Y
0.095 MM 0.095 MM 0.400 MM
0.400 MM
110_OHM_DIFF
110_OHM_DIFF
1:1_DIFFPAIR
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM NO_TYPE,BGA_P1MM
MM
DEFAULT * Y =50_OHM_SE
0.100MM
30 MM
STANDARD
55_OHM_SE
*
Y 0.076 MM 0.076 MM =STANDARD
=STANDARD
=STANDARD
27P4_OHM_SE *
Y
0.222 MM 0.222 MM
=STANDARD
=STANDARD
=STANDARD
110_OHM_DIFF
* Y =DEFAULT =DEFAULT
12.7 MM =DEFAULT
=DEFAULT
TOP,BOTTOM Y
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ISL3,ISL4,ISL9,ISL10 Y
TOP,BOTTOM
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
*
Y
Y
0.090 MM
0.095 MM
0.090 MM
55_OHM_SE *
Y 0.076 MM
0.076 MM
=STANDARD
=STANDARD =STANDARD
50_OHM_SE TOP,BOTTOM
Y 0.115 MM
0.115 MM
40_OHM_SE TOP,BOTTOM Y
0.165 MM
40_OHM_SE * Y
0.126 MM 0.100 MM
=STANDARD
=STANDARD
=STANDARD
27P4_OHM_SE TOP,BOTTOM
Y
0.310 MM
0.100 MM
0.310 MM
0.095 MM
=STANDARD 0.224 MM
0.224 MM
0.200 MM 0.200 MM
0.234 MM
0.234 MM
0.112 MM 0.112 MM 0.220 MM
0.220 MM
100_OHM_DIFF_HDD ISL3,ISL4,ISL9,ISL10 Y
0.083 MM
0.083 MM
0.400 MM 0.400 MM
* N =STANDARD =STANDARD
=STANDARD
0.075 MM 0.075 MM 0.330 MM
0.330 MM
0.077 MM 0.077 MM 0.330 MM
0.330 MM
Y =STANDARD
=STANDARD =STANDARD 0.1 MM 0.1 MM
0 MM
=STANDARD
0 MM
=STANDARD
ALLEGRO
VERSION
15.5.1
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_BOARD_INFO
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
DEFAULT *
0.1 MM
?
STANDARD
BGA_P1MM
=DEFAULT ?
* =DEFAULT
?
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
NET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
AREA_TYPE SPACING_RULE_SET
8 7 6 5 4 3 2 1
*
BGA_P2MM *
=DEFAULT
BGA_P3MM *
=DEFAULT
?
1.5:1_SPACING
2:1_SPACING
*
0.15 MM
* 0.2 MM
2.5:1_SPACING *
0.25 MM
?
3:1_SPACING *
0.3 MM
?
4:1_SPACING * 0.4 MM
?
2X_DIELECTRIC TOP,BOTTOM 0.140 MM
?
3X_DIELECTRIC TOP,BOTTOM
0.210 MM
?
4X_DIELECTRIC TOP,BOTTOM 0.280 MM
?
5X_DIELECTRIC TOP,BOTTOM 0.350 MM
?
2X_DIELECTRIC
3X_DIELECTRIC
4X_DIELECTRIC
5X_DIELECTRIC
*
0.126 MM ?
* 0.189 MM
?
* 0.252 MM
?
* 0.315 MM
?
?
?
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
*
*
BGA_P1MM
BGA_P1MM
MEM_CLK *
BGA_P1MM BGA_P2MM
CLK_FSB * BGA_P1MM
BGA_P2MM
CLK_LPC
* BGA_P1MM
BGA_P2MM
CLK_PCI * BGA_P1MM
BGA_P2MM
CLK_PCIE * BGA_P1MM BGA_P2MM
CLK_SLOW *
BGA_P1MM
BGA_P2MM
FSB_DSTB FSB_DSTB BGA_P1MM
BGA_P3MM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
NET_PHYSICAL_TYPE
Preliminary
APPLE INC.
AREA_TYPE
SCALE
TABLE_PHYSICAL_ASSIGNMENT_HEAD
PHYSICAL_RULE_SET
MEM_40S BGA_P1MM
STANDARD
MEM_40S_VDD BGA_P1MM STANDARD
SYNC_MASTER=M97_MLB
NONE
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
M97 RULE DEFINITIONS
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
DRAWING NUMBER
SHT OF
109
REV.
051-7537 A
109
D
C
B
A