Chuan Seng Tan, M.I.T. - Sematech
Chuan Seng Tan, M.I.T. - Sematech
Chuan Seng Tan, M.I.T. - Sematech
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TRC: Oct 25-27, 2004<br />
Multi-layered Three-Dimensional<br />
Integration Enabled by Wafer<br />
Bonding<br />
C.S. <strong>Tan</strong>*, A. Fan, K.-N. Chen, and R. Reif<br />
Microsystems Technology Laboratories<br />
MIT<br />
Cambridge, MA<br />
*tancs@mtl.mit.edu
Outline<br />
• Background and Motivation<br />
• 3-D Research at MIT<br />
- Process flow: Silicon layer transfer<br />
- Cu and oxide wafer bonding<br />
• Technical challenges<br />
Slide 2
Outline<br />
• Background and Motivation<br />
• 3-D Research at MIT<br />
- Process flow: Silicon layer transfer<br />
- Cu and oxide wafer bonding<br />
• Technical challenges<br />
Slide 3
Three-dimensional Integrated Circuits<br />
(3-D ICs)<br />
A vertical stack consists of multiple device and<br />
interconnect layers that are connected together by<br />
interlayer vertical vias.<br />
Layer 4<br />
Layer 3<br />
Layer 2<br />
Layer 1<br />
Interlayer vertical via<br />
Device/Interconnect layer<br />
Slide 4
What can 3-D offer ?<br />
• Narrower interconnect length<br />
distribution<br />
shorter semi-global and global<br />
interconnects<br />
RC delay decreases<br />
power consumption decreases<br />
• Improved chip form factor<br />
more devices can be packed for a<br />
given chip area<br />
volumetric density ?<br />
Number of Interconnects<br />
Wire-length<br />
2-D IC<br />
3-D IC<br />
Slide 5
What can 3-D offer ? (continued)<br />
• Heterogeneous Integration<br />
3-D System-on-a-Chip: mixed-signal/mixedtechnology<br />
based applications<br />
parallel fabrication and subsequent stacking<br />
process optimization for each<br />
device/interconnect layers<br />
Performance, Form Factor, Integration<br />
Slide 6
Outline<br />
• Background and Motivation<br />
• 3-D Research at MIT<br />
- Process flow: Silicon layer transfer<br />
- Cu and oxide wafer bonding<br />
• Technical challenges<br />
Slide 7
Test Vehicle: 3-D 3 D Ring Oscillator<br />
p-MOS<br />
n-MOS<br />
Cu<br />
Cross Section<br />
3-D inverter Layout<br />
• 3-D functionality will be verified<br />
using pMOS and nMOS devices on separate<br />
active layers, forming a ring oscillator<br />
Layout<br />
(A. Fan)<br />
Slide 8
MIT 3-D Process Flow - Summary<br />
Sacrificial<br />
Bond<br />
Permanent<br />
Bond<br />
Slide 9
MIT 3-D Process Flow – Summary<br />
1. Permanent bonding achieved by<br />
direct Cu-to-Cu wafer bonding.<br />
2. Sacrificial bonding achieved by<br />
e.g., oxide-to-oxide wafer<br />
bonding.<br />
The MIT 3-D process flow is based on a thin film layer<br />
transfer method with the above two bonding steps.<br />
Slide 10
H 2 + implant peak<br />
Proposed thin-film transfer method<br />
Handle Wafer<br />
PECVD Oxide<br />
Device/Interconnect Layer 2 (SOI)<br />
BOX<br />
Handle wafer is bonded to SOI wafer: CVD oxide<br />
to thermal oxide bonding.<br />
Slide 11
Proposed thin-film transfer method<br />
Handle Wafer<br />
PECVD Oxide<br />
Device/Interconnect Layer 2 (SOI)<br />
BOX<br />
Handle wafer is bonded to SOI wafer: CVD oxide<br />
to thermal oxide bonding.<br />
Slide 12
Proposed thin-film transfer method<br />
Handle Wafer<br />
PECVD Oxide<br />
Device/Interconnect Layer 2 (SOI)<br />
BOX<br />
SOI wafer is thinned back (mechanical grinding<br />
and TMAH etch) and etch stop on BOX.<br />
Slide 13
Proposed thin-film transfer method<br />
Handle Wafer<br />
PECVD Oxide<br />
Device/Interconnect Layer 2 (SOI)<br />
BOX<br />
Cu<br />
Device/Interconnect Layer 1<br />
Thinned SOI wafer is bonded to substrate wafer<br />
using Cu-Cu direct bonding.<br />
Slide 14
Proposed thin-film transfer method<br />
PECVD Oxide<br />
Device/Interconnect Layer 2 (SOI)<br />
BOX<br />
Cu<br />
Device/Interconnect Layer 1<br />
Thin film transfer by Hydrogen induced<br />
wafer splitting.<br />
Slide 15
Proposed thin-film transfer method<br />
PECVD Oxide<br />
Device/Interconnect Layer 2 (SOI)<br />
BOX<br />
Cu<br />
Device/Interconnect Layer 1<br />
Strip the remaining Si with short TMAH dip.<br />
Slide 16
H 2 + implant<br />
peak<br />
Proposed thin-film transfer method - Summary<br />
(C.S. <strong>Tan</strong>)<br />
Slide 17
This approach offers …<br />
• Via first approach, hence relax the AR<br />
requirement of vertical vias: Vertical vias are<br />
formed on both wafers and bonded (compared<br />
with via last approach)<br />
• Minimum damage to the stack: The 3-D stack<br />
does not see the SOI thinning step. This also<br />
explains the choice of back-to-face stacking<br />
Slide 18
The choice of metal bonding …<br />
• Better thermal management – Bonding<br />
interface also acts as heat conduit<br />
• Bonding interface acts as another metal layer<br />
(e.g., Ground Shield)<br />
• Noise and cross talk suppression ? (Grounded<br />
bonding interface)<br />
Slide 19
Outline<br />
• Background and Motivation<br />
• 3-D Research at MIT<br />
- Process flow: Silicon layer transfer<br />
- Cu and oxide wafer bonding<br />
• Technical challenges<br />
Slide 20
Characterization of Cu-Cu Bonding<br />
Interface<br />
• Bonding strength determination, process yield<br />
improvement<br />
• Morphologies of bonding interface<br />
Cu-Cu Cu Cu Bonding Experiment<br />
Ta/Cu = 50nm/300nm<br />
N 2 purge prior to bonding<br />
Bonding Conditions = 400 o C / 30 min<br />
Contact Pressure = 4000 mBar<br />
Chamber Ambient = 1x10 -3 Torr<br />
Post-Bonding Anneal = 400 o C / 30 min<br />
Anneal Ambient = atm pressure with N 2 purge<br />
Slide 21
Evolution of Morphologies During Bonding<br />
Before bonding 30 min bonding 30 min bonding + 30 min N 2 anneal<br />
• (111) orientation<br />
• Clear interface<br />
• (220) orientation<br />
• Grain structure<br />
• Grain size saturates after 30 min of<br />
annealing<br />
• Stable grain structures and bonded<br />
layers are observed after further<br />
annealing<br />
(Chen et al., APL)<br />
Slide 22
Morphology and strength map under different<br />
bonding temperatures and annealing conditions.<br />
Bonding /Annealing<br />
Temperature<br />
Bonding /Annealing Duration<br />
(Chen et al, ECS Letters)<br />
Slide 23
Handle Wafer<br />
CVD Oxide<br />
SOI<br />
BOX<br />
Oxide Wafer Bonding<br />
5000Å Thermal oxide –<br />
Protection against<br />
KOH/TMAH<br />
1 µm CVD OX – ILD, low<br />
temperature process,<br />
high deposition rate.<br />
Schematic shows the bonding of thermal oxide<br />
on a handle wafer to CVD oxide on an SOI<br />
structure.<br />
Slide 24
Can CVD Oxide bond to thermal oxide ?<br />
We need …<br />
• pre-bonding densification to prevent<br />
out-gassing from CVD oxide during<br />
bonding and annealing.<br />
• CMP to smoothen the CVD oxide<br />
surface.<br />
• post-bonding annealing to enhance<br />
the bond<br />
Slide 25
Why do we need pre-bonding densification ?<br />
Wafer pair without densification on PECVD oxide<br />
Wafer pair with densification on PECVD oxide<br />
[350 o C/16h pre-bonding anneal]<br />
300 o C/6 h<br />
post-bonding anneal<br />
300 o C/6 h<br />
post-bonding anneal<br />
Voids<br />
[<strong>Tan</strong> et al, APL, 82(16) 2003]<br />
Slide 26
AFM surface roughness data<br />
Oxide<br />
LTO<br />
PE-TEOS<br />
PE-Silane<br />
As deposited<br />
Densified and CMP<br />
As deposited<br />
Densified and CMP<br />
As deposited<br />
Densified and CMP<br />
Bare Silicon: 0.143 nm<br />
Surface preparation<br />
500 nm SiO2/Si: 0.273 nm<br />
RMS Roughness (nm)<br />
13.35<br />
Mean and root-mean-square (RMS) roughness of wafers with different surfaces<br />
preparations estimated from AFM. RMS roughness of
AFM scans<br />
(a)as-deposited PE-Silane oxide.<br />
(b) densified (350 o C/16h) and<br />
polished PE-Silane oxide.<br />
[<strong>Tan</strong> et al, APL, 82(16) 2003]<br />
Slide 1
Wafer Bow (mm)<br />
25<br />
20<br />
15<br />
10<br />
5<br />
0<br />
Wafer Bow<br />
500nm SiO 2 /Si<br />
LTO<br />
PE-Silane<br />
PE-TEOS<br />
Silicon<br />
0 20 40 60 80 100 120 140<br />
Edge-to-edge Wafer Length (mm)<br />
Wafer Bow < 25 um for successful bonding of 6” wafers.<br />
[<strong>Tan</strong> et al, ECS Letters, accepted]<br />
Slide 1
The importance of post-bonding annealing<br />
Bond Strength (mJ/m 2 )<br />
1000<br />
800<br />
600<br />
400<br />
200<br />
0<br />
0 2 4 6 8 10<br />
Post-bond annealing time (h)<br />
LTO<br />
PE-Silane<br />
PE-TEOS<br />
Bonding strength of the bonded wafer pairs with<br />
different CVD oxides at 300 o C.<br />
[<strong>Tan</strong> et al, ECS Letters, accepted]<br />
Slide 1
Bonding Strength (mJ/m 2 )<br />
1000<br />
800<br />
600<br />
400<br />
200<br />
Post-bonding anneal duration<br />
0<br />
0 2 4 6 8 10<br />
Post-bond annealing time (h)<br />
300 o C<br />
250 o C<br />
200 o C<br />
Bonding strength does not increase significantly beyond 2-3<br />
hours of post-bonding annealing. (Data from PE-TEOS oxide)<br />
[<strong>Tan</strong> et al, ECS Letters, accepted]<br />
Slide 2
Outline<br />
• Background and Motivation<br />
• 3-D Research at MIT<br />
- Process flow: Silicon layer transfer<br />
- Cu and oxide wafer bonding<br />
• Technical challenges<br />
Slide 3
Bonding Temperature = 400 o C<br />
σ<br />
Normal Stress (MPa)<br />
1200<br />
1000<br />
800<br />
600<br />
400<br />
200<br />
0<br />
-200<br />
(1) D.E. Riemer, IEEE Trans. Components, Hybrids, and<br />
Manufacturing Technology, 13(1), pp. 194-199, 1990.<br />
(2) E. Suhir, J. Appl. Mechanics, 55, pp. 143-148, 1988.<br />
(3) FEMLAB, Comsol, Inc.<br />
Thermal Stress - Thin Films Normal Stress<br />
FEMLAB<br />
Riemer<br />
Suhir<br />
Si substrate<br />
LOCOS<br />
BOX<br />
SOI<br />
LOCOS<br />
97 98 99 100 101 102 103<br />
Cu<br />
Vertical Distance (µm)<br />
[<strong>Tan</strong> et al, submitted to IRPS 2005]<br />
Slide 4
Interfacial Stress (MPa)<br />
Thermal Stress - Thin Films Interfacial Stresses<br />
0<br />
-50<br />
-100<br />
-150<br />
-200<br />
Shear 2-3<br />
Shear 3-4<br />
Peel 2-3<br />
Peel 3-4<br />
4960 4970 4980 4990 5000<br />
Distance (µm)<br />
[<strong>Tan</strong>, unpublished]<br />
Slide 5
Baseline oxide-oxide bond, top and bottom-heated<br />
• Upon doubly-aligned heating, the temperature gradient becomes<br />
even larger within the ILD<br />
• Maximum temperature is at 312 o C<br />
Heating elements<br />
2000 A SOI<br />
2000 A BOX<br />
2 µm ILD<br />
Bulk Si<br />
[Fan, unpublished]<br />
Slide 6
Basic Improvement with Cu-Cu bonding<br />
• Maximum temperature is at 178 o C, a 43% decrease from 312 o C<br />
Heating elements<br />
2000 A SOI<br />
2000 A BOX<br />
6000 A Cu<br />
2 µm ILD<br />
Bulk Si<br />
[Fan, unpublished]<br />
Slide 7
Doubly-SOI, doubly-aligned heated structure<br />
• Maximum temperature is at 197 o C, a +10% increase from 178 o C<br />
just due to the higher thermal resistance of the lower SOI layer<br />
Heating elements<br />
2000 A SOI<br />
2000 A BOX<br />
6000 A Cu<br />
2 µm ILD<br />
2000 A SOI<br />
2000 A BOX<br />
BulK Si<br />
[Fan, unpublished]<br />
Slide 8
With Cu plane and two Cu vias<br />
• Maximum temperature is at 160 o C, a 19% decrease from 197 o C<br />
just due to two Cu vias<br />
450<br />
Heating elements<br />
2000 A SOI<br />
2000 A BOX<br />
6000 A Cu<br />
2 µm ILD<br />
2000 A SOI<br />
2000 A BOX<br />
BulK Si<br />
2 Cu vias:<br />
[Fan, unpublished]<br />
Slide 9
Thermal Management - Summary<br />
• Preliminary FEM simulations show that,<br />
- The addition of Cu planes in between active device layers<br />
can offer a ~40% reduction in the maximum steady-state<br />
temperature a two-layered 3-D structure<br />
- The addition of Cu vias can offer an addition ~15-20 %<br />
reduction in the system's maximum temperature<br />
- The convergence and divergence of heat flux lines can be<br />
tailored using either Cu planes or vias<br />
• Work in progress<br />
- Explore different layout designs in order to optimize the<br />
performance of Cu plane / via heat extractors<br />
- Verification of simulated results with a fabricated 3-D device<br />
Slide 10
Evaluation of relative merits and process flows for<br />
wafer-to-wafer, chip-to-wafer, and chip-to-chip 3-D<br />
technologies<br />
Throughput<br />
Yield<br />
Bond Quality<br />
Availability of Tool<br />
Post-bonding<br />
processing<br />
Wafer-to-Wafer<br />
High<br />
Low<br />
Large area, prone<br />
to defect<br />
Production tools<br />
available<br />
Possible<br />
Chip-to-Wafer<br />
Low<br />
High<br />
Different areas,<br />
needs careful<br />
handling<br />
Not readily<br />
available<br />
Extremely<br />
challenging<br />
Chip-to-Chip<br />
Low<br />
High<br />
Smaller area, less<br />
prone to defects<br />
Not readily<br />
available<br />
Possible but more<br />
challenging<br />
[Fan and <strong>Tan</strong>]<br />
Slide 11
Technical challenges needing further research<br />
• Thermal Stress – thin films stresses due to<br />
CTE mismatch.<br />
• Thermal management – increased power<br />
density and local heating.<br />
• Maintaining device integrity –need to<br />
preserve electrical integrity of devices and<br />
circuits as a result of additional steps.<br />
• Yield – Cumulative yield for wafer-to-wafer<br />
bonding.<br />
• Wafer bonding – bonding mechanism, bonding<br />
parameters (temperature, pressure, wafer bow,<br />
etc)<br />
• Noise and crosstalk – coupling between<br />
device layers.<br />
• Orientation – face-to-face or back-to-face<br />
bonding ?<br />
Slide 12
Acknowledgement<br />
1) DARPA<br />
2) MARCO – Interconnect Focus Center<br />
3) SRC<br />
4) Applied Materials – Graduate Fellowship<br />
(C.S. <strong>Tan</strong>)<br />
Slide 13