Chuan Seng Tan, M.I.T. - Sematech

TRC: Oct 25-27, 2004
Multi-layered Three-Dimensional
Integration Enabled by Wafer
Bonding
C.S. Tan*, A. Fan, K.-N. Chen, and R. Reif
Microsystems Technology Laboratories
MIT
Cambridge, MA
*tancs@mtl.mit.edu

Outline
• Background and Motivation
• 3-D Research at MIT
- Process flow: Silicon layer transfer
- Cu and oxide wafer bonding
• Technical challenges
Slide 2

Outline
• Background and Motivation
• 3-D Research at MIT
- Process flow: Silicon layer transfer
- Cu and oxide wafer bonding
• Technical challenges
Slide 3

Three-dimensional Integrated Circuits
(3-D ICs)
A vertical stack consists of multiple device and
interconnect layers that are connected together by
interlayer vertical vias.
Layer 4
Layer 3
Layer 2
Layer 1
Interlayer vertical via
Device/Interconnect layer
Slide 4

What can 3-D offer ?
• Narrower interconnect length
distribution
shorter semi-global and global
interconnects
RC delay decreases
power consumption decreases
• Improved chip form factor
more devices can be packed for a
given chip area
volumetric density ?
Number of Interconnects
Wire-length
2-D IC
3-D IC
Slide 5

What can 3-D offer ? (continued)
• Heterogeneous Integration
3-D System-on-a-Chip: mixed-signal/mixedtechnology
based applications
parallel fabrication and subsequent stacking
process optimization for each
device/interconnect layers
Performance, Form Factor, Integration
Slide 6

Outline
• Background and Motivation
• 3-D Research at MIT
- Process flow: Silicon layer transfer
- Cu and oxide wafer bonding
• Technical challenges
Slide 7

Test Vehicle: 3-D 3 D Ring Oscillator
p-MOS
n-MOS
Cu
Cross Section
3-D inverter Layout
• 3-D functionality will be verified
using pMOS and nMOS devices on separate
active layers, forming a ring oscillator
Layout
(A. Fan)
Slide 8

MIT 3-D Process Flow - Summary
Sacrificial
Bond
Permanent
Bond
Slide 9

MIT 3-D Process Flow – Summary
1. Permanent bonding achieved by
direct Cu-to-Cu wafer bonding.
2. Sacrificial bonding achieved by
e.g., oxide-to-oxide wafer
bonding.
The MIT 3-D process flow is based on a thin film layer
transfer method with the above two bonding steps.
Slide 10

H 2 + implant peak
Proposed thin-film transfer method
Handle Wafer
PECVD Oxide
Device/Interconnect Layer 2 (SOI)
BOX
Handle wafer is bonded to SOI wafer: CVD oxide
to thermal oxide bonding.
Slide 11

Proposed thin-film transfer method
Handle Wafer
PECVD Oxide
Device/Interconnect Layer 2 (SOI)
BOX
Handle wafer is bonded to SOI wafer: CVD oxide
to thermal oxide bonding.
Slide 12

Proposed thin-film transfer method
Handle Wafer
PECVD Oxide
Device/Interconnect Layer 2 (SOI)
BOX
SOI wafer is thinned back (mechanical grinding
and TMAH etch) and etch stop on BOX.
Slide 13

Proposed thin-film transfer method
Handle Wafer
PECVD Oxide
Device/Interconnect Layer 2 (SOI)
BOX
Cu
Device/Interconnect Layer 1
Thinned SOI wafer is bonded to substrate wafer
using Cu-Cu direct bonding.
Slide 14

Proposed thin-film transfer method
PECVD Oxide
Device/Interconnect Layer 2 (SOI)
BOX
Cu
Device/Interconnect Layer 1
Thin film transfer by Hydrogen induced
wafer splitting.
Slide 15

Proposed thin-film transfer method
PECVD Oxide
Device/Interconnect Layer 2 (SOI)
BOX
Cu
Device/Interconnect Layer 1
Strip the remaining Si with short TMAH dip.
Slide 16

H 2 + implant
peak
Proposed thin-film transfer method - Summary
(C.S. Tan)
Slide 17

This approach offers …
• Via first approach, hence relax the AR
requirement of vertical vias: Vertical vias are
formed on both wafers and bonded (compared
with via last approach)
• Minimum damage to the stack: The 3-D stack
does not see the SOI thinning step. This also
explains the choice of back-to-face stacking
Slide 18

The choice of metal bonding …
• Better thermal management – Bonding
interface also acts as heat conduit
• Bonding interface acts as another metal layer
(e.g., Ground Shield)
• Noise and cross talk suppression ? (Grounded
bonding interface)
Slide 19

Outline
• Background and Motivation
• 3-D Research at MIT
- Process flow: Silicon layer transfer
- Cu and oxide wafer bonding
• Technical challenges
Slide 20

Characterization of Cu-Cu Bonding
Interface
• Bonding strength determination, process yield
improvement
• Morphologies of bonding interface
Cu-Cu Cu Cu Bonding Experiment
Ta/Cu = 50nm/300nm
N 2 purge prior to bonding
Bonding Conditions = 400 o C / 30 min
Contact Pressure = 4000 mBar
Chamber Ambient = 1x10 -3 Torr
Post-Bonding Anneal = 400 o C / 30 min
Anneal Ambient = atm pressure with N 2 purge
Slide 21

Evolution of Morphologies During Bonding
Before bonding 30 min bonding 30 min bonding + 30 min N 2 anneal
• (111) orientation
• Clear interface
• (220) orientation
• Grain structure
• Grain size saturates after 30 min of
annealing
• Stable grain structures and bonded
layers are observed after further
annealing
(Chen et al., APL)
Slide 22

Morphology and strength map under different
bonding temperatures and annealing conditions.
Bonding /Annealing
Temperature
Bonding /Annealing Duration
(Chen et al, ECS Letters)
Slide 23

Handle Wafer
CVD Oxide
SOI
BOX
Oxide Wafer Bonding
5000Å Thermal oxide –
Protection against
KOH/TMAH
1 µm CVD OX – ILD, low
temperature process,
high deposition rate.
Schematic shows the bonding of thermal oxide
on a handle wafer to CVD oxide on an SOI
structure.
Slide 24

Can CVD Oxide bond to thermal oxide ?
We need …
• pre-bonding densification to prevent
out-gassing from CVD oxide during
bonding and annealing.
• CMP to smoothen the CVD oxide
surface.
• post-bonding annealing to enhance
the bond
Slide 25

Why do we need pre-bonding densification ?
Wafer pair without densification on PECVD oxide
Wafer pair with densification on PECVD oxide
[350 o C/16h pre-bonding anneal]
300 o C/6 h
post-bonding anneal
300 o C/6 h
post-bonding anneal
Voids
[Tan et al, APL, 82(16) 2003]
Slide 26

AFM surface roughness data
Oxide
LTO
PE-TEOS
PE-Silane
As deposited
Densified and CMP
As deposited
Densified and CMP
As deposited
Densified and CMP
Bare Silicon: 0.143 nm
Surface preparation
500 nm SiO2/Si: 0.273 nm
RMS Roughness (nm)
13.35
Mean and root-mean-square (RMS) roughness of wafers with different surfaces
preparations estimated from AFM. RMS roughness of

AFM scans
(a)as-deposited PE-Silane oxide.
(b) densified (350 o C/16h) and
polished PE-Silane oxide.
[Tan et al, APL, 82(16) 2003]
Slide 1

Wafer Bow (mm)
25
20
15
10
5
0
Wafer Bow
500nm SiO 2 /Si
LTO
PE-Silane
PE-TEOS
Silicon
0 20 40 60 80 100 120 140
Edge-to-edge Wafer Length (mm)
Wafer Bow < 25 um for successful bonding of 6” wafers.
[Tan et al, ECS Letters, accepted]
Slide 1

The importance of post-bonding annealing
Bond Strength (mJ/m 2 )
1000
800
600
400
200
0
0 2 4 6 8 10
Post-bond annealing time (h)
LTO
PE-Silane
PE-TEOS
Bonding strength of the bonded wafer pairs with
different CVD oxides at 300 o C.
[Tan et al, ECS Letters, accepted]
Slide 1

Bonding Strength (mJ/m 2 )
1000
800
600
400
200
Post-bonding anneal duration
0
0 2 4 6 8 10
Post-bond annealing time (h)
300 o C
250 o C
200 o C
Bonding strength does not increase significantly beyond 2-3
hours of post-bonding annealing. (Data from PE-TEOS oxide)
[Tan et al, ECS Letters, accepted]
Slide 2

Outline
• Background and Motivation
• 3-D Research at MIT
- Process flow: Silicon layer transfer
- Cu and oxide wafer bonding
• Technical challenges
Slide 3

Bonding Temperature = 400 o C
σ
Normal Stress (MPa)
1200
1000
800
600
400
200
0
-200
(1) D.E. Riemer, IEEE Trans. Components, Hybrids, and
Manufacturing Technology, 13(1), pp. 194-199, 1990.
(2) E. Suhir, J. Appl. Mechanics, 55, pp. 143-148, 1988.
(3) FEMLAB, Comsol, Inc.
Thermal Stress - Thin Films Normal Stress
FEMLAB
Riemer
Suhir
Si substrate
LOCOS
BOX
SOI
LOCOS
97 98 99 100 101 102 103
Cu
Vertical Distance (µm)
[Tan et al, submitted to IRPS 2005]
Slide 4

Interfacial Stress (MPa)
Thermal Stress - Thin Films Interfacial Stresses
0
-50
-100
-150
-200
Shear 2-3
Shear 3-4
Peel 2-3
Peel 3-4
4960 4970 4980 4990 5000
Distance (µm)
[Tan, unpublished]
Slide 5

Baseline oxide-oxide bond, top and bottom-heated
• Upon doubly-aligned heating, the temperature gradient becomes
even larger within the ILD
• Maximum temperature is at 312 o C
Heating elements
2000 A SOI
2000 A BOX
2 µm ILD
Bulk Si
[Fan, unpublished]
Slide 6

Basic Improvement with Cu-Cu bonding
• Maximum temperature is at 178 o C, a 43% decrease from 312 o C
Heating elements
2000 A SOI
2000 A BOX
6000 A Cu
2 µm ILD
Bulk Si
[Fan, unpublished]
Slide 7

Doubly-SOI, doubly-aligned heated structure
• Maximum temperature is at 197 o C, a +10% increase from 178 o C
just due to the higher thermal resistance of the lower SOI layer
Heating elements
2000 A SOI
2000 A BOX
6000 A Cu
2 µm ILD
2000 A SOI
2000 A BOX
BulK Si
[Fan, unpublished]
Slide 8

With Cu plane and two Cu vias
• Maximum temperature is at 160 o C, a 19% decrease from 197 o C
just due to two Cu vias
450
Heating elements
2000 A SOI
2000 A BOX
6000 A Cu
2 µm ILD
2000 A SOI
2000 A BOX
BulK Si
2 Cu vias:
[Fan, unpublished]
Slide 9

Thermal Management - Summary
• Preliminary FEM simulations show that,
- The addition of Cu planes in between active device layers
can offer a ~40% reduction in the maximum steady-state
temperature a two-layered 3-D structure
- The addition of Cu vias can offer an addition ~15-20 %
reduction in the system's maximum temperature
- The convergence and divergence of heat flux lines can be
tailored using either Cu planes or vias
• Work in progress
- Explore different layout designs in order to optimize the
performance of Cu plane / via heat extractors
- Verification of simulated results with a fabricated 3-D device
Slide 10

Evaluation of relative merits and process flows for
wafer-to-wafer, chip-to-wafer, and chip-to-chip 3-D
technologies
Throughput
Yield
Bond Quality
Availability of Tool
Post-bonding
processing
Wafer-to-Wafer
High
Low
Large area, prone
to defect
Production tools
available
Possible
Chip-to-Wafer
Low
High
Different areas,
needs careful
handling
Not readily
available
Extremely
challenging
Chip-to-Chip
Low
High
Smaller area, less
prone to defects
Not readily
available
Possible but more
challenging
[Fan and Tan]
Slide 11

Technical challenges needing further research
• Thermal Stress – thin films stresses due to
CTE mismatch.
• Thermal management – increased power
density and local heating.
• Maintaining device integrity –need to
preserve electrical integrity of devices and
circuits as a result of additional steps.
• Yield – Cumulative yield for wafer-to-wafer
bonding.
• Wafer bonding – bonding mechanism, bonding
parameters (temperature, pressure, wafer bow,
etc)
• Noise and crosstalk – coupling between
device layers.
• Orientation – face-to-face or back-to-face
bonding ?
Slide 12

Acknowledgement
1) DARPA
2) MARCO – Interconnect Focus Center
3) SRC
4) Applied Materials – Graduate Fellowship
(C.S. Tan)
Slide 13