DFM Tutorial Program

Munich – Germany – 11-13 September 2007
TUTORIALS
Monday, September 10 th
Design for Manufacturing: “Variability in UDSM Technologies’’
Theresianum - 0606
Organizer: Bernd Lemaitre, Infineon Technologies AG, Germany
Content: Since some years DFM covers a wide range of new techniques,
methodologies and tools that have to be considered during the design
phase within Ultra Deep Submicron Technologies to be successful in terms
of yield and manufacturability. However for the design community DFM is a
set of technologies and methodologies that help designer to extract
maximum value from silicon process technology and solve manufacturing
challenges as variability and leakage. Achieving the required time to market
with economically acceptable yield levels and maintaining them in volume
production has become a very challenging task in the most advanced
technology nodes. One of the primary reasons is the relative increase in
process variability in each generation.
In this tutorial we will present an overview of Yield Detractors and Variability
Sources in UDSM technologies, new methodologies and techniques within
circuit design and physical implementation, discuss the new role of the
Foundries in the DFM arena and show some practical examples to reduce
the sensitivity of designs on manufacturing variability.

Agenda:
Time Topic Speaker
9:00
Yield Detractors and Variability Sources in
UDSM Technologies
10:00 Impact of Variability on circuit design
11:00 Coffee Break
11:30
12:30 Lunch
13:45
14:45
Device degradation consumes margin of
DFM-window
DFM Enabling - foundry data, model, flow
and qualification
Best Practice for DFM during Physical
Implementation
15:30 Coffee Break
16:00 Variability aware SRAM design
Andrzej Strojwas,
CMU and PDF Solutions Inc., USA
Sani R. Nassif,
IBM Austin Research Laboratory, USA
Christian Schluender,
Infineon Technologies AG, Germany
K.K. Lin,
Chartered Semiconductor
Manufacturing Inc., Singapore
Hanno Melzner,
Infineon Technologies AG, Germany
Wim Dehaene,
KULeuven, Belgium

Abstracts:
Yield Detractors and Variability Sources in UDSM Technologies
Speaker: Andrzej Strojwas, CMU and PDF Solutions Inc., USA
Content: In the first part we will present benchmarking of yield loss components for
different product classes. We will briefly overview several approaches for
variability reduction in the design, yield ramp and volume manufacturing
phases.
Process variability sources can be categorized based on the spatial
hierarchy: lot-to-lot, wafer-to-wafer, within-wafer or within-die, or root
causes: random or systematic. These sources create a complicated
distribution of parameters that must be addressed by circuit designers.
This tutorial will describe a comprehensive study of the main sources of
variability and their effects on active devices, interconnect and ultimately
product performance and yield. In the older technology generations,
manufacturing yield loss was dominated by random defects. By the time
volume manufacturing started, systematic yield loss was typically
insignificant. This situation started to change rapidly at the 130nm
technology node in which the product layout systematic effects became
more critical. More recently, due to challenging product performance
requirements and increased process variability, parametric yield losses
have become significant as well.
Impact of Variability on circuit design
Speaker: Sani R. Nassif, IBM Austin Research Laboratory, USA
Content: In the second part of the tutorial, we will review all current work and results
on the modeling and characterization of variability, the impact on circuit
design and show some future impact trends for which research needs to
be underway now.
Manufacturing variability comes from multiple sources, some physical,
some environmental and some "informational". It can be random, pseudorandom,
or systematic, and can have complex spatial dependence. Finally,
it can have time scales that range from nanoseconds for certain types of
environmental noise to megaseconds for phenomena such as electromigration.
With all this rich behavior it is important that we invest in
understanding the sources, magnitude, temporal and spatial models,
characterization and methods for analysis of variability. We do this because
variability can impact circuit performance in many complex ways, and can
thus lead to unpredictability, which can also be understood to be a
mismatch between model and hardware.

Device degradation consumes margin of DFM-window
Speaker: Christian Schluender, Infineon Technologies AG, Germany
Content: In the third part we will investigate device degradation as a part of the
variability sources. To ensure the function of circuits the electrical
parameters of every device must not leave a specific window. This window
is not only specified by process variation but also by competing
mechanisms like device reliability. Degradation mechanisms like NBTI or
HCI lead to parameter drifts during lifetime adding on top of the process
variations and thereby shrinking the available margin. While for full-custom
design several possibilities are available to take reliability contribution into
account, for semi-custom designs a smart approach is necessary. The
close relationship between process variations and reliability degradation
can be utilized to consider reliability within a semi-custom design flow. For
e.g. checking critical time paths in semi-custom design, parameter shifts
are expressed as propagation-delays. After a brief introduction of NBTI and
HCI, different approaches for considering reliability on design level will be
presented.
DFM Enabling - foundry data, model, flow and qualification
Speaker: K.K. Lin, Chartered Semiconductor Manufacturing Inc., Singapore
Content: In the fourth part we will discuss the new foundry roles and contributions in
DFM. To facilitate DFM, foundries are opening up some of its
manufacturing data via encrypted process model kits. EDA tools, chosen
by the foundries and their customers, can read and allow simulation and
optimization of process-related issues during the design process.
Foundries, EDA companies and the design community are engaging in a
triple-win scenario to co-optimize the designs for better yield, lower power,
accurate timing and manufacturing-aware/compliant layouts. We will
present a spectrum of currently foundry-supported DFM tools. Modelbased
DFM tools that account for various manufacturing effects
(lithography, polishing, defect-density, etc.) will be covered. Integrated use
model and methodology will be discussed, including complementary usage
with traditional rule-based approach. Finally, a survey of future DFM tools
will also be given.
Best Practice for DfM during Physical Implementation
Speaker: Hanno Melzner, Infineon Technologies AG, Germany
Content: In the fifth part we will discuss and show examples for Best Practice for
DfM during physical implementation. Even in modern technologies and
ultra-clean fabs, particles will still be one of the main sources of yield loss
in the manufacturing of Integrated Circuits at least in the mature production
phase. Sensitivity of layouts to random defects can be measured,
analyzed, and – most importantly – improved in many ways. By stepping
through some real-world examples, we will identify typical areas of
improvement and – in this regard – review the theoretical foundations of
random defect yield modeling. Beyond random defects, a lot can be done
to make circuits more robust and improve yield. Although effects are often

Variability aware SRAM design
hard to predict and verify in this field, many measures are intuitively
beneficial and often even come at nearly zero cost. Again we will look at
some good and bad examples and try to extract some guiding principles
how to make robust layouts. Eventually, after the obvious and cheap has
been done, we are left with real trade-offs. One of the most important ones
is yield versus chip area. Although it is often thought that “smaller is better”
this is not always true. We will review the basic dependencies and finish
again with a practically relevant example – the optimization of memory
redundancy.
Speaker: Wim Dehaene, KULeuven, Belgium
Content: In the sixth part of the tutorial we will discuss SRAM design techniques for
robust design and handling of process variability. SRAMs are the first
digital circuits to suffer from the increased variability that comes with
advanced CMOS technology scaling to 90nm and beyond. In this
presentation it will be addressed how this variability can be, partially,
mitigated with circuit design techniques. First it will be shown how
variability can be taken into account during the design. Second memory
circuit improvements will be described that improve the robustness against
technological variability.

Biographies:
Bernd Lemaitre received the Diploma degree in Physics from Technical University
Darmstadt, Germany at the Institute of Nuclear Physics and the PHD in
Electronics from the University of Bundeswehr Munich, Germany in
1992. In 1985 he jointed Siemens AG, Semiconductor Division, now
Infineon Technology AG. He worked in the area of CAD, Technology
Development, Device Modeling and Technology Characterization. He
leads a simulation group with the main interest in Device Modeling for
enhanced CMOS Technologies. From 1998 to 2002 he holds the
position of the Vice Chairman of the international Compact Model
Council organized under the Electronic Industries Association (EIA).
Since 2002 he is working in the area of Yield Management and Design
for Manufacturing as Program Manager for 90nm and 65nm
Technologies.
Andrzej Strojwas has served as a technical advisor to PDF since the company's
founding, and was named its chief technologist in 1997. A Keithley
Professor of Electrical and Computer Engineering at Carnegie Mellon
University, Dr. Strojwas has held senior technical positions at Harris
Semiconductor Co., AT&T Bell Labs, Texas Instruments, NEC, Hitachi,
SEMATECH, and KLA-Tencor. In addition, Strojwas has consulted for
semiconductor companies, equipment vendors, and electronic design
automation companies in the area of statistically based CAD/CIM of
VLSI circuits. He holds an M.S. in Electronic Engineering from Warsaw
Technical University and a Ph.D. in Electrical Engineering from Carnegie
Mellon University.
Sani R. Nassif received his PhD from Carnegie-Mellon university in the eighties. He
worked for ten years at Bell Laboratories on various aspects of design
and technology coupling including device modeling, parameter
extraction, worst case analysis, design optimization and circuit
simulation. He joined the IBM Austin Research Laboratory in January
1996 where he is presently managing the tools and technology
department, which is focused on design/technology coupling and
includes activities in: model to hardware matching, simulation and
modeling, physical design, statistical modeling, statistical technology
characterization and similar areas.
Christian Schlünder has received his Dipl.-Ing. (1999) in electrical engineering focussing on
microelectronics from the University of Dortmund, Germany. From
1998-1999 he worked in a cooperative program between Siemens
Corporate Research Labs in Munich and the University of Dortmund in
the field of characterization, modelling, and reliability of analog CMOS
circuits.
After the founding of Infineon Technologies AG, he acted for a short
time as a technical consultant for Infineon, until he joined Infineon as a
member of the Corporate Research Department, where he was active in

esearch on hot carrier stress in mixed signal applications. Since 2000
he works in the Infineon Central Reliability Methodology Group and was
promoted to Staff Engineer last year. He manages process qualification
projects for various state-of-the-art CMOS-Technologies and evaluates
the reliability of innovative technologies like SOI, Strained Silicon,
MultiGate/FIN-FETs etc.
Besides, his main research work is in the area of NBTI. He has done his
doctoral thesis on this topic accompanying his regular work and
received his doctoral degree in 2006 from the University of Dortmund,
Germany. Some pending patents have originated from his work in the
area of reliability methodology. His current research is focussed on
NBTI recovery phenomena, where he and his colleagues develop new
reliability stress- and measurement-techniques.
Christian Schlünder has published several papers in various conference
proceedings and microelectronic journals. Additionally, he has
presented invited talks and tutorials at many conferences such as
‘IRPS’. He is frequently a member of the Technical Program Committee
of the IEEE-conferences ‘IRPS’, ‘IRW’ and referee of several IEEE
journals. Furthermore he is involved in JEDEC standards developments
K.K. Lin received his B. Sc., M. Sc. and Ph.D. degrees in Electrical Engineering
and Computer Science from the University of California at Berkeley. He
is currently a senior manager in Chartered US office. He has served in
engineering and management positions in Intel Corporation, Cadence,
HP since 1990. He had led and managed teams in Physical-design,
CAD and Tapeout-Operations for Intel 45/65/90/130nm microprocessor
products. His extensive hands-on development and customer-support
experience include DFM/RET/OPC, Layout migration/compaction,
Custom layouts, Full-chip integration/planning/place-route, and
Technology CAD (TCAD). He has published and served in
internal/external conferences.
Hanno Melzner received his diploma in physics from the Technical University Munich,
Munich, Germany, in 1986. His focus was on silicon micromechanics.
In 1987, he joined Siemens Semiconductors in Munich. He worked in
DRAM process integration, defect engineering, DRAM and logic
product engineering, sensor technology development, and yield
engineering mainly in Germany with extended delegations to USA and
UK. Currently, he is working in Infineon Technologies in the design
methodology group as a Principal for Yield Methodologies, with special
focus on Design for Manufacturing and defect-limited yield
improvement.
Wim Dehaene was born in Nijmegen, The Netherlands, in 1967. He received the M.
Sc. degree in electrical and mechanical engineering in 1991 from the
Katholieke Universiteit Leuven. In November 1996 he received the Ph.
D degree at the Katholieke Universiteit Leuven. His thesis is entitled
“CMOS integrated circuits for analog signal processing in hard disk
systems.”

After receiving the M. Sc. Degree Wim Dehaene was a research
assistant at the ESAT-MICAS Laboratory of the Katholieke Universiteit
Leuven. His research involved the design of novel CMOS building
blocks for hard disk systems. The research was first sponsored by the
IWONL (Belgian Institute for Science and Research in Industry and
agriculture) and later by the IWT (the Flemish institute for Scientific
Research in the Industry). In November 1996 Wim Dehaene joined
Alcatel Microelectronics, Belgium. There he was a senior project leader
for the feasibility, design and development of mixed mode Systems on
Chip. The application domains were telephony, xDSL and high speed
wireless LAN. In July 2002 Wim Dehaene joined the staff of the ESAT-
MICAS laboratory of the Katholieke Universiteit Leuven where he is now
a professor. His research domain is circuit level design of digital
circuits. The current focus is on ultra low power signal processing and
memories. Wim Dehaene is teaching several classes on digital circuit
and system design. Wim Dehaene is a senior member of the IEEE.