compact - TUM

High-Speed Digital CMOS Circuits 

73255 

Summer Term 2012 

Monday 8:00 – 9:30 

N5325 


Stephan Henzler 

1 

Technische Universität München Sumer Term 2012 

henzler@tum.de 

2 

Lecturer CV 

Stephan Henzler received the Dipl.-Ing. degree in 

electrical engineering in 2002, the Dr.-Ing. degree in 2006, 

and the habilitation 1 degree in 2010 from the Technische 

Universität München (TUM), Germany. From 2002 to 

2005, he was with the Institute for Technical Electronics, 

Technische Universität München, where he worked on 

low-power digital integrated circuit design and leakage 

reduction techniques. For his dissertation on power 

management and leakage reduction techniques he 

received the Rhode-und-Schwarz outstanding thesis 

award 2007. In 2005, he joined the Advanced Systems 

and Circuits Department of Infineon Technologies AG, 

Munich, where he worked on high-speed/highperformance 

digital integrated circuits, variability in deepsubmicron 

CMOS technologies, and mixed-signal circuit 

design in nanometer CMOS technologies, especially timeto-digital 

converters. In 2010 he joined the wireless mixedsignal 

department of Infineon where he works on mixedsignal 

system and circuit design. Since February 2011 he 

carries on the same responsibilities within Intel. 




Administratives 

Lecture: Stephan Henzler 

henzler@tum.de 

office hours by arrangement 

Nasim Pour Aryan (teaching assistant) 

n.aryan@tum.de 

Tutorials: embedded in lecture 

Exam: in written form, 60 minutes, after lecture cycle 

Language: english 



3 


1

Exam Schedule 

Suggested dates for the High-Speed Digital CMOS Circuits exam 



4 


Course and Online Material 

Handout with extended slides: 

– available for download prior to lecture 

Online material comprising 

– extended slides (1 per page and 3 per page) 

– video stream of past lectures 

www.lte.ei.tum.de/homes/henzler 


5 



Course Overview 

Logic families for high-speed and high-performance 

Register (flip-flop) design 

Clock generation and distribution 

– Phase/Delay Locked Loop 

– Frequency dividers 

Time-to-digital converters 

Arithmetic algorithms and macros for fast adders, 

multipliers, etc. 

Memory design 



6 


2

Literature 

Outline 

CMOS delay models 

– Elmore delay 

– Delay Minimization in buffer chain 

– Delay minimization of combinatorial logic 

Logical Effort methodology 

Static CMOS logic – Design considerations 

Dynamic Logic 



7 


Course Books: 

Recommended Literature I 

Rabaey, Chanddrakasan, Nikolic. 

Digital Integrated Circuits, A Design Perspective 

Weste, Harris. 

CMOS VLSI Design, A Circuits and System Perspective 

Kaeslin, 

Digital Integrated Circuit Design 

Ken, Martin. 

Digital Integrated Circuit Design 

Bernstein, Carrig, Durham, Hansen, Hogenmiller, Nowak, Rohrer. 

High Speed CMOS Design Styles 


8 



Phase-Locked Loops 

Razavi. 

RF-Microelectronics 

Recommended Literature II 

Time-to-Digital Converters: 

Henzler. 

Time-to-Digital Converters 

Arithmetic Circuits: 

Ercegovac, Lang. 

Digital Arithmetic 

Parhami. 

Computer Arithmetic, Algorithms and Hardware Design 



9 


3

Memory Circuits: 

Haraszi. 

CMOS Memory Circuits 

Recommended Literature III 

Low-Power: 

Henzler. 

Power Management of Digital Circuits in Deep Sub-Micron 

CMOS Technologies 

Latest material for all chapters: 

IEEE Xplore with TUM full library access 



10 


High-Speed Circuits 

Very high frequency, i.e. several GHz 

Considerable part of clock period consumed for 

synchronization, e.g. flip-flop delay t cpq, setup time t setup, and 

clock skew plus jitter t skew 

Limited time for logic only simple operations per cycle or 

pipeline stage, respectively 

Be aware of hold time violations! 


11 



High-Performance Circuits 

Moderate frequency, i.e. 300MHz – 2GHz 

Predominant part of clock period consumed for logic 

operations, small synchronization overhead 

Powerful operations possible within a single cycle/stage 

Despite long cycle time the timing is critical due to the long 

combinatorial paths between two flip-flop stages 

Be aware of setup time violations! 



12 


4

Logic Design for High-Performance 



13 


Static CMOS Logic 

Complementary pull-up and pulldown 

network: 

NMOS PMOS 

serial parallel connection 

Always low resistive connection to 

power supply (VDD or VSS) 

– full swing signals 

– noise and leakage tolerant 

– strong supply dependence of delay 

Inputs connected to n PMOS and n 

NMOS devices 

– input load ∝ 2n (large) 

– large internal load connected to output 


14 



Static CMOS Logic 2 

Handover between pull-up and pulldown 

during switching 

– cross current 

– medium speed 

– not ratioed 

Activity dependent power 

consumption 

Excellent modeling and EDA 

integration available 



15 


5

Literature 

Outline 







Dynamic Logic 



16 


Elmore Delay 

Prerequisites: 

– one input only 

– caps between network node and ground 

– no resistive loops 

W. C. Elmore, The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers, Journal of Applied Physics, 1948. 


17 



Elmore Delay (cont) 

There is exactly one path from a network node i to the input s. 

The sum of all resistances along this path is the path resistance 

R ii, e.g. R 44 = R 4 + R 3 + R 1. 

W. C. Elmore, The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers, Journal of Applied Physics, 1948. 



18 


6


The shared path resistance R ik is the sum of all resistances 

along the joint sub-path of the two paths s i and s k. 

Example: R i4 = R 1 + R 3 



19 


Elmore delay: 


First order approximation of the delay after which a voltage 

step at the input s can be observed at the output i. 


20 



Elmore delay: 


quite useful for 

– wire delay estimation 

– first order delay model of static and dynamic CMOS gates 

(RC model) 

(actually a transistor is not a resistor, excellent for qualitative understanding) 



21 


7

Load Dependence of Inverter 

electrical effort, effort 

fanout, (gain, fan-out) gain 

Linear load-delay dependence holds 

fairly good, even in deep sub-micron 

technologies. 



22 


Sizing of Super Buffer 

min. sized N - 1 unknown sizings 

Find inverter dimensions for minimum propagation delay. 

C 1 and C L given N-1 variables 

path electrical effort 


23 



Sizing of Super Buffer 2 

Minimize delay (i.e. search for optimum fanout h i): 

for optimum delay all fanouts need to be the same, 

i.e. h 1 = h 2 = h 3 = … = h N 



24 


8


The product of all fanouts is constant and given by the 

constraints, i.e. C 1 and C L: 

Minimum delay of an N-stage inverter chain (superbuffer): 

However, what is the optimum number of stages 



25 



Find optimum number of stages: 

normalized delay 

100 

80 

60 

40 

20 

(implicit equation for h i) 

H=50 

H=100 

H=200 

0 

0 1 2 3 

number of stages 

4 5 6 



Technische Universität München 

* Sometimes an optimal fan-out of e is reported . 

This follows from a similar derivation if the parasitic 

delay of the gate is neglected. 

26 

Sumer Term 2012 

Sizing of Combinatorial Logic 

Buffer chain is mainly an academic exercise. 

How can we size combinatorial logic for minimum delay? 

How many stages shall we use to realize a certain function? 

Logical Effort Methodology 

(a generalization of the preceding investigation) 



27 


9

Delay of Combinatorial Gate 

effort delay 

p parasitic delay, depends on logic, not sizing or load 

h electrical effort, depends on sizing and load not on log. func. 

g logical effort, depends on logic, not sizing 

Two equivalent definitions of logical effort g: 

gate capacitance 

1. gate cap. of ref. inverter when the gate is sized to deliver 

the same current than the reference inverter 

2. g describes how much worse the gate can deliver current to the load 

compared to an inverter when the gate is sized to provide the same 

input capacitance as the inverter. 



28 


Calculation of Logical Effort 

p = 2, g =4/3 


29 



Calculation of Logical Effort 

p = 7/3, g A = 2, g B = 2, g C = 5/3 



30 


10

Delay of High Fanin Gates 

Parasitic delay and logical effort of NAND gate 

(according to basic estimation of previous slides) 

inputs 2 3 4 5 6 8 n 

parasitic delay 2 3 4 5 6 8 n 

logical effort 4/3 5/3 2 7/3 8/3 10/3 (n+2)/3 

In reality parasitic delay increases nearly quadratically due to 

intermediate capacitances. 

Use Elmore delay or simulation for accurate parameter 

extraction. Linear delay model still quite good. 

p N = 1 

3 

 

N 2 + N 



31 


Delay of Combinatorial Paths 

The branching in combinatorial blocks increases the electrical 

effort by the branching effort b 

branching effort 


32 



Delay of Combinatorial Path 2 

determine optimum sizing in the same way than for buffers 

 

Define path effort: 

minimum delay can be estimated 

before sizing process is started! 



33 


11

Unequal Rising and Falling Delay 

Equal rise and fall delay is often disadvantageous for 

average delay (path delay is relevant for applications) and 

area consumption. 



34 


Add-On Material 

Unequal Rising and Falling Delay 

Logical effort methodology can be extended for independent 

rising and falling delays. 

Averaging along path, e.g. the sum of a slow pull-up and a 

fast pull-down can be smaller than two times a symmetrical 

delay same calculation with average delay 

optimum P/N ratio r: 


35 



Limitations of Logical Effort 

Logical effort methodology does … 

– Valuable rule of thumb for sizing of high performance paths 

– Predicts the optimum path delay /wo knowledge of sizing 

– Indicates how to distribute the gain along a critical path 

Logical effort methodology does not … 

– Take the slope dependence of gate delays into account 

(however, along the critical path slopes are very similar) 

– Consider simultaneous switching 

– Consider power, i.e. gives no sizing rule for sub-critical paths 

– Indicate how to size a path for small power and/or area 

– Interconnect delay 

– Branching is difficult to estimate, especially for parallel critical paths 



36 


12

Non-Linear Delay Model 

Linear delay model is suited very well for hand calculation 

and intuitive understanding how to size gates 

Linear delay model is not suited for high numerical accuracy 

Non-linear delay model for computer calculation 

– Define a set or relevant input slopes (transition times) 

– Define a set of relevant load capacitances 

– Perform SPICE simulation for each (load,slope) tupel 

– Measure propagation delay and output slope (transition time) 

and store results in 2-dimensional lookup table 

– Usually stored in the so called liberty-file 

Numerically accurate 

Not useful to understand trade-offs / derive design strategies 



37 


Example for Timing Description in LIB File 

pin(Z) { 

… 

timing() { 

related_pin : “X1”; 

timing () { 

cell_fall(slp_load) { 

index_1 (“0.010, 0.050”); (slope) 

index_2 (“0, 10, 50”); (load) 

values( “50, 150, 550”\ 

“60, 170, 610”); 

… 

Description tables like this are done for any timing figure, i.e. 

– delay from any input in both switching directions to the output 

– slope at the output in response to a switching event at any input 

– setup & hold times 

– … 


38 



Literature 

Outline 







Dynamic CMOS Logic 



39 


13

Input Dependence of Gate Delay 

simultaneous switching of inputs is worst case 



40 


Equalization of Gate Delay 

Layout is more complex, i.e. cell area is larger 

– makes only sense if functionality requires equal propagation delay 


41 



Asymmetric Gates 

speed requirements of 

one input relaxed 

– downsizing of slow 

branch 

– upsizing of low active 

series devices 

p Ad = 13/9, p Au = 13/9 

p Bd = 17/9, p Bu = 26/9 

g Ad = 10/9, g Au = 10/9 

g Bd = 5/3, g Bu = 10/3 



42 


14

Skewed Gates 

If one transition is much more critical than the other one the 

critical transition can be accelerated at the cost of the other one 

unskewed 

p = 1, g = 1 

skewed 

p u = 5/6, p d = 5/3, g u = 5/6, g d = 5/3 



43 


Dynamic Logic 

(Precharge Logic) 


44 



Low input & parasitic caps. 

No contention 

No static power consumption 

Extremely fast 

Wide NOR structures e.g. for 

decoders 

Dynamic Logic 

Sensitive to noise and leakage 

High dynamic power consumption 

Clocking required 

Monotonicity requirement 



45 


15

High Fanin Dynamic Gates 

Wide NOR Structures 

NOR operation is for free in single 

ended domino gate 

Wide OR structures cause significant 

leakage currents degrading the charge 

on the dynamic node keeper 



46 


Alternative for Wide NOR: Pseudo NMOS 

Cross current, acceptable e.g. if pulldown 

is exception or for high-speed 

applications 

Reduced swing (tradeoff between pullup 

speed and level reduction 

ratioed 


47 



High Fanin Dynamic Gates 

Long NAND Structures 

No contention 

Low load 

long NMOS pull-down chain possible 

but charge sharing is critical 



48 


16

Evolution of Power Consumption 

Sakurai, ISSCC 03 

Leakage currents 

became a significant 

component of power 

dissipation. 

Fortunately it is not thus 

serious 

Technology innovation 

can only decelerate this 

trend. 

Circuit innovation (sleep 

transistor scheme) 

reduces leakage in idle 

modules 



49 


Leakage Currents in Deep Sub-Micron MOSFETs: 

Classic Leakage Currents 

gate 

source drain 

1 

2 

Subthreshold current 

Junction leakage 

1 

bulk 


50 



Subthreshold Leakage 



51 


2 

17

Leakage Currents in Deep Sub-Micron MOSFETs: 

Tunneling Currents 

gate 

source drain 

1 

2 

1 

bulk 

Gate tunneling current 

Gate induced drain leakage 



52 


Noise and Leakage Sensitivity 


53 



2 

Leakage currents discharge 

dynamic node 

limited retention time 

minimum operation frequency 

(very disadvantageous for 

production test or low speed 

operation modes) 

Noise on power and signal wires 

opens pull-down paths weakly 

erroneous discharge of 

dynamic node 

Reduction of Noise & Leakage Sensitivity 

Weak keeper device compensates for leakage and noise 

induced discharge currents 

Size keeper for approximately 10% of discharge current 

5-10 % speed degradation 

No inversion 



54 


18

good device 

properties but 

large current 

Designing Weak Keepers 

weak keeper small W / L – ratio small W, large L? 

small current 

but strongly 

sensitive to 

variations 

small current 

but modeling of 

length dependence 

is difficult 

good keeper 

device 



55 


good keeper device but 

large output loading 

Design of Weak Keepers 2 

good keeper with reduced 

output loading 


56 



Adaptive Keepers 

With increasing process variations 

keeper design becomes difficult 

slow NMOS & fast PMOS: 

– keeper too strong 

– significant speed degradation 

fast NMOS & slow PMOS: 

– high leakage in pull-down path 

but small compensation current 

keeper too weak 

– erroneous discharge 

Steven Hsu, Intel, ISSCC 2006 



57 


19

Delayed Keeper 

Increasing leakage calls for stronger keepers 

delay penalty, advantage of dynamic circuits vanishes 

Concept: 

– Use small keeper which cannot compensate leakage completely 

– Enable strong keeper after evaluation/discharge is completed 

Challenge: Size permanent and delayed keeper such that 

leakage currents do not compromise logical decision 



58 


Charge Sharing in Dynamic Gates 

Charge sharing between 

cap of pre-charged node 

and intrinsic caps 

Eventually undefined 

levels and disturbance of 

subsequent stages 

Might be recovered by keeper 

Can be easily overlooked in simulation 

think about worst case situation 

Remedy: Precharge internal nodes with 

weak transistors 


59 



Multi-Output Dynamic Logic 

Domino gates can produce multiple logic functions (with 

common subterms) simultaneously 



60 


20

Compound Domino Logic 

Coupling inverters can be substituted by any static gate to 

reduce number of logic stages 



61 


Conditional Keeper 

Strongly low skewed 

CMOS gates with precharge 

Reduced contention 

No latching 

Also known as skewed 

CMOS 


62 



Clocking of Single-Rail Domino Circuits 

Sequential activation of logic stages 

High noise sensitivity 

High speed optimized clock skews variation sensitive 

Circuit becomes somehow “analog” 



63 


21

Clocking of Single-Rail Domino Circuits 2 



64 



Self timed evaluation (domino principle) 

Simultaneous pre-charge / evaluation 

Bypassing of stages possible 


65 






66 


22

Clocking of Footer-Less Domino Circuits 

No footer speed & power improvement 

Self timed 

Sequential pre-charge to avoid cross currents 



67 


Clocking of Footer-Less Domino Circuits 2 


68 



NORAce Domino Logic 

Alternating NMOS / PMOS Domino Gates 

pre-charged state disables all evaluation paths 

Self timed 

Noise sensitive 

No direct bypassing 



69 


23

NORAce Domino Logic 2 



70 


Cross Coupled Domino 

– A Dynamic Dual Rail Family – 

No contention 

Improved robustness 

Implicit inversion 

Higher clock load 

Complex wiring 

No wide NOR structures 


71 



Is it a good idea to use dynamic logic? 

Well, it‘s fancy 

Performance advantage vanishes in DSM technologies 

Many design pitfalls, e.g. charge sharing, leakage, noise 

Very susceptible to parasitics, PVT, etc. 

Weak EDA support, e.g. timing verification, 

poor verification 

Conclusion 

– Dynamic logic is a risk – Say No-No! 

– Dynamic logic is often the reason for redesigns 

– Avoid whenever possible 

– If you think its required, first seek for architectural loopholes, 

e.g. logic optimization, pipelining, parallelization … 

If you find no other way do it, but very carefully! 



72 


24

This is a industry wide 

consensus and trend 

Industrie‘s Oppineon 



73 


Legal Notice 

This lecture is recorded (audio, video, and slides) and 

streamed to the internet. 

By attending this lecture you agree that any question or 

comment that you give during the lecture is audible in the 

stream. You will not be visible unless you walk into the front 

part of the lecture room. Please keep out of this area during 

the lecture. 

If you want to ask a question or give comments which are not 

recorded, please consult the lecturer after the lecture or the 

teaching assistant during office hours. 

The availability of the electronic version is not guaranteed. 

Relevant for the exam is the attendance of the live lecture. 


74 



25

compact - TUM

Create successful ePaper yourself

Delete template?

Save as template?