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decimation filter Downsampling III Down-sampling requires, that there is no signal energy in between baseband and mirror spectra (e.g. noise) In general this is not the case, so down-sampling may cause aliasing To avoid aliasing a low pass filter is required in front of downsampling block Decimation Filter (Decimator) Stephan Henzler Mixed-Signal-Electronics 2012/13 36
Upsampling Stephan Henzler Mixed-Signal-Electronics 2012/13 imaging Additional information: Fractional sample rate conversion is up-sampling combined with down-sampling. Low-pass filters may be shared. Compute only what is necessary! 37
Page 1 and 2: Mixed-Signal-Electronics PD Dr.-Ing
Page 3 and 4: Stephan’s ambition for this cours
Page 5 and 6: Administratives Lecture: Stephan He
Page 7 and 8: The Macroscopic World is Purely Ana
Page 9 and 10: Topics of MSE Course Structure of
Page 11 and 12: Recommended Literature Analog Integ
Page 13 and 14: Constraints of Mixed Signal Circuit
Page 15 and 16: Generic Structure of Mixed-Signal S
Page 17 and 18: Representation of Discrete Time Sig
Page 19 and 20: Inverse Z-Transformation Methods f
Page 21 and 22: Representation of Discrete Time Sig
Page 23 and 24: low-pass low-pass low-pass Aliasing
Page 25 and 26: amplitude fsampling = 1 f signal,2
Page 27 and 28: Anti Aliasing Filter No brick wall
Page 29 and 30: Practical Sampling: Sample & Hold
Page 31 and 32: Xsh(!) = ¡ 1 j!¿ Sampling with Fi
Page 33 and 34: generalization X(s) = Relation Betw
Page 35: Downsampling II Mathematically dow
Page 39 and 40: Fractional Sample Rate Conversion
Page 41 and 42: Example for Simple Anti Aliasing Fi
Page 43 and 44: Transistor Description (for hand ca
Page 45 and 46: Chapter 2 Sample and Hold Circuits
Page 47 and 48: Sample & Hold Circuit Stephan Henzl
Page 49 and 50: Sample & Hold: Clock Feed-Through 3
Page 51 and 52: 5. 6. Clock jitter Sample & Hold Ci
Page 53 and 54: Impact of Jitter on S&H Performance
Page 55 and 56: Noise due to jitter: Jitter Effect
Page 57 and 58: S&H with Correlated Double Sampling
Page 59 and 60: Noise of Sampled Signals: kT/C-Nois
Page 61 and 62: Closed Loop Track & Hold Circuit 1
Page 63 and 64: Closed Loop Track & Hold Circuit 3
Page 65 and 66: Summary Sample & Hold Circuits Step
Page 67 and 68: Resistor Realizations in MOS Techno
Page 69 and 70: Resistor Realizations in MOS Techno
Page 71 and 72: Switched Capacitor Resistor Emulati
Page 73 and 74: Resistor Equivalents Stephan Henzle
Page 75 and 76: Parameter Variations in SC Circuits
Page 77 and 78: Implementation of Integrated Capaci
Page 79 and 80: Vertical Parallel Plate Capacitor S
Page 81 and 82: Limitations of SC-Equivalence Steph
Page 83 and 84: Limitations of SC-Equivalence Switc
Page 85 and 86: Switched Capacitor Integrators Step
Page 87 and 88:
z-Transformation Approximation on
Page 89 and 90:
Analysis of Switched-Capacitor Circ
Page 91 and 92:
Impact of Parasitic Capacitances C
Page 93 and 94:
Switched Capacitor Amplifier Stepha
Page 95 and 96:
SC Amplifier: Output Signal Stephan
Page 97 and 98:
Superposition Theorem in SC Circuit
Page 99 and 100:
Ideal Digital-to-Analog Conversion
Page 101 and 102:
DAC Gain Error Stephan Henzler Mixe
Page 103 and 104:
Ideal Analog-to-Digital Conversion
Page 105 and 106:
Quantization in A/D-Converters Step
Page 107 and 108:
Quantization in A/D-Converters Sig
Page 109 and 110:
ADC Gain Error Stephan Henzler Mixe
Page 111 and 112:
Non-Linearity in Data Converters St
Page 113 and 114:
Nonlinearity in Data-Converters Ste
Page 115 and 116:
DAC Nonlinearity: Differential Nonl
Page 117 and 118:
ADC Nonlinearity: Integral Nonlinea
Page 119 and 120:
Dynamic ADC Measurement ADC conver
Page 121 and 122:
Harmonic Distortion Caused by Nonli
Page 123 and 124:
Effective Number of Bits An ideal
Page 125 and 126:
Other Useful Figures in Mixed-Signa
Page 127 and 128:
Non-Linearity Gain Compression Co
Page 129 and 130:
Superposition of Two Frequencies St
Page 131 and 132:
Non-Linearity Cross Modulation Co
Page 133 and 134:
Non-Linearity Intermodulation Two
Page 135 and 136:
Non-Linearity: Further Reading Rec
Page 137 and 138:
Chapter 5 Nyquist Rate Digital-to-A
Page 139 and 140:
max value bus voltage follower stri
Page 141 and 142:
Elmore Delay (cont.): Path Resistan
Page 143 and 144:
Elmore Delay (cont): Delay Approxim
Page 145 and 146:
Stephan Henzler Mixed-Signal-Electr
Page 147 and 148:
Normalized Delay 300 250 200 150 10
Page 149 and 150:
Stephan Henzler Mixed-Signal-Electr
Page 151 and 152:
Monotonicity in Binary Weighted DAC
Page 153 and 154:
Implementation of Binary Weighted D
Page 155 and 156:
High number of bits - large area Hi
Page 157 and 158:
Page 159 and 160:
R-2R-Ladder Network Stephan Henzler
Page 161 and 162:
Page 163 and 164:
SC-Amplifier with Controllable Capa
Page 165 and 166:
Thermometer Code Converters (method
Page 167 and 168:
Hybrid Converter Architectures Step
Page 169 and 170:
Charge Scaling DAC Compatibel with
Page 171 and 172:
Analog-to-Digital Converter Familie
Page 173 and 174:
Dual-Slope Analog-to-Digital Conver
Page 175 and 176:
Iterative Analog-to-Digital Convert
Page 177 and 178:
Converter with Successive Approxima
Page 179 and 180:
Converter with Successive Approxima
Page 181 and 182:
Modified SAR Algorithm Stephan Henz
Page 183 and 184:
Charge Redistribution SAR Converter
Page 185 and 186:
Charge Redistribution SAR Converter
Page 187 and 188:
Hybrid SAR Converters Search can b
Page 189 and 190:
Detailed SAR Architecture Let’s
Page 191 and 192:
Binary Weighted SAR Stephan Henzler
Page 193 and 194:
Algorithmic Analog-to-Digital Conve
Page 195 and 196:
Page 197 and 198:
Illustration in Robertson Diagram 2
Page 199 and 200:
Page 201 and 202:
Voltage Doubling in Algorithmic Con
Page 203 and 204:
Voltage Doubling in Algorithmic Con
Page 205 and 206:
Pipelined ADC 1 Going for pipeline
Page 207 and 208:
High-Speed ADC: Pipeline Processing
Page 209 and 210:
Impact of Comparator Offset on ADC
Page 211 and 212:
Impairments in SAR Algorithms Find
Page 213 and 214:
Redundant SAR Algorithms Stage qua
Page 215 and 216:
Subranging Principle quantization e
Page 217 and 218:
Linear Model of Subranging ADC Step
Page 219 and 220:
Linear Model of Subranging ADC Eff
Page 221 and 222:
General Pipeline SAR ADC Stephan He
Page 223 and 224:
Background Calibration for Stage Ga
Page 225 and 226:
Summary Pipeline ADC Stage errors
Page 227 and 228:
implemented as parallel connection
Page 229 and 230:
thermometer code one-hot code trans
Page 231 and 232:
Bubble Correction in Flash Converte
Page 233 and 234:
Interpolating Flash Converter Steph
Page 235 and 236:
Kickback Effect Especially in flas
Page 237 and 238:
Folding ADC: Operation Principle St
Page 239 and 240:
High-Speed ADC: Parallel Processing
Page 241 and 242:
Chapter 7 Comparators Stephan Henzl
Page 243 and 244:
Static Characteristics of Comparato
Page 245 and 246:
Operational Amplifier as Comparator
Page 247 and 248:
Comparator Propagation Delay Linea
Page 249 and 250:
Track & Latch Circuit I Stephan Hen
Page 251 and 252:
Principle of Track-and-Latch Stage
Page 253 and 254:
Latched Comparators I Standard arc
Page 255 and 256:
Track & latch circuit: Latched Comp
Page 257 and 258:
Current Mode (CML) Latch Combines
Page 259 and 260:
Elimination of Memory Effect Prech
Page 261 and 262:
Chapter 8 Oversampled Converters Si
Page 263 and 264:
Linear Model of Quantization Noise
Page 265 and 266:
Quantization Noise and Oversampling
Page 267 and 268:
Feasibility of Oversampling Goal:
Page 269 and 270:
First Order Noise Shaping Stephan H
Page 271 and 272:
First Order Noise Shaping Stephan H
Page 273 and 274:
Calculation of Signal-to-Noise Rati
Page 275 and 276:
SC Implementation of 1. Order ΣΔ
Page 277 and 278:
Comparison Nyquist Rate vs. SD AD N
Page 279 and 280:
Calculation of Transfer Functions S
Page 281 and 282:
Simulation with Matlab/Simulink Ste
Page 283 and 284:
Output Spectrum of ΣΔ-Modulator f
Page 285 and 286:
Input Level Dependent SNR 2. Order
Page 287 and 288:
Tones Stephan Henzler Mixed-Signal-
Page 289 and 290:
Dithering Reduce the risk of tones
Page 291 and 292:
maximum noise peak Tones input DC l
Page 293 and 294:
STF of 3. Order ΣΔ-Modulator Step
Page 295 and 296:
Cascaded ΣΔ-Modulator (Multi stAg
Page 297 and 298:
3. Order MASH Structure Stephan Hen
Page 299 and 300:
hist(S1) 12000 10000 8000 6000 4000
Page 301 and 302:
hist(S1) 2.5 2 1.5 1 0.5 0 -1 -0.8
Page 303 and 304:
ΣΔ-Analog-to-Digital Conversion S
Page 305 and 306:
Sinc-Filter Basic low-pass filter a
Page 307 and 308:
Sinc Filter Transfer Functions Step
Page 309 and 310:
Implementation of Sinc-Filter Steph
Page 311 and 312:
ΣΔ-Digital-to-Analog Conversion S
Page 313 and 314:
Continuous Time Sigma-Delta Convert
Page 315 and 316:
Comparison of Discrete- and Continu
Page 317:
Web References Murmann. VLSI Data
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